// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// \omap3530\omap3530_assp\prcm.cpp

// Access to PRCM. And implimentation of device driver's power and clock control API

// This file is part of the Beagle Base port

//

#include <e32cmn.h>

#include <assp/omap3530_assp/omap3530_prcm.h>

#include <assp/omap3530_assp/omap3530_ktrace.h>

#include <assp/omap3530_assp/omap3530_irqmap.h>

#include <assp/omap3530_assp/omap3530_hardware_base.h>

#include <assp/omap3530_assp/omap3530_assp_priv.h>

#include <nkern.h>

#include "prcm_regs.h"

namespace Prcm

{

TSpinLock iLock(/*TSpinLock::EOrderGenericIrqLow0*/); // prevents concurrent access to the prcm hardware registers

void Panic( TPanic aPanic )

	{

	Kern::Fault( "PRCM", aPanic );

	}

void InternalPanic( TInt aLine )

	{

	Kern::Fault( "PRCMINT", aLine );

	}

FORCE_INLINE void _BitClearSet( TUint32 aRegister, TUint32 aClearMask, TUint32 aSetMask )

	{

	volatile TUint32* pR = (volatile TUint32*)aRegister;

	*pR = (*pR & ~aClearMask) | aSetMask;

	}

FORCE_INLINE void _LockedBitClearSet( TUint32 aRegister, TUint32 aClearMask, TUint32 aSetMask )

	{

	volatile TUint32* pR = (volatile TUint32*)aRegister;

	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);

	*pR = (*pR & ~aClearMask) | aSetMask;

	__SPIN_UNLOCK_IRQRESTORE(iLock, irq);

	}

EXPORT_C void SetPllConfig( TPll aPll, const TPllConfiguration& aConfig  )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::SetPllConfig(%x)", aPll ) );

	__ASSERT_DEBUG( (TUint)aPll < KSupportedPllCount, Panic( ESetPllConfigBadPll ) );

	const TPllControlInfo& inf = KPllControlInfo[ aPll ];

	__ASSERT_DEBUG( aConfig.iDivider <= KPllMaximumDivider,		Panic( ESetPllConfigBadDivider ) );

	__ASSERT_DEBUG( aConfig.iMultiplier <= KPllMaximumMultiplier,	Panic( ESetPllConfigBadMultiplier ) );

	__ASSERT_DEBUG( ((TUint)aConfig.iFreqRange <= EPllRange_1750_2100)

				&&  ((TUint)aConfig.iFreqRange >= EPllRange_075_100),	Panic( ESetPllConfigBadFreqRange ) );

	__ASSERT_DEBUG( ((TUint)aConfig.iRamp <= EPllRamp40us),	Panic( ESetPllConfigBadRamp ) );

	__ASSERT_DEBUG( (TUint)aConfig.iDrift <= EPllDriftGuardEnabled,	Panic( ESetPllConfigBadDrift ) );

	TUint	mult = (aConfig.iMultiplier bitand KPllMultiplierMask) << inf.iMultShift;

	TUint	div = ((aConfig.iDivider - 1) bitand KPllDividerMask) << inf.iDivShift;

	TUint	range = (aConfig.iFreqRange bitand KPllFreqRangeMask) << inf.iFreqSelShift;

	TUint	ramp = (aConfig.iRamp bitand KPllRampMask) << inf.iRampShift;

	TUint	drift = (aConfig.iDrift == EPllDriftGuardEnabled) ? (1 << inf.iDriftShift) : 0;

	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);

	// We must apply frequency range setting before new multuplier and divider

	TUint clearMaskConfig =			(KPllFreqRangeMask << inf.iFreqSelShift)

							bitor	(KPllRampMask << inf.iRampShift)

							bitor	(1 << inf.iDriftShift);

	_BitClearSet( inf.iConfigRegister, clearMaskConfig, range | ramp | drift );

	TUint clearMaskMulDiv =	(KPllMultiplierMask << inf.iMultShift) bitor (KPllDividerMask << inf.iDivShift);

	_BitClearSet( inf.iMulDivRegister, clearMaskMulDiv, mult | div );

	__SPIN_UNLOCK_IRQRESTORE(iLock, irq);

	}

EXPORT_C void PllConfig( TPll aPll, TPllConfiguration& aConfigResult )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::PllConfig(%x)", aPll ) );

	__ASSERT_DEBUG( (TUint)aPll < KSupportedPllCount, Panic( EGetPllConfigBadPll ) );

	const TPllControlInfo& inf = KPllControlInfo[ aPll ];

	TUint32 config = AsspRegister::Read32( inf.iConfigRegister );

	TUint32 muldiv = AsspRegister::Read32( inf.iMulDivRegister );

	aConfigResult.iMultiplier =	(muldiv >> inf.iMultShift) bitand KPllMultiplierMask;

	aConfigResult.iDivider =	1 + ((muldiv >> inf.iDivShift) bitand KPllDividerMask);

	aConfigResult.iFreqRange =	static_cast<TPllFrequencyRange>((config >> inf.iFreqSelShift) bitand KPllFreqRangeMask);

	aConfigResult.iRamp =		static_cast<TPllRamp>((config >> inf.iRampShift ) bitand KPllRampMask);

	aConfigResult.iDrift =		(config >> inf.iDriftShift ) bitand 1 ? EPllDriftGuardEnabled : EPllDriftGuardDisabled;

	__KTRACE_OPT( KPRCM, Kern::Printf( "DPLL%d: m=%d, d=%d, fr=%d, r=%d, dr=%d",

						aPll + 1,

						aConfigResult.iMultiplier,

						aConfigResult.iDivider,

						aConfigResult.iFreqRange,

						aConfigResult.iRamp,

						aConfigResult.iDrift ) );

	}

EXPORT_C void SetPllLp( TPll aPll, TLpMode aLpMode )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::SetPllLp(%x)", aPll ) );

	__ASSERT_DEBUG( (TUint)aPll < KSupportedPllCount, Panic( ESetPllLpBadPll ) );

	__ASSERT_DEBUG( (aLpMode == ENormalMode)

					|| (aLpMode == ELpMode), Panic( ESetPllLpBadMode ) );

	const TPllControlInfo& inf = KPllControlInfo[ aPll ];

	TUint32 clear = 1 << inf.iLpShift;

	TUint32 set = 0;

	if( ELpMode == aLpMode )

		{

		set = clear;

		clear = 0;

		}

	_LockedBitClearSet( inf.iConfigRegister, clear, set );

	}

EXPORT_C TLpMode PllLp( TPll aPll )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::PllLp(%x)", aPll ) );

	__ASSERT_DEBUG( (TUint)aPll < KSupportedPllCount, Panic( EGetPllLpBadPll ) );

	const TPllControlInfo& inf = KPllControlInfo[ aPll ];

	TUint32 config = AsspRegister::Read32( inf.iConfigRegister );

	if( 0 == ((config >> inf.iLpShift) bitand 1) )

		{

		return ENormalMode;

		}

	else

		{

		return ELpMode;

		}

	}

EXPORT_C void SetPllMode( TPll aPll, TPllMode aPllMode )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::SetPllMode(%x;%x)", aPll, aPllMode ) );

	__ASSERT_DEBUG( (TUint)aPll <= EDpll5, Panic( ESetPllModeBadClock ) );

	TUint32 newMode;

	TUint32 newAuto = KPllAutoOff;

	switch( aPllMode )

		{

		default:

			__DEBUG_ONLY( Panic( ESetPllModeBadMode ) );

			return;

		case EPllStop:

			newMode = KPllModeStop;

			break;

		case EPllBypass:

			newMode = KPllModeBypass;

			break;

		case EPllAuto:

			newAuto = KPllAutoOn;

			// fall through...

		case EPllRun:

			newMode = KPllModeLock;

			break;

		case EPllFastRelock:

			newMode = KPllModeFastRelock;

			break;

		}

	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);

	_BitClearSet(	KPllMode[ aPll ].iModeRegister,

					KPllModeMask << KPllMode[ aPll ].iModeShift,

					newMode << KPllMode[ aPll ].iModeShift );

	_BitClearSet(	KPllMode[ aPll ].iAutoRegister,

					KPllAutoMask << KPllMode[ aPll ].iAutoShift,

					newAuto << KPllMode[ aPll ].iAutoShift );

	__SPIN_UNLOCK_IRQRESTORE(iLock, irq);

	}

EXPORT_C TPllMode PllMode( TPll aPll )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::PllMode(%x)", aPll ) );

	__ASSERT_DEBUG( (TUint)aPll <= EDpll5, Panic( ESetPllModeBadClock ) );

	TUint32 mode = (AsspRegister::Read32( KPllMode[ aPll ].iModeRegister ) >> KPllMode[ aPll ].iModeShift) bitand KPllModeMask;

	TUint32 autoSet = (AsspRegister::Read32( KPllMode[ aPll ].iAutoRegister ) >> KPllMode[ aPll ].iAutoShift) bitand KPllAutoMask;

	static const TPllMode modeTable[8][2] =

		{	// auto disabled	auto enabled

			{ EPllStop,			EPllStop },	// not possible

			{ EPllStop,			EPllStop },

			{ EPllStop,			EPllStop },	// not possible

			{ EPllStop,			EPllStop },	// not possible

			{ EPllStop,			EPllStop },	// not possible

			{ EPllBypass,		EPllBypass },

			{ EPllFastRelock,	EPllAuto },

			{ EPllRun,			EPllAuto },

		};

	return modeTable[ mode ][ (KPllAutoOff == autoSet) ? 0 : 1 ];

	}

EXPORT_C void CalcPllFrequencyRange( TPll aPll, TPllConfiguration& aConfig )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::CalcPllFrequencyRange(%x)", aPll ) );

	struct TFreqSelRange

		{

		TUint	iMin;

		TUint	iMax;

		TPllFrequencyRange	iSetting;

		};

	const TFreqSelRange KRanges[] =

		{

			{ 750000,	1000000,	EPllRange_075_100 },

			{ 1000001,	1250000,	EPllRange_100_125 },

			{ 1250001,	1500000,	EPllRange_125_150 },

			{ 1500001,	1750000,	EPllRange_150_175 },

			{ 1750001,	2100000,	EPllRange_175_210 },

			{ 7500000,	10000000,	EPllRange_750_1000 },

			{ 10000001,	12500000,	EPllRange_1000_1250 },

			{ 12500001,	15000000,	EPllRange_1250_1500 },

			{ 15000001,	17500000,	EPllRange_1500_1750 },

			{ 17500001,	21000000,	EPllRange_1750_2100 },

			{ 0,		0,			EPllRange_1750_2100	}

		};

	// We have to work out the internal frequency from the source clock frequency and the

	// divider factor N

	const TUint32 divider =	aConfig.iDivider;

	TInt found = -1;

	if( divider > 0 )

		{

		TUint fInternal = ClockFrequency( EClkSysClk ) / divider;

		// Find an appropriate range

		for( TInt i = 0; KRanges[i].iMax > 0; ++i )

			{

			if( fInternal < KRanges[i].iMin )

				{

				// We've passed all possible ranges, work out whether current or previous is nearest

				__DEBUG_ONLY( Panic( EPllInternalFrequencyOutOfRange ) );

				if( i > 0 )

					{

					// How near are we to minimum of current range?

					TUint currentDiff = KRanges[i].iMin - fInternal;

					// How near are we to maximum of previous range?

					TUint prevDiff = fInternal - KRanges[i - 1].iMax;

					found = (prevDiff < currentDiff) ? i - 1 : i;

					}

				else

					{

					// it's below minimum, so use minimum range

					found = 0;

					}

				break;

				}

			else if( (KRanges[i].iMin <= fInternal) && (KRanges[i].iMax >= fInternal) )

				{

				found = i;

				break;

				}

			}

		}

	// If we've fallen off end of list, use maximum setting

	__ASSERT_DEBUG( found >= 0, Panic( EPllInternalFrequencyOutOfRange ) );

	aConfig.iFreqRange = (found >= 0) ? KRanges[ found ].iSetting : EPllRange_1750_2100;

	}

EXPORT_C void AutoSetPllLpMode( TPll aPll )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::PllMode(%x)", aPll ) );

	__ASSERT_DEBUG( (TUint)aPll <= EDpll5, Panic( ESetPllModeBadClock ) );

	const TUint32 reg = KPllControlInfo[ aPll ].iConfigRegister;

	const TUint shift = KPllControlInfo[ aPll ].iLpShift;

	TUint freq = ClockFrequency( KPllToClock[ aPll ] );

	TUint32 clear = 1 << shift;

	TUint32 set = 0;

	if( freq <= KPllLpModeMaximumFrequency )

		{

		// LP mode can be enabled

		set = clear;

		clear = 0;

		}

	_LockedBitClearSet( reg, clear, set );

	}

EXPORT_C TBool PllIsLocked( TPll aPll )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::PllIsLocked(%x)", aPll ) );

	__ASSERT_DEBUG( (TUint)aPll <= EDpll5, Panic( EPllIsLockedBadPll ) );

	TUint32 reg = KPllControlInfo[ aPll ].iStatusRegister;

	TUint32 lockMask = 1 << KPllControlInfo[ aPll ].iLockBit;

	return ( 0 != (AsspRegister::Read32( reg ) bitand lockMask) );

	}

EXPORT_C void WaitForPllLock( TPll aPll )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::WaitForPllLock(%x)", aPll ) );

	__ASSERT_DEBUG( (TUint)aPll <= EDpll5, Panic( EWaitForPllLockBadPll ) );

	TUint32 reg = KPllControlInfo[ aPll ].iStatusRegister;

	TUint32 lockMask = 1 << KPllControlInfo[ aPll ].iLockBit;

	while( 0 == (AsspRegister::Read32( reg ) bitand lockMask) );

	}

EXPORT_C void SetPllBypassDivider( TPll aPll, TBypassDivider aDivider )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::SetPllBypassDivider(%x;%x)", aPll, aDivider ) );

	__ASSERT_DEBUG( (TUint)aPll <= EDpll5, Panic( ESetPllBypassDividerBadPll ) );

	__ASSERT_DEBUG( (TUint)aDivider <= EBypassDiv4, Panic( ESetPllBypassDividerBadDivider ) );

	static const TUint8 KLookupTable[] =

		{

		1,	// EBypassDiv1

		2,	// EBypassDiv2

		4.	// EBypassDiv4

		};

	TUint32 div = KLookupTable[ aDivider ];

	switch( aPll )

		{

		case EDpll1:

			_LockedBitClearSet( KCM_CLKSEL1_PLL_MPU, KBit19 | KBit20 | KBit21, div << 19 );

			break;

		case EDpll2:

			_LockedBitClearSet( KCM_CLKSEL1_PLL_IVA2, KBit19 | KBit20 | KBit21, div << 19 );

			break;

		default:

			break;

		}

	}

EXPORT_C TBypassDivider PllBypassDivider( TPll aPll )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::PllBypassDivider(%x)", aPll ) );

	__ASSERT_DEBUG( (TUint)aPll <= EDpll5, Panic( EPllBypassDividerBadPll ) );

	TUint div = 1;

	switch( aPll )

		{

		case EDpll1:

			div = (AsspRegister::Read32( KCM_CLKSEL1_PLL_MPU ) >> 19) bitand 0x7;

			break;

		case EDpll2:

			div = (AsspRegister::Read32( KCM_CLKSEL1_PLL_IVA2 ) >> 19) bitand 0x7;

			break;

		default:

			break;

		}

	TBypassDivider result = EBypassDiv1;

	if( 2 == div )

		{

		result = EBypassDiv2;

		}

	else if( 4 == div )

		{

		result = EBypassDiv4;

		}

	return result;

	}

EXPORT_C void SetDivider( TClock aClock, TUint aDivide )

	{

	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::SetDivider(%x;%x)", aClock, aDivide ) );

	__ASSERT_DEBUG( (TUint)aClock < KSupportedClockCount, Panic( ESetDividerBadClock ) );

	const TDividerInfo&	inf = KDividerInfo[ aClock ];

	TUint32 div = aDivide;	// most common case, special cases handled below

	switch( inf.iDivType )

		{

		case EDivUsimClk:

			// Special case, not suppored by this function - use SetUsimClockDivider()

			return;

		default:

		case EDivNotSupported:

			Panic( ESetDividerUnsupportedClock );

			return;

		case EDiv_1_2:

			if( (1 != aDivide ) && (2 != aDivide ) )

				{

				__DEBUG_ONLY( Panic( ESetDividerBadDivider ) );

				return;

				}

			break;

		case EDivCore_1_2_4:

			if( (1 != aDivide ) && (2 != aDivide ) && (3 != aDivide) )

				{

				__DEBUG_ONLY( Panic( ESetDividerBadDivider ) );

				return;

				}

			break;

		case EDivCore_3_4_6_96M:

			{

			switch( aDivide )

				{

				default:

					__DEBUG_ONLY( Panic( ESetDividerBadDivider ) );

					return;

				case 3:

					div = 0;

					break;

				case 4:

					div = 1;

					break;

				case 6:

					div = 2;

					break;

				case 0:

					// Special-case, use 96MHz clock

					div = 3;

					break;

				}

			break;

			}

		case EDivPll_1_To_16:

			if( (aDivide < 1) || (aDivide > 16) )

				{

				__DEBUG_ONLY( Panic( ESetDividerBadDivider ) );

				return;

				}

			break;

		case EDivPll_1_To_31:

			if( (aDivide < 1) || (aDivide > 16) )

				{

				__DEBUG_ONLY( Panic( ESetDividerBadDivider ) );

				return;

				}

			break;

		case EDivClkOut_1_2_4_8_16:

			{

			switch( aDivide )

				{

				default:

					__DEBUG_ONLY( Panic( ESetDividerBadDivider ) );

					return;

				case 1:

					div = 0;

					break;

				case 2:

					div = 1;

					break;

				case 4:

					div = 2;

					break;

				case 8:

					div = 3;

					break;

				case 16:

					div = 4;

					break;

				}

			break;