FCL/sf/adapt/beagleboard: comparison omap3530/omap3530

equal deleted inserted replaced

-:b7e488c49d0d
+:117faf51deac
 		{ KCM_CLKSEL_CORE,			KBit0 | KBit1,					EDiv_1_2,			0 },	// EClkL3Domain,
 		{ KCM_CLKSEL_CORE,			KBit2 | KBit3,					EDiv_1_2,			2 },	// EClkL4Domain,
 		{ KCM_CLKSEL1_PLL_MPU,		KBit19 | KBit20 | KBit21,		EDivCore_1_2_4,		19 },	// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency
 		{ KCM_CLKSEL1_PLL_IVA2,		KBit19 | KBit20 | KBit21,		EDivCore_1_2_4,		19 },	// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency
 		{ KCM_CLKSEL_WKUP,			KBit1 | KBit2,					EDiv_1_2,			1 },	// EClkRM_F,	///< Reset manager functional clock
 		{ KCM_CLKSEL3_PLL,			0x1F,							EDivPll_1_To_16,	0 },	// EClk96M		///< 96MHz clock
 		{ KCM_CLKSEL5_PLL,			0x1F,							EDivPll_1_To_16,	0 },	// EClk120M		///< 120MHz clock
 		{ KCM_CLKOUT_CTRL,			KBit3 | KBit4 | KBit5,			EDivClkOut_1_2_4_8_16,	3 },	// EClkSysOut
 		// Functional clocks
 		{ { KDummy, 0, 0, 0 },							{ KCM_CLKSTCTRL_CORE, KBit0 | KBit1, KBit0 | KBit1, 0 } },		// EClkL3Domain,
 		{ { KDummy, 0, 0, 0 },							{ KCM_CLKSTCTRL_CORE, KBit2 | KBit3, KBit2 | KBit3, 0 } },	// EClkL4Domain,
 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency
 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency
 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkRM_F,			///< Reset manager functional clock
 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk96M,			///< 96MHz clock
 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk120M,			///< 120MHz clock
 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkSysOut,
 	// Functional clocks
 		{ { KCM_FCLKEN_PER, KBit1, KBit1, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP3_F,
 		{ { KCM_FCLKEN_PER, KBit2, KBit2, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP4_F,
 		{ { KCM_FCLKEN1_CORE, KBit10, KBit10, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP5_F,
 		{ { KCM_FCLKEN1_CORE, KBit18, KBit18, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi1_F,
 		{ { KCM_FCLKEN1_CORE, KBit19, KBit19, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi2_F,
-		{ { KCM_FCLKEN1_CORE, KBit20, KBit20, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi3_F,
+		{ { KCM_FCLKEN1_CORE, KBit20, KBit20, 0 },	{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkMcSpi3_F,
-		{ { KCM_FCLKEN1_CORE, KBit21, KBit21, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi4_F,
+		{ { KCM_FCLKEN1_CORE, KBit21, KBit21, 0 },	{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkMcSpi4_F,
 		{ { KCM_FCLKEN1_CORE, KBit15, KBit15, 0},	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkI2c1_F,
 		{ { KCM_FCLKEN1_CORE, KBit16, KBit16, 0},	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkI2c2_F,
 		{ { KCM_FCLKEN1_CORE, KBit17, KBit17, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkI2c3_F,
 		{ { KCM_FCLKEN1_CORE, KBit13, KBit13, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUart1_F,
 		{ { KCM_FCLKEN1_CORE, KBit14, KBit14, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUart2_F,
 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkL3Domain,
 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkL4Domain,
 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency
 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency
 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkRM_F,			///< Reset manager functional clock
 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClk96M,			///< 96MHz clock
 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClk120M,			///< 120MHz clock
 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSysOut,
 	// Functional clocks
 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkL3Domain,
 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkL4Domain,
 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency
 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency
 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkRM_F,			///< Reset manager functional clock
 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClk96M,			///< 96MHz clock
 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClk120M,			///< 120MHz clock
 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSysOut,
 	// Functional clocks
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkL3Domain,
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkL4Domain,
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkRM_F,			///< Reset manager functional clock
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClk96M,			///< 96MHz clock
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClk120M,			///< 120MHz clock
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSysOut,
 	// Functional clocks
 		{ KPM_WKDEP_USBHOST,	{1,	0,		2,		-1,		-1,		4	} },		// EClkUsb_I,			///< USB host interface clock
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClk48M
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClk12M
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSysClk
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkAltClk
 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSysClk32k
 		// REGISTER			MPU		CORE	IVA2	PER		DSS		WAKE
 	};
 		{ KCM_CLKSEL_PER, KBit2 },	//	EGpt4,
 		{ KCM_CLKSEL_PER, KBit3 },	//	EGpt5,
 		{ KCM_CLKSEL_PER, KBit4 },	//	EGpt6,
 		{ KCM_CLKSEL_PER, KBit5 },	//	EGpt7,
 		{ KCM_CLKSEL_PER, KBit6 },	//	EGpt8,
 		{ KCM_CLKSEL_PER, KBit7 },	//	EGpt9,
 		{ KCM_CLKSEL_CORE, KBit6 },	//	EGpt10,
 		{ KCM_CLKSEL_CORE, KBit7 },	//	EGpt11,
 		{ KDummy, 0 },			//	EGpt12	- clocked from security block
 	};
 		{ EDuplicate,	Prcm::EClkSysClk32k },					// EClkGpio3_F,
 		{ EDuplicate,	Prcm::EClkSysClk32k },					// EClkGpio4_F,
 		{ EDuplicate,	Prcm::EClkSysClk32k },					// EClkGpio5_F,
 		{ EDuplicate,	Prcm::EClkSysClk32k },					// EClkGpio6_F,
 		{ EDuplicate,	Prcm::EClk120M },		// EClkUsb120_F,
 		{ EDuplicate,	Prcm::EClk48M },		// EClkUsb48_F,
 	// Interface clocks
 		{ EDuplicate,	Prcm::EClkL4Domain },		// EClkDss_I,
 		{ EDuplicate,	Prcm::EClkL4Domain },		// EClkCam_I,
 		{ },					// EClkIcr_I,
 			newMode = KPllModeFastRelock;
 			break;
 		}
 	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);
 	_BitClearSet(	KPllMode[ aPll ].iModeRegister,
 					KPllModeMask << KPllMode[ aPll ].iModeShift,
 					newMode << KPllMode[ aPll ].iModeShift );
 	_BitClearSet(	KPllMode[ aPll ].iAutoRegister,
 					KPllAutoMask << KPllMode[ aPll ].iAutoShift,
 					newAuto << KPllMode[ aPll ].iAutoShift );
 	__SPIN_UNLOCK_IRQRESTORE(iLock, irq);
 	}
 EXPORT_C TPllMode PllMode( TPll aPll )
 	__ASSERT_DEBUG( (TUint)aPll <= EDpll5, Panic( ESetPllModeBadClock ) );
 	TUint32 mode = (AsspRegister::Read32( KPllMode[ aPll ].iModeRegister ) >> KPllMode[ aPll ].iModeShift) bitand KPllModeMask;
 	TUint32 autoSet = (AsspRegister::Read32( KPllMode[ aPll ].iAutoRegister ) >> KPllMode[ aPll ].iAutoShift) bitand KPllAutoMask;
 	static const TPllMode modeTable[8][2] =
 		{	// auto disabled	auto enabled
 			{ EPllStop,			EPllStop },	// not possible
 			{ EPllStop,			EPllStop },
 			{ EPllStop,			EPllStop },	// not possible
 			{ EPllStop,			EPllStop },	// not possible
 EXPORT_C TBypassDivider PllBypassDivider( TPll aPll )
 	{
 	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::PllBypassDivider(%x)", aPll ) );
 	__ASSERT_DEBUG( (TUint)aPll <= EDpll5, Panic( EPllBypassDividerBadPll ) );
 	TUint div = 1;
 	switch( aPll )
 		{
 		case EDpll1:
 	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::SetDivider(%x;%x)", aClock, aDivide ) );
 	__ASSERT_DEBUG( (TUint)aClock < KSupportedClockCount, Panic( ESetDividerBadClock ) );
 	const TDividerInfo&	inf = KDividerInfo[ aClock ];
 	TUint32 div = aDivide;	// most common case, special cases handled below
 	switch( inf.iDivType )
 		{
 		case EDivUsimClk:
 			break;
 			}
 		}
 	// if we get here, we have a valid divider value
 	_LockedBitClearSet( inf.iRegister, inf.iMask, div << inf.iShift );
 	}
 EXPORT_C TUint Divider( TClock aClock )
 	{
 	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::Divider(%x)", aClock ) );
 	__ASSERT_DEBUG( (TUint)aClock < KSupportedClockCount, Panic( EGetDividerBadClock ) );
 	const TDividerInfo&	inf = KDividerInfo[ aClock ];
 	TUint32 div = ( AsspRegister::Read32( inf.iRegister ) bitand inf.iMask ) >> inf.iShift;
 	TUint result = div;	// most common case
 	switch( inf.iDivType )
 		{
 	__KTRACE_OPT( KPRCM, Kern::Printf( "Prcm::SetPowerDomainMode(%x;%x)", aDomain, aMode ) );
 	__ASSERT_DEBUG( (TUint)aDomain < KSupportedPowerDomainCount, Panic( ESetDomainModeBadDomain ) );
 	__ASSERT_DEBUG( (TUint)aMode <= EPowerOn, Panic( ESetDomainModeBadMode ) );
 	__ASSERT_DEBUG( 0 != (KPowerDomainControl[ aDomain ].iAllowedMask bitand (1 << aMode)), Panic( ESetDomainModeUnsupportedMode ) );
 	TUint shift = KPowerDomainControl[ aDomain ].iShift;
 	_LockedBitClearSet( KPowerDomainControl[ aDomain ].iRegister,
 						KPowerModeMask << shift,
 						aMode << shift );
 	__ASSERT_DEBUG( (TUint)aClock <= (TUint)KSupportedClockCount, Panic( EAddDomainBadClock ) );
 	__ASSERT_DEBUG( (TUint)aDomain <= (TUint)KSupportedWakeupDomainCount, Panic( EAddDomainBadDomain ) );
 	const TWakeupDomainInfo& inf = KClockWakeupDomainTable[ aClock ];
 	TUint32 mask = 1 << (TUint)inf.iBitNumber[ aDomain ];	// unsupported bit numbers will result in a mask of 0x00000000
 	_LockedBitClearSet( inf.iRegister, KClearNone, mask );
 	}
 EXPORT_C void RemoveFromWakeupDomain( TClock aClock, TWakeupDomain aDomain )
 	{
 	__ASSERT_DEBUG( (TUint)aClock <= (TUint)KSupportedClockCount, Panic( ERemoveDomainBadClock ) );
 	__ASSERT_DEBUG( (TUint)aDomain <= (TUint)KSupportedWakeupDomainCount, Panic( ERemoveDomainBadDomain ) );
 	const TWakeupDomainInfo& inf = KClockWakeupDomainTable[ aClock ];
 	TUint32 mask = 1 << (TUint)inf.iBitNumber[ aDomain ];	// unsupported bit numbers will result in a mask of 0x00000000
 	_LockedBitClearSet( inf.iRegister, mask, KSetNone );
 	}
 EXPORT_C TBool IsInWakeupDomain( TClock aClock, TWakeupDomain aDomain )
 	{
 			case EDiv4:
 				div *= 4;
 				break;
 			}
 		currentClock = prevClock;
 		}	// end do
 	// When we reach here we have worked back to the origin clock
 	TUint64 fSrc;
 	const Omap3530Assp* variant = (Omap3530Assp*)Arch::TheAsic();
 	if( EClkSysClk == currentClock )
 		{
 	}
 /** Get the currently configured SysClk frequency */
 EXPORT_C TSysClkFrequency SysClkFrequency()
 	{
 	switch( AsspRegister::Read32( KPRM_CLKSEL ) bitand (KBit0 | KBit1 | KBit2) )
 		{
 		case 0:
 			return ESysClk12MHz;
 		case 1:
 	SetClockState( EClkMcSpi2_F, EClkOff );
 	SetClockState( EClkMcSpi2_I, EClkOff );
 	r = AsspRegister::Read32(KMCSPI3_SYSCONFIG);
 	__NK_ASSERT_ALWAYS((r & 1 << 3) == 0);
 	__NK_ASSERT_ALWAYS((r & 1 << 8) == 0);
+	/* nxz enable SPI 3
 	SetClockState( EClkMcSpi3_F, EClkOff );
-	SetClockState( EClkMcSpi3_I, EClkOff );
+	SetClockState( EClkMcSpi3_I, EClkOff );*/
+	SetClockState( EClkMcSpi3_F, EClkOn );
+	SetClockState( EClkMcSpi3_I, EClkOn );
 	r = AsspRegister::Read32(KMCSPI4_SYSCONFIG);
 	__NK_ASSERT_ALWAYS((r & 1 << 3) == 0);
 	__NK_ASSERT_ALWAYS((r & 1 << 8) == 0);
+	/* nxz enable SPI 4
 	SetClockState( EClkMcSpi4_F, EClkOff );
-	SetClockState( EClkMcSpi4_I, EClkOff );
+	SetClockState( EClkMcSpi4_I, EClkOff );*/
+	SetClockState( EClkMcSpi4_F, EClkOn );
+	SetClockState( EClkMcSpi4_I, EClkOn );
 	// UART
 	TInt debugport = Kern::SuperPage().iDebugPort;
 	if( debugport != 0 )
 		{
 	r = AsspRegister::Read32(KGPIO1_SYSCONFIG);
 	__NK_ASSERT_ALWAYS((r & 1 << 3) == 0);
 	__NK_ASSERT_ALWAYS((r & 1 << 8) == 0);
 	_BitClearSet(KCM_FCLKEN_WKUP, 1 << 3, 0);
 	_BitClearSet(KCM_ICLKEN_WKUP, 1 << 3, 0);
 	//r = AsspRegister::Read32(KGPIO2_SYSCONFIG);
 	//__NK_ASSERT_ALWAYS((r & 1 << 3) == 0);
 	//__NK_ASSERT_ALWAYS((r & 1 << 8) == 0);
 	//_BitClearSet(KCM_FCLKEN_PER, 1 << 13, 0);
 	//_BitClearSet(KCM_ICLKEN_PER, 1 << 13, 0);

changeset 23	117faf51deac
parent 0	6663340f3fc9
child 52	d2416cb47e12