1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // \omap3530\omap3530_assp\prcm.cpp

    15 // Access to PRCM. And implimentation of device driver's power and clock control API

    16 // This file is part of the Beagle Base port

    17 //

    18 

    19 #include <e32cmn.h>

    20 #include <assp/omap3530_assp/omap3530_prcm.h>

    21 #include <assp/omap3530_assp/omap3530_ktrace.h>

    22 #include <assp/omap3530_assp/omap3530_irqmap.h>

    23 #include <assp/omap3530_assp/omap3530_hardware_base.h>

    24 #include <assp/omap3530_assp/omap3530_assp_priv.h>

    25 #include <nkern.h>

    26 

    27 #include "prcm_regs.h"

    28 

    29 // Dummy location for redirecting writes which have no effect on a particular clock

    30 // More efficient than having to test for it in code

    31 TUint32 __dummypoke;

    32 #define	KDummy	(TUint32)&__dummypoke

    33 

    34 namespace

    35 {

    36 

    37 // PLL modes

    38 const TUint32 KPllModeStop	= 0x1;

    39 const TUint32 KPllModeBypass = 0x5;

    40 const TUint32 KPllModeFastRelock = 0x6;

    41 const TUint32 KPllModeLock = 0x7;

    42 const TUint32 KPllModeMask = 0x7;

    43 const TUint32 KPllAutoOff = 0x0;

    44 const TUint32 KPllAutoOn = 0x1;

    45 const TUint32 KPllAutoMask = 0x7;

    46 

    47 #ifdef _DEBUG	// to stop warings about unused definitions

    48 const TUint	KPllMaximumDivider		= 127;

    49 const TUint	KPllMaximumMultiplier	= 2047;

    50 #endif

    51 const TUint	KPllDividerMask		= 127;

    52 const TUint	KPllMultiplierMask	= 2047;

    53 const TUint	KPllFreqRangeMask	= 15;

    54 const TUint	KPllRampMask		= 3;

    55 

    56 const TUint KPllLpModeMaximumFrequency = 600000000;

    57 

    58 // TPll to TClock lookup table

    59 static const Prcm::TClock KPllToClock [] =

    60 	{

    61 	Prcm::EClkMpu,

    62 	Prcm::EClkIva2Pll,

    63 	Prcm::EClkCore,

    64 	Prcm::EClkPeriph,

    65 	Prcm::EClkPeriph2

    66 	};

    67 

    68 // struct of info on how to configure each PLL

    69 // this doesn't include settings which are the same for all PLLs

    70 struct TPllControlInfo

    71 	{

    72 	TUint32	iConfigRegister;		// register containing configuration settings

    73 	TUint32	iMulDivRegister;		// register containing multiplier and divider setting

    74 	TUint32	iStatusRegister;		// register containing PLL status

    75 	TUint	iMultShift;				// shift to move multiplier into position

    76 	TUint	iDivShift;				// shift to move divider into position

    77 	TUint	iFreqSelShift;			// shift to move frequency range selection into position

    78 	TUint	iRampShift;				// shift to move ramp bits into position

    79 	TUint	iDriftShift;			// shift to move driftsel into position

    80 	TUint	iLpShift;				// shift to move LP bit into position

    81 	TUint	iLockBit;				// bit number of lock flag in iStatusRegister

    82 	};

    83 

    84 static const TPllControlInfo KPllControlInfo[ Prcm::KSupportedPllCount ] =

    85 	{

    86 	//	ConfReg				MulDivReg			StatusReg				MulShift	DivShift	FreqShift	RampShift	DriftShift	LpShift	LockBit

    87 		{ KCM_CLKEN_PLL_MPU,  KCM_CLKSEL1_PLL_MPU,	KCM_IDLEST_PLL_MPU,		8,		0,			4,			8,			3,			10,		0 },		// DPLL1 (mpu)

    88 		{ KCM_CLKEN_PLL_IVA2, KCM_CLKSEL1_PLL_IVA2,	KCM_IDLEST_PLL_IVA2,	8,		0,			4,			8,			3,			10,		0 },		// DPLL2 (iva2)

    89 		{ KCM_CLKEN_PLL,	KCM_CLKSEL1_PLL,		KCM_IDLEST_CKGEN,		16,		8,			4,			8,			3,			10,		0 },		// DPLL3 (core)

    90 		{ KCM_CLKEN_PLL,	KCM_CLKSEL2_PLL,		KCM_IDLEST_CKGEN,		8,		0,			20,			24,			19,			26,		1 },		// DPLL4 (periph)

    91 		{ KCM_CLKEN2_PLL,	KCM_CLKSEL4_PLL,		KCM_IDLEST2_CKGEN,		8,		0,			4,			8,			3,			10,		0 }		// DPLL5 (periph2)

    92 	};

    93 __ASSERT_COMPILE( (sizeof(KPllControlInfo) / sizeof( KPllControlInfo[0] )) == Prcm::KSupportedPllCount );

    94 

    95 struct TPllModeInfo

    96 	{

    97 	TUint32		iModeRegister;

    98 	TUint32		iAutoRegister;

    99 	TUint8		iModeShift;

   100 	TUint8		iAutoShift;

   101 	TUint8		_spare[2];

   102 	};

   103 

   104 static const TPllModeInfo KPllMode[] =

   105 	{

   106 		// iModeRegister		iAutoRegister			iModeShift	iAutoShift

   107 		{ KCM_CLKEN_PLL_MPU,	KCM_AUTOIDLE_PLL_MPU,	0,			0 },

   108 		{ KCM_CLKEN_PLL_IVA2,	KCM_AUTOIDLE_PLL_IVA2,	0,			0 },

   109 		{ KCM_CLKEN_PLL,		KCM_AUTOIDLE_PLL,		0,			0 },

   110 		{ KCM_CLKEN_PLL,		KCM_AUTOIDLE_PLL,		16,			3 },

   111 		{ KCM_CLKEN2_PLL,		KCM_AUTOIDLE2_PLL,		0,			3 }

   112 	};

   113 __ASSERT_COMPILE( (sizeof(KPllMode) / sizeof( KPllMode[0] )) == Prcm::KSupportedPllCount );

   114 

   115 

   116 // All dividers in the PRCM fall into one of these classes

   117 // Some are unique to a particular peripheral but some

   118 // are used by multiple peripherals so we can share that implementation

   119 enum TDivType

   120 	{

   121 	EDivNotSupported,

   122 	EDiv_1_2,

   123 	EDivCore_1_2_4,

   124 	EDivCore_3_4_6_96M,

   125 	EDivPll_1_To_16,

   126 	EDivPll_1_To_31,

   127 	EDivUsimClk,

   128 	EDivClkOut_1_2_4_8_16,

   129 	};

   130 

   131 struct TDividerInfo

   132 	{

   133 	TUint32		iRegister;

   134 	TUint32		iMask;			// mask of bits to modify in register

   135 	TDivType	iDivType : 8;

   136 	TUint8		iShift;			// number of bits to shift to move divide value into position

   137 	};

   138 

   139 static const TDividerInfo KDividerInfo[] =

   140 	{

   141 		{ KCM_CLKSEL2_PLL_MPU,		0x1F,							EDivPll_1_To_16,	0 },	// EClkMpu,		///< DPLL1

   142 		{ KCM_CLKSEL2_PLL_IVA2,		0x1F,							EDivPll_1_To_16,	0 },

   143 		{ KCM_CLKSEL1_PLL,			0x1FU << 27,					EDivPll_1_To_31,	27 },	// EClkCore,		///< DPLL3

   144 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkPeriph,		///< DPLL4

   145 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkPeriph2,	///< DPLL5

   146 

   147 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkPrcmInterface,

   148 

   149 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkEmu,		///< Emulation clock

   150 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkNeon,

   151 

   152 		{ KCM_CLKSEL_CORE,			KBit0 | KBit1,					EDiv_1_2,			0 },	// EClkL3Domain,

   153 		{ KCM_CLKSEL_CORE,			KBit2 | KBit3,					EDiv_1_2,			2 },	// EClkL4Domain,

   154 

   155 		{ KCM_CLKSEL1_PLL_MPU,		KBit19 | KBit20 | KBit21,		EDivCore_1_2_4,		19 },	// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency

   156 		{ KCM_CLKSEL1_PLL_IVA2,		KBit19 | KBit20 | KBit21,		EDivCore_1_2_4,		19 },	// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency

   157 		{ KCM_CLKSEL_WKUP,			KBit1 | KBit2,					EDiv_1_2,			1 },	// EClkRM_F,	///< Reset manager functional clock	

   158 		{ KCM_CLKSEL3_PLL,			0x1F,							EDivPll_1_To_16,	0 },	// EClk96M		///< 96MHz clock

   159 		{ KCM_CLKSEL5_PLL,			0x1F,							EDivPll_1_To_16,	0 },	// EClk120M		///< 120MHz clock

   160 		{ KCM_CLKOUT_CTRL,			KBit3 | KBit4 | KBit5,			EDivClkOut_1_2_4_8_16,	3 },	// EClkSysOut

   161 

   162 		// Functional clocks

   163 		{ KCM_CLKSEL_DSS,			0x1FU << 8,						EDivPll_1_To_16,	8 },	// EClkTv_F,

   164 		{ KCM_CLKSEL_DSS,			0x1F,							EDivPll_1_To_16,	0 },	// EClkDss1_F,

   165 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkDss2_F,

   166 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkCsi2_F,

   167 		{ KCM_CLKSEL_CAM,			0x1F,							EDivPll_1_To_16,	0 },	// EClkCam_F,

   168 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkIva2_F,

   169 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc1_F,

   170 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc2_F,

   171 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc3_F,

   172 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMsPro_F,

   173 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkHdq_F,

   174 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp1_F,

   175 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp2_F,

   176 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp3_F,

   177 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp4_F,

   178 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp5_F,

   179 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi1_F,

   180 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi2_F,

   181 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi3_F,

   182 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi4_F,

   183 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c1_F,

   184 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c2_F,

   185 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c3_F,

   186 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart1_F,

   187 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart2_F,

   188 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart3_F,

   189 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt1_F,

   190 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt2_F,

   191 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt3_F,

   192 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt4_F,

   193 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt5_F,

   194 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt6_F,

   195 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt7_F,

   196 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt8_F,

   197 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt9_F,

   198 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt10_F,

   199 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt11_F,

   200 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsbTll_F,

   201 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkTs_F,

   202 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkCpeFuse_F,

   203 

   204 		{ KCM_CLKSEL_SGX,	KBit0 | KBit1 | KBit2,					EDivCore_3_4_6_96M, 0 },	// EClkSgx_F,

   205 

   206 		{ KCM_CLKSEL_WKUP,	KBit3 | KBit4 | KBit5 | KBit6,			EDivUsimClk,		3 },	// EClkUsim_F,

   207 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSmartReflex2_F,

   208 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSmartReflex1_F,

   209 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt2_F,

   210 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt3_F,

   211 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio1_F,

   212 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio2_F,

   213 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio3_F,

   214 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio4_F,

   215 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio5_F,

   216 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio6_F,

   217 

   218 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsb120_F,		///< USB host 120MHz functional clock

   219 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsb48_F,		///< USB host 48MHz functional clock

   220 

   221 

   222 	// Interface clocks

   223 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkDss_I,

   224 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkCam_I,

   225 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkIcr_I,

   226 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc1_I,

   227 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc2_I,

   228 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc3_I,

   229 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMsPro_I,

   230 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkHdq_I,

   231 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkAes1_I,

   232 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkAes2_I,

   233 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSha11_I,

   234 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSha12_I,

   235 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkDes1_I,

   236 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkDes2_I,

   237 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp1_I,

   238 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp2_I,

   239 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp3_I,

   240 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp4_I,

   241 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp5_I,

   242 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c1_I,

   243 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c2_I,

   244 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c3_I,

   245 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart1_I,

   246 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart2_I,

   247 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart3_I,

   248 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi1_I,

   249 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi2_I,

   250 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi3_I,

   251 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi4_I,

   252 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt1_I,

   253 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt2_I,

   254 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt3_I,

   255 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt4_I,

   256 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt5_I,

   257 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt6_I,

   258 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt7_I,

   259 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt8_I,

   260 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt9_I,

   261 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt10_I,

   262 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt11_I,

   263 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt12_I,

   264 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMailboxes_I,

   265 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkOmapSCM_I,

   266 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkHsUsbOtg_I,

   267 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSdrc_I,

   268 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkPka_I,

   269 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkRng_I,

   270 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsbTll_I,

   271 

   272 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSgx_I,

   273 

   274 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsim_I,

   275 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt1_I,

   276 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt2_I,

   277 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt3_I,

   278 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio1_I,

   279 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio2_I,

   280 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio3_I,

   281 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio4_I,

   282 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio5_I,

   283 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio6_I,

   284 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClk32Sync_I,

   285 

   286 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsb_I,			///< USB host interface clock

   287 

   288 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClk48M

   289 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClk12M

   290 

   291 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSysClk,

   292 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkAltClk,

   293 		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSysClk32k,

   294 	};

   295 __ASSERT_COMPILE( (sizeof(KDividerInfo) / sizeof( KDividerInfo[0] )) == Prcm::KSupportedClockCount );

   296 

   297 // Special case divider and mux info for USIM

   298 struct TUsimDivMuxInfo

   299 	{

   300 	Prcm::TClock	iClock : 8;		// source clock

   301 	TUint8			iDivider;		// divider factor

   302 	};

   303 static const TUsimDivMuxInfo UsimDivMuxInfo[16] =

   304 	{

   305 		{ Prcm::EClkSysClk,		1 },	// 0x0

   306 		{ Prcm::EClkSysClk,		1 },	// 0x1

   307 		{ Prcm::EClkSysClk,		2 },	// 0x2

   308 		{ Prcm::EClk96M,		2 },	// 0x3

   309 		{ Prcm::EClk96M,		4 },	// 0x4

   310 		{ Prcm::EClk96M,		8 },	// 0x5

   311 		{ Prcm::EClk96M,		10 },	// 0x6

   312 		{ Prcm::EClk120M,		4 },	// 0x7

   313 		{ Prcm::EClk120M,		8 },	// 0x8

   314 		{ Prcm::EClk120M,		16 },	// 0x9

   315 		{ Prcm::EClk120M,		20 },	// 0xA

   316 		{ Prcm::EClkSysClk,		1 },	// 0xB

   317 		{ Prcm::EClkSysClk,		1 },	// 0xC

   318 		{ Prcm::EClkSysClk,		1 },	// 0xD

   319 		{ Prcm::EClkSysClk,		1 },	// 0xE

   320 		{ Prcm::EClkSysClk,		1 }		// 0xF

   321 	};

   322 

   323 // Structure representing a register, mask and enable/disable values

   324 struct TRegisterBitDef

   325 	{

   326 	TUint32	iRegister;

   327 	TUint32	iMask;

   328 	TUint32	iEnablePattern;

   329 	TUint32	iDisablePattern;

   330 	};

   331 

   332 // Structure for holding information on clock enable and auto mode

   333 struct TClockEnableAutoInfo

   334 	{

   335 	TRegisterBitDef	iGate;

   336 	TRegisterBitDef	iAuto;

   337 	};

   338 

   339 const TUint32 KDummyReadAsDisabled = 1;

   340 const TUint32 KDummyReadAsEnabled = 0;

   341 const TUint32 KBit012	= KBit0 | KBit1 | KBit2;

   342 const TUint32 KBit345	= KBit3 | KBit4 | KBit5;

   343 const TUint32 KBit16_17_18 = KBit16 | KBit17 | KBit18;

   344 

   345 // Table of bits to set to enable each clock

   346 // Note where a function doesn't exist, use { KDummy, 0, V, 0 } which will cause a write to harmlessly write

   347 // to __dummypoke and a read to find that the item is disabled if V==KDummyReadAsDisabled and enabled if V=KDummyReadAsEnabled

   348 static const TClockEnableAutoInfo KClockControlTable[] =

   349 	{

   350 		{ { KDummy, 0, 0, 0 },						{ KCM_AUTOIDLE_PLL_MPU, KBit012, 1, 0 } },					// EClkMpu,

   351 		{ { KCM_CLKEN_PLL_IVA2, KBit012, 7, 1 },	{ KCM_AUTOIDLE_PLL_IVA2, KBit0, 1, 0 } },					// EClkIva2Pll,

   352 		{ { KCM_CLKEN_PLL, KBit012, 0x7, 0x5 },						{ KCM_AUTOIDLE_PLL, KBit012, 1, 0 } },		// EClkCore,		///< DPLL3

   353 		{ { KCM_CLKEN_PLL, KBit16_17_18, KBit16_17_18, KBit16 },	{ KCM_AUTOIDLE_PLL, KBit345, KBit3, 0 } },	// EClkPeriph,		///< DPLL4

   354 		{ { KCM_CLKEN2_PLL, KBit012, 0x7, 0x1 },					{ KCM_AUTOIDLE2_PLL, KBit012, 1, 0 } },		// EClkPeriph2,	///< DPLL5

   355 

   356 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkPrcmInterface,

   357 		{ { KDummy, 0, 0, 0 },							{ KCM_CLKSTCTRL_EMU, KBit0 | KBit1, 3, 2 } },		// EClkEmu,		///< Emulation clock

   358 		{ { KCM_IDLEST_NEON, KBit0, 0, 1 },				{ KCM_CLKSTCTRL_NEON, KBit0 | KBit1, 3, 2 } },		// EClkNeon,

   359 

   360 		{ { KDummy, 0, 0, 0 },							{ KCM_CLKSTCTRL_CORE, KBit0 | KBit1, KBit0 | KBit1, 0 } },		// EClkL3Domain,

   361 		{ { KDummy, 0, 0, 0 },							{ KCM_CLKSTCTRL_CORE, KBit2 | KBit3, KBit2 | KBit3, 0 } },	// EClkL4Domain,

   362 

   363 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency

   364 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency

   365 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkRM_F,			///< Reset manager functional clock	

   366 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk96M,			///< 96MHz clock

   367 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk120M,			///< 120MHz clock

   368 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkSysOut,

   369 

   370 	// Functional clocks

   371 		{ { KCM_FCLKEN_DSS, KBit2, KBit2, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkTv_F,

   372 		{ { KCM_FCLKEN_DSS, KBit0, KBit0, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkDss1_F,

   373 		{ { KCM_FCLKEN_DSS, KBit1, KBit1, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkDss2_F,

   374 		{ { KCM_FCLKEN_CAM, KBit1, KBit1, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkCsi2_F,

   375 		{ { KCM_FCLKEN_CAM, KBit0, KBit0, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkCam_F,

   376 		{ { KCM_FCLKEN_IVA2, KBit0, KBit0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkIva2_F,

   377 		{ { KCM_FCLKEN1_CORE, KBit24, KBit24, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMmc1_F,

   378 		{ { KCM_FCLKEN1_CORE, KBit25, KBit25, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMmc2_F,

   379 		{ { KCM_FCLKEN1_CORE, KBit30, KBit30, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMmc3_F,

   380 		{ { KCM_FCLKEN1_CORE, KBit23, KBit23, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMsPro_F,

   381 		{ { KCM_FCLKEN1_CORE, KBit22, KBit22, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkHdq_F,

   382 		{ { KCM_FCLKEN1_CORE, KBit9, KBit9, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP1_F,

   383 		{ { KCM_FCLKEN_PER, KBit0, KBit0, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP2_F,

   384 		{ { KCM_FCLKEN_PER, KBit1, KBit1, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP3_F,

   385 		{ { KCM_FCLKEN_PER, KBit2, KBit2, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP4_F,

   386 		{ { KCM_FCLKEN1_CORE, KBit10, KBit10, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP5_F,

   387 		{ { KCM_FCLKEN1_CORE, KBit18, KBit18, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi1_F,

   388 		{ { KCM_FCLKEN1_CORE, KBit19, KBit19, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi2_F,

   389 		{ { KCM_FCLKEN1_CORE, KBit20, KBit20, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi3_F,

   390 		{ { KCM_FCLKEN1_CORE, KBit21, KBit21, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi4_F,

   391 		{ { KCM_FCLKEN1_CORE, KBit15, KBit15, 0},	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkI2c1_F,

   392 		{ { KCM_FCLKEN1_CORE, KBit16, KBit16, 0},	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkI2c2_F,

   393 		{ { KCM_FCLKEN1_CORE, KBit17, KBit17, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkI2c3_F,

   394 		{ { KCM_FCLKEN1_CORE, KBit13, KBit13, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUart1_F,

   395 		{ { KCM_FCLKEN1_CORE, KBit14, KBit14, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUart2_F,

   396 		{ { KCM_FCLKEN_PER, KBit11, KBit11, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUart3_F,

   397 		{ { KCM_FCLKEN_WKUP, KBit0, KBit0, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt1_F,

   398 		{ { KCM_FCLKEN_PER, KBit3, KBit3, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt2_F,

   399 		{ { KCM_FCLKEN_PER, KBit4, KBit4, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt3_F,

   400 		{ { KCM_FCLKEN_PER, KBit5, KBit5, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt4_F,

   401 		{ { KCM_FCLKEN_PER, KBit6, KBit6, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt5_F,

   402 		{ { KCM_FCLKEN_PER, KBit7, KBit7, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt6_F,

   403 		{ { KCM_FCLKEN_PER, KBit8, KBit8, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt7_F,

   404 		{ { KCM_FCLKEN_PER, KBit9, KBit9, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt8_F,

   405 		{ { KCM_FCLKEN_PER, KBit10, KBit10, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt9_F,

   406 		{ { KCM_FCLKEN1_CORE, KBit11, KBit11, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt10_F,

   407 		{ { KCM_FCLKEN1_CORE, KBit12, KBit12, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt11_F,

   408 		{ { KCM_FCLKEN3_CORE, KBit2, KBit2, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUsbTll_F,

   409 		{ { KCM_FCLKEN3_CORE, KBit1, KBit1, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkTs_F,

   410 		{ { KCM_FCLKEN3_CORE, KBit0, KBit0, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkCpeFuse_F,

   411 

   412 		{ { KCM_FCLKEN_SGX, KBit1, KBit1, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkSgx_F,

   413 

   414 		{ { KCM_FCLKEN_WKUP, KBit9, KBit9, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUsim_F,

   415 		{ { KCM_FCLKEN_WKUP, KBit7, KBit7, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkSmartReflex2_F,

   416 		{ { KCM_FCLKEN_WKUP, KBit6, KBit6, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkSmartReflex1_F,

   417 		{ { KCM_FCLKEN_WKUP, KBit5, KBit5, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkWdt2_F,

   418 		{ { KCM_FCLKEN_PER, KBit12, KBit12, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkWdt3_F,

   419 		{ { KCM_FCLKEN_WKUP, KBit3, KBit3, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio1_F,

   420 		{ { KCM_FCLKEN_PER, KBit13, KBit13, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio2_F,

   421 		{ { KCM_FCLKEN_PER, KBit14, KBit14, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio3_F,

   422 		{ { KCM_FCLKEN_PER, KBit15, KBit15, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio4_F,

   423 		{ { KCM_FCLKEN_PER, KBit16, KBit16, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio5_F,

   424 		{ { KCM_FCLKEN_PER, KBit17, KBit17, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio6_F,

   425 

   426 		{ { KCM_FCLKEN_USBHOST, KBit1, KBit1, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUsb120_F,

   427 		{ { KCM_FCLKEN_USBHOST, KBit0, KBit0, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUsb48_F,

   428 

   429 

   430 	// Interface clocks

   431 		{ { KCM_ICLKEN_DSS, KBit0, KBit0, 0 },		{ KCM_AUTOIDLE_DSS, KBit0, KBit0, 0 } },		// EClkDss_I,

   432 		{ { KCM_ICLKEN_CAM, KBit0,KBit0, 0 },		{ KCM_AUTOIDLE_CAM, KBit0, KBit0, 0 } },		// EClkCam_I,

   433 		{ { KCM_ICLKEN1_CORE, KBit29, KBit29, 0 },	{ KCM_AUTOIDLE1_CORE, KBit29, KBit29, 0 } },	// EClkIcr_I,

   434 		{ { KCM_ICLKEN1_CORE, KBit24, KBit24, 0 },	{ KCM_AUTOIDLE1_CORE, KBit24, KBit24, 0 } },	// EClkMmc1_I,

   435 		{ { KCM_ICLKEN1_CORE, KBit25, KBit25, 0 },	{ KCM_AUTOIDLE1_CORE, KBit25, KBit25, 0 } },	// EClkMmc2_I,

   436 		{ { KCM_ICLKEN1_CORE, KBit30, KBit30, 0 },	{ KCM_AUTOIDLE1_CORE, KBit30, KBit30, 0 } },	// EClkMmc3_I,

   437 		{ { KCM_ICLKEN1_CORE, KBit23, KBit23, 0 },	{ KCM_AUTOIDLE1_CORE, KBit23, KBit23, 0 } },	// EClkMsPro_I,

   438 		{ { KCM_ICLKEN1_CORE, KBit22, KBit22, 0 },	{ KCM_AUTOIDLE1_CORE, KBit22, KBit22, 0 } },	// EClkHdq_I,

   439 		{ { KCM_ICLKEN2_CORE, KBit3, KBit3, 0 },	{ KCM_AUTOIDLE2_CORE, KBit3, KBit3, 0 } },		// EClkAes1_I,

   440 		{ { KCM_ICLKEN1_CORE, KBit28, KBit28, 0 },	{ KCM_AUTOIDLE1_CORE, KBit28, KBit28, 0 } },	// EClkAes2_I,

   441 		{ { KCM_ICLKEN2_CORE, KBit1, KBit1, 0 },	{ KCM_AUTOIDLE2_CORE, KBit1, KBit1, 0 } },		// EClkSha11_I,

   442 		{ { KCM_ICLKEN1_CORE, KBit28, KBit27, 0 },	{ KCM_AUTOIDLE1_CORE, KBit27, KBit27, 0 } },	// EClkSha12_I,

   443 		{ { KCM_ICLKEN2_CORE, KBit0, KBit0, 0 },	{ KCM_AUTOIDLE2_CORE, KBit0, KBit0, 0 } },		// EClkDes1_I,

   444 		{ { KCM_ICLKEN1_CORE, KBit26, KBit26, 0 },	{ KCM_AUTOIDLE1_CORE, KBit26, KBit26, 0 } },	// EClkDes2_I,

   445 		{ { KCM_ICLKEN1_CORE, KBit9, KBit9, 0 },	{ KCM_AUTOIDLE1_CORE, KBit9, KBit9, 0 } },		// EClkMcBSP1_I,

   446 		{ { KCM_ICLKEN_PER, KBit0, KBit0, 0},		{ KCM_AUTOIDLE_PER, KBit0, KBit0, 0 } },		// EClkMcBSP2_I,

   447 		{ { KCM_ICLKEN_PER, KBit1, KBit1, 0 },		{ KCM_AUTOIDLE_PER, KBit1, KBit1, 0 } },		// EClkMcBSP3_I,

   448 		{ { KCM_ICLKEN_PER, KBit2, KBit2, 0 },		{ KCM_AUTOIDLE_PER, KBit2, KBit2, 0 } },		// EClkMcBSP4_I,

   449 		{ { KCM_ICLKEN1_CORE, KBit10, KBit10, 0 },	{ KCM_AUTOIDLE1_CORE, KBit10, KBit10, 0 } },	// EClkMcBSP5_I,

   450 		{ { KCM_ICLKEN1_CORE, KBit15, KBit15, 0 },	{ KCM_AUTOIDLE1_CORE, KBit15, KBit15, 0 } },	// EClkI2c1_I,

   451 		{ { KCM_ICLKEN1_CORE, KBit16, KBit16, 0 },	{ KCM_AUTOIDLE1_CORE, KBit16, KBit16, 0 } },	// EClkI2c2_I,

   452 		{ { KCM_ICLKEN1_CORE, KBit17, KBit17, 0 },	{ KCM_AUTOIDLE1_CORE, KBit17, KBit17, 0 } },	// EClkI2c3_I,

   453 		{ { KCM_ICLKEN1_CORE, KBit13, KBit13, 0 },	{ KCM_AUTOIDLE1_CORE, KBit13, KBit13, 0 } },	// EClkUart1_I,

   454 		{ { KCM_ICLKEN1_CORE, KBit14, KBit14, 0 },	{ KCM_AUTOIDLE1_CORE, KBit14, KBit14, 0 } },	// EClkUart2_I,

   455 		{ { KCM_ICLKEN_PER, KBit11, KBit11, 0 },	{ KCM_AUTOIDLE_PER, KBit11, KBit11, 0 } },		// EClkUart3_I,

   456 		{ { KCM_ICLKEN1_CORE, KBit18, KBit18, 0 },	{ KCM_AUTOIDLE1_CORE, KBit18, KBit18, 0 } },	// EClkMcSpi1_I,

   457 		{ { KCM_ICLKEN1_CORE, KBit19, KBit19, 0 },	{ KCM_AUTOIDLE1_CORE, KBit19, KBit19, 0 } },	// EClkMcSpi2_I,

   458 		{ { KCM_ICLKEN1_CORE, KBit20, KBit20, 0 },	{ KCM_AUTOIDLE1_CORE, KBit20, KBit20, 0 } },	// EClkMcSpi3_I,

   459 		{ { KCM_ICLKEN1_CORE, KBit21, KBit21, 0 },	{ KCM_AUTOIDLE1_CORE, KBit21, KBit21, 0 } },	// EClkMcSpi4_I,

   460 		{ { KCM_ICLKEN_WKUP, KBit0, KBit0, 0 },		{ KCM_AUTOIDLE_WKUP, KBit0, KBit0, 0 } },		// EClkGpt1_I,

   461 		{ { KCM_ICLKEN_PER, KBit3, KBit3, 0 },		{ KCM_AUTOIDLE_PER, KBit3, KBit3, 0 } },		// EClkGpt2_I,

   462 		{ { KCM_ICLKEN_PER, KBit4, KBit4, 0 },		{ KCM_AUTOIDLE_PER, KBit4, KBit4, 0 } },		// EClkGpt3_I,

   463 		{ { KCM_ICLKEN_PER, KBit5, KBit5, 0 },		{ KCM_AUTOIDLE_PER, KBit5, KBit5, 0 } },		// EClkGpt4_I,

   464 		{ { KCM_ICLKEN_PER, KBit6, KBit6, 0 },		{ KCM_AUTOIDLE_PER, KBit6, KBit6, 0 } },		// EClkGpt5_I,

   465 		{ { KCM_ICLKEN_PER, KBit7, KBit7, 0 },		{ KCM_AUTOIDLE_PER, KBit7, KBit7, 0 } },		// EClkGpt6_I,

   466 		{ { KCM_ICLKEN_PER, KBit8, KBit8, 0 },		{ KCM_AUTOIDLE_PER, KBit8, KBit8, 0 } },		// EClkGpt7_I,

   467 		{ { KCM_ICLKEN_PER, KBit9, KBit9, 0 },		{ KCM_AUTOIDLE_PER, KBit9, KBit9, 0 } },		// EClkGpt8_I,

   468 		{ { KCM_ICLKEN_PER, KBit10, KBit10, 0 },	{ KCM_AUTOIDLE_PER, KBit10, KBit10, 0 } },		// EClkGpt9_I,

   469 		{ { KCM_ICLKEN1_CORE, KBit11, KBit11, 0 },	{ KCM_AUTOIDLE1_CORE, KBit11, KBit11, 0 } },	// EClkGpt10_I,

   470 		{ { KCM_ICLKEN1_CORE, KBit12, KBit12, 0 },	{ KCM_AUTOIDLE1_CORE, KBit12, KBit12, 0 } },	// EClkGpt11_I,

   471 		{ { KDummy, 0, 0, 0 },						{ KDummy, 0, KDummyReadAsDisabled, 0 } },							// EClkGpt12_I,

   472 		{ { KCM_ICLKEN1_CORE, KBit7, KBit7, 0 },	{ KCM_AUTOIDLE1_CORE, KBit7, KBit7, 0 } },		// EClkMailboxes_I,

   473 		{ { KCM_ICLKEN1_CORE, KBit6, KBit6, 0 },	{ KCM_AUTOIDLE1_CORE, KBit6, KBit6, 0 } },		// EClkOmapSCM_I,

   474 		{ { KCM_ICLKEN1_CORE, KBit4, KBit4, 0 },	{ KCM_AUTOIDLE1_CORE, KBit4, KBit4, 0 } },		// EClkHsUsbOtg_I,

   475 		{ { KCM_ICLKEN1_CORE, KBit1, KBit1, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSdrc_I,

   476 		{ { KCM_ICLKEN2_CORE, KBit4, KBit4, 0 },	{ KCM_AUTOIDLE2_CORE, KBit4, KBit4, 0 } },		// EClkPka_I,

   477 		{ { KCM_ICLKEN2_CORE, KBit2, KBit2, 0 },	{ KCM_AUTOIDLE2_CORE, KBit2, KBit2, 0 } },		// EClkRng_I,

   478 		{ { KCM_ICLKEN3_CORE, KBit2, KBit2, 0 },	{ KCM_AUTOIDLE3_CORE, KBit2, KBit2, 0 } },		// EClkUsbTll_I,

   479 

   480 		{ { KCM_ICLKEN_SGX, KBit0, KBit0, 0 },		{ KCM_CLKSTCTRL_SGX, KBit0 | KBit1, 0x3, 0x0 } },	// EClkSgx_I,

   481 

   482 		{ { KCM_ICLKEN_WKUP, KBit9, KBit9, 0 },		{ KCM_AUTOIDLE_WKUP, KBit9, KBit9, 0 } },		// EClkUsim_I,

   483 		{ { KCM_ICLKEN_WKUP, KBit4, KBit4, 0 },		{ KCM_AUTOIDLE_WKUP, KBit4, KBit4, 0 } },		// EClkWdt1_I,

   484 		{ { KCM_ICLKEN_WKUP, KBit5, KBit5, 0 },		{ KCM_AUTOIDLE_WKUP, KBit5, KBit5, 0 } },		// EClkWdt2_I,

   485 		{ { KCM_ICLKEN_PER, KBit12, KBit12, 0 },	{ KCM_AUTOIDLE_PER, KBit12, KBit12, 0 } },		// EClkWdt3_I,

   486 		{ { KCM_ICLKEN_WKUP, KBit3, KBit3, 0 },		{ KCM_AUTOIDLE_WKUP, KBit3, KBit3, 0 } },		// EClkGpio1_I,

   487 		{ { KCM_ICLKEN_PER, KBit13, KBit13, 0 },	{ KCM_AUTOIDLE_PER, KBit13, KBit13, 0 } },		// EClkGpio2_I,

   488 		{ { KCM_ICLKEN_PER, KBit14, KBit14, 0 },	{ KCM_AUTOIDLE_PER, KBit14, KBit14, 0 } },		// EClkGpio3_I,

   489 		{ { KCM_ICLKEN_PER, KBit15, KBit15, 0 },	{ KCM_AUTOIDLE_PER, KBit15, KBit15, 0 } },		// EClkGpio4_I,

   490 		{ { KCM_ICLKEN_PER, KBit16, KBit16, 0 },	{ KCM_AUTOIDLE_PER, KBit16, KBit16, 0 } },		// EClkGpio5_I,

   491 		{ { KCM_ICLKEN_PER, KBit17, KBit17, 0 },	{ KCM_AUTOIDLE_PER, KBit17, KBit17, 0 } },		// EClkGpio6_I,

   492 		{ { KCM_ICLKEN_WKUP, KBit2, KBit2, 0 },		{ KCM_AUTOIDLE_WKUP, KBit2, KBit2, 0 } },		// EClk32Sync_I,

   493 

   494 		{ { KCM_ICLKEN_USBHOST, KBit0, KBit0, 0 }, { KCM_AUTOIDLE_USBHOST, KBit0, KBit0, 0 } },		// EClkUsb_I,			///< USB host interface clock

   495 

   496 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk48M

   497 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk12M

   498 

   499 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkSysClk

   500 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkAltClk

   501 		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkSysClk32k

   502 	};

   503 __ASSERT_COMPILE( (sizeof(KClockControlTable) / sizeof( KClockControlTable[0] )) == Prcm::KSupportedClockCount );

   504 

   505 static const TRegisterBitDef KClockWakeupTable[] =

   506 	{

   507 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMpu,		///< DPLL1

   508 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkIva2Pll,	///< DPLL2

   509 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkCore,		///< DPLL3

   510 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkPeriph,		///< DPLL4

   511 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkPeriph2,	///< DPLL5

   512 

   513 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkPrcmInterface,

   514 

   515 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkEmu,		///< Emulation clock

   516 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkNeon,

   517 

   518 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkL3Domain,

   519 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkL4Domain,

   520 

   521 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency

   522 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency

   523 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkRM_F,			///< Reset manager functional clock	

   524 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClk96M,			///< 96MHz clock

   525 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClk120M,			///< 120MHz clock

   526 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSysOut,

   527 

   528 	// Functional clocks

   529 	// NOTE - functional clocks aren't mapped to a wakeup event, these just clock the internals

   530 	// Use the interface clocks to register a wakeup

   531 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkTv_F,

   532 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkDss1_F,

   533 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkDss2_F,

   534 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkCsi2_F,

   535 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkCam_F,

   536 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkIva2_F,

   537 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMmc1_F,

   538 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMmc2_F,

   539 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMmc3_F,

   540 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMsPro_F,

   541 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkHdq_F,

   542 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMcBSP1_F,

   543 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMcBSP2_F,

   544 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMcBSP3_F,

   545 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMcBSP4_F,

   546 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMcBSP5_F,

   547 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMcSpi1_F

   548 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMcSpi2_F

   549 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMcSpi3_F

   550 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMcSpi4_F

   551 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkI2c1_F,

   552 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkI2c2_F,

   553 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkI2c3_F,

   554 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkUart1_F,

   555 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkUart2_F,

   556 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkUart3_F,

   557 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt1_F,

   558 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt2_F,

   559 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt3_F,

   560 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt4_F,

   561 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt5_F,

   562 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt6_F,

   563 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt7_F,

   564 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt8_F,

   565 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt9_F,

   566 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt10_F,

   567 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpt11_F,

   568 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkUsbTll_F,

   569 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkTs_F,

   570 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkCpeFuse_F,

   571 

   572 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSgx_F,

   573 

   574 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkUsim_F,

   575 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSmartReflex2_F,

   576 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSmartReflex1_F,

   577 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkWdt2_F,

   578 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkWdt3_F,

   579 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpio1_F,

   580 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpio2_F,

   581 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpio3_F,

   582 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpio4_F,

   583 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpio5_F,

   584 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkGpio6_F,

   585 

   586 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkUsb120_F,		///< USB host 120MHz functional clock

   587 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkUsb48_F,		///< USB host 48MHz functional clock

   588 

   589 

   590 	// Interface clocks

   591 		{ KPM_WKEN_DSS, KBit0, KBit0, 0 },	// EClkDss_I,

   592 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkCam_I,

   593 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkIcr_I,

   594 		{ KPM_WKEN1_CORE, KBit24, KBit24, 0 },	// EClkMmc1_I,

   595 		{ KPM_WKEN1_CORE, KBit25, KBit25, 0 },	// EClkMmc2_I,

   596 		{ KPM_WKEN1_CORE, KBit30, KBit30, 0 },	// EClkMmc3_I,

   597 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMsPro_I,

   598 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkHdq_I,

   599 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkAes1_I,

   600 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkAes2_I,

   601 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSha11_I,

   602 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSha12_I,

   603 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkDes1_I,

   604 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkDes2_I,

   605 		{ KPM_WKEN1_CORE, KBit9, KBit9, 0 },	// EClkMcBSP1_I,

   606 		{ KPM_WKEN_PER, KBit0, KBit0, 0 },	// EClkMcBSP2_I,

   607 		{ KPM_WKEN_PER, KBit1, KBit1, 0 },	// EClkMcBSP3_I,

   608 		{ KPM_WKEN_PER, KBit2, KBit2, 0 },	// EClkMcBSP4_I,

   609 		{ KPM_WKEN1_CORE, KBit10, KBit10, 0 },	// EClkMcBSP5_I,

   610 		{ KPM_WKEN1_CORE, KBit15, KBit15, 0 },	// EClkI2c1_I,

   611 		{ KPM_WKEN1_CORE, KBit16, KBit16, 0 },	// EClkI2c2_I,

   612 		{ KPM_WKEN1_CORE, KBit17, KBit17, 0 },	// EClkI2c3_I,

   613 		{ KPM_WKEN1_CORE, KBit13, KBit13, 0 },	// EClkUart1_I,

   614 		{ KPM_WKEN1_CORE, KBit14, KBit14, 0 },	// EClkUart2_I,

   615 		{ KPM_WKEN_PER, KBit11, KBit11, 0 },	// EClkUart3_I,

   616 		{ KPM_WKEN1_CORE, KBit18, KBit18, 0 },	// EClkMcSpi1_I

   617 		{ KPM_WKEN1_CORE, KBit19, KBit19, 0 },	// EClkMcSpi2_I

   618 		{ KPM_WKEN1_CORE, KBit20, KBit20, 0 },	// EClkMcSpi3_I

   619 		{ KPM_WKEN1_CORE, KBit21, KBit21, 0 },	// EClkMcSpi4_I

   620 		{ KPM_WKEN_WKUP, KBit0, KBit0, 0 },	// EClkGpt1_I,

   621 		{ KPM_WKEN_PER, KBit3, KBit3, 0 },	// EClkGpt2_I,

   622 		{ KPM_WKEN_PER, KBit4, KBit4, 0 },	// EClkGpt3_I,

   623 		{ KPM_WKEN_PER, KBit5, KBit5, 0 },	// EClkGpt4_I,

   624 		{ KPM_WKEN_PER, KBit6, KBit6, 0 },	// EClkGpt5_I,

   625 		{ KPM_WKEN_PER, KBit7, KBit7, 0 },	// EClkGpt6_I,

   626 		{ KPM_WKEN_PER, KBit8, KBit8, 0 },	// EClkGpt7_I,

   627 		{ KPM_WKEN_PER, KBit9, KBit9, 0 },	// EClkGpt8_I,

   628 		{ KPM_WKEN_PER, KBit10, KBit10, 0 },	// EClkGpt9_I,

   629 		{ KPM_WKEN1_CORE, KBit11, KBit11, 0 },	// EClkGpt10_I,

   630 		{ KPM_WKEN1_CORE, KBit12, KBit12, 0 },	// EClkGpt11_I,

   631 		{ KPM_WKEN_WKUP, KBit1, KBit1, 0 },	// EClkGpt12_I,

   632 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMailboxes_I,

   633 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkOmapSCM_I,

   634 		{ KPM_WKEN1_CORE, KBit4, KBit4, 0 },	// EClkHsUsbOtg_I,

   635 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSdrc_I,

   636 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkPka_I,

   637 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkRng_I,

   638 		{ KPM_WKEN3_CORE, KBit2, KBit2, 0 },	// EClkUsbTll_I,

   639 

   640 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSgx_I,

   641 

   642 		{ KPM_WKEN_WKUP, KBit9, KBit9, 0 },	// EClkUsim_I,

   643 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkWdt1_I,

   644 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkWdt2_I,

   645 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkWdt3_I,

   646 		{ KPM_WKEN_WKUP, KBit3, KBit3, 0 },	// EClkGpio1_I,

   647 		{ KPM_WKEN_PER, KBit13, KBit13, 0 },	// EClkGpio2_I,

   648 		{ KPM_WKEN_PER, KBit14, KBit14, 0 },	// EClkGpio3_I,

   649 		{ KPM_WKEN_PER, KBit15, KBit15, 0 },	// EClkGpio4_I,

   650 		{ KPM_WKEN_PER, KBit16, KBit16, 0 },	// EClkGpio5_I,

   651 		{ KPM_WKEN_PER, KBit17, KBit17, 0 },	// EClkGpio6_I,

   652 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClk32Sync_I,

   653 

   654 		{ KPM_WKEN_USBHOST, KBit0, KBit0, 0 },	// EClkUsb_I,			///< USB host interface clock

   655 

   656 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClk48M

   657 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClk12M

   658 

   659 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSysClk

   660 		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkAltClk

   661 		{ KDummy, 0, KDummyReadAsDisabled, 0 }	// EClkSysClk32k

   662 

   663 	};

   664 __ASSERT_COMPILE( (sizeof(KClockWakeupTable) / sizeof( KClockWakeupTable[0] )) == Prcm::KSupportedClockCount );

   665 

   666 

   667 __ASSERT_COMPILE( Prcm::EWakeGroupMpu == 0 );

   668 __ASSERT_COMPILE( Prcm::EWakeGroupIva2 == 1 );

   669 static const TRegisterBitDef KClockWakeupGroupTable[ Prcm::KSupportedClockCount ][ Prcm::KSupportedWakeupGroupCount ] =

   670 	{

   671 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMpu,		///< DPLL1

   672 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkIva2Pll,	///< DPLL2

   673 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkCore,		///< DPLL3

   674 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkPeriph,		///< DPLL4

   675 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkPeriph2,	///< DPLL5

   676 

   677 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkPrcmInterface,

   678 

   679 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkEmu,		///< Emulation clock

   680 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkNeon,

   681 

   682 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkL3Domain,

   683 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkL4Domain,

   684 

   685 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency

   686 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency

   687 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkRM_F,			///< Reset manager functional clock	

   688 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClk96M,			///< 96MHz clock

   689 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClk120M,			///< 120MHz clock

   690 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSysOut,

   691 

   692 	// Functional clocks

   693 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkTv_F,

   694 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkDss1_F,

   695 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkDss2_F,

   696 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkCsi2_F,

   697 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkCam_F,

   698 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkIva2_F,

   699 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMmc1_F,

   700 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMmc2_F,

   701 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMmc3_F,

   702 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMsPro_F,

   703 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkHdq_F,

   704 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMcBsp1_F,

   705 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMcBsp2_F,

   706 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMcBsp3_F,

   707 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMcBsp4_F,

   708 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMcBsp5_F,

   709 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMcSpi1_F,

   710 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMcSpi2_F,

   711 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMcSpi3_F,

   712 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMcSpi4_F,

   713 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkI2c1_F,

   714 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkI2c2_F,

   715 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkI2c3_F,

   716 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkUart1_F,

   717 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkUart2_F,

   718 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkUart3_F,

   719 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt1_F,

   720 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt2_F,

   721 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt3_F,

   722 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt4_F,

   723 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt5_F,

   724 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt6_F,

   725 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt7_F,

   726 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt8_F,

   727 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt9_F,

   728 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt10_F,

   729 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpt11_F,

   730 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkUsbTll_F,

   731 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkTs_F,

   732 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkCpeFuse_F,

   733 

   734 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSgx_F,

   735 

   736 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkUsim_F,

   737 		{ { KPM_MPUGRPSEL_WKUP, KBit7, KBit7, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSmartReflex2_F,

   738 		{ { KPM_MPUGRPSEL_WKUP, KBit6, KBit6, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSmartReflex1_F,

   739 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkWdt2_F,

   740 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkWdt3_F,

   741 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpio1_F,

   742 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpio2_F,

   743 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpio3_F,

   744 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpio4_F,

   745 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpio5_F,

   746 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkGpio6_F,

   747 

   748 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkUsb120_F,		///< USB host 120MHz functional clock

   749 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkUsb48_F,		///< USB host 48MHz functional clock

   750 

   751 

   752 	// Interface clocks

   753 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkDss_I,

   754 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkCam_I,

   755 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkIcr_I,

   756 		{ { KPM_MPUGRPSEL1_CORE, KBit24, KBit24, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit24, KBit24, 0 } },			// EClkMmc1_I,

   757 		{ { KPM_MPUGRPSEL1_CORE, KBit25, KBit25, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit25, KBit25, 0 } },			// EClkMmc2_I,

   758 		{ { KPM_MPUGRPSEL1_CORE, KBit30, KBit30, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit30, KBit30, 0 } },			// EClkMmc3_I,

   759 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMsPro_I,

   760 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkHdq_I,

   761 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkAes1_I,

   762 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkAes2_I,

   763 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSha11_I,

   764 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSha12_I,

   765 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkDes1_I,

   766 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkDes2_I,

   767 		{ { KPM_MPUGRPSEL1_CORE, KBit9, KBit9, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit9, KBit9, 0 } },			// EClkMcBsp1_I,

   768 		{ { KPM_MPUGRPSEL_PER, KBit0, KBit0, 0 },	{ KPM_IVA2GRPSEL_PER, KBit0, KBit0, 0 } },			// EClkMcBsp2_I,

   769 		{ { KPM_MPUGRPSEL_PER, KBit1, KBit1, 0 },	{ KPM_IVA2GRPSEL_PER, KBit1, KBit1, 0 } },			// EClkMcBsp3_I,

   770 		{ { KPM_MPUGRPSEL_PER, KBit2, KBit2, 0 },	{ KPM_IVA2GRPSEL_PER, KBit2, KBit2, 0 } },			// EClkMcBsp4_I,

   771 		{ { KPM_MPUGRPSEL1_CORE, KBit10, KBit10, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit10, KBit10, 0 } },			// EClkMcBsp5_I,

   772 		{ { KPM_MPUGRPSEL1_CORE, KBit15, KBit15, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit15, KBit15, 0 } },			// EClkI2c1_I,

   773 		{ { KPM_MPUGRPSEL1_CORE, KBit16, KBit16, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit16, KBit16, 0 } },			// EClkI2c2_I,

   774 		{ { KPM_MPUGRPSEL1_CORE, KBit17, KBit17, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit17, KBit17, 0 } },			// EClkI2c3_I,

   775 		{ { KPM_MPUGRPSEL1_CORE, KBit13, KBit13, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit13, KBit13, 0 } },			// EClkUart1_I,

   776 		{ { KPM_MPUGRPSEL1_CORE, KBit14, KBit14, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit14, KBit14, 0 } },			// EClkUart2_I,

   777 		{ { KPM_MPUGRPSEL_PER, KBit11, KBit11, 0 },	{ KPM_IVA2GRPSEL_PER, KBit11, KBit11, 0 } },			// EClkUart3_I,

   778 		{ { KPM_MPUGRPSEL1_CORE, KBit18, KBit18, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit18, KBit18, 0 } },			// EClkMcSpi1_I,

   779 		{ { KPM_MPUGRPSEL1_CORE, KBit19, KBit19, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit19, KBit19, 0 } },			// EClkMcSpi2_I,

   780 		{ { KPM_MPUGRPSEL1_CORE, KBit20, KBit20, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit20, KBit20, 0 } },			// EClkMcSpi3_I,

   781 		{ { KPM_MPUGRPSEL1_CORE, KBit21, KBit21, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit21, KBit21, 0 } },			// EClkMcSpi4_I,

   782 		{ { KPM_MPUGRPSEL_WKUP, KBit0, KBit0, 0 },	{ KPM_IVA2GRPSEL_WKUP, KBit0, KBit0, 0 } },			// EClkGpt1_I,

   783 		{ { KPM_MPUGRPSEL_PER, KBit3, KBit3, 0 },	{ KPM_IVA2GRPSEL_PER, KBit3, KBit3, 0 } },			// EClkGpt2_I,

   784 		{ { KPM_MPUGRPSEL_PER, KBit4, KBit4, 0 },	{ KPM_IVA2GRPSEL_PER, KBit4, KBit4, 0 } },			// EClkGpt3_I,

   785 		{ { KPM_MPUGRPSEL_PER, KBit5, KBit5, 0 },	{ KPM_IVA2GRPSEL_PER, KBit5, KBit5, 0 } },			// EClkGpt4_I,

   786 		{ { KPM_MPUGRPSEL_PER, KBit6, KBit6, 0 },	{ KPM_IVA2GRPSEL_PER, KBit6, KBit6, 0 } },			// EClkGpt5_I,

   787 		{ { KPM_MPUGRPSEL_PER, KBit7, KBit7, 0 },	{ KPM_IVA2GRPSEL_PER, KBit7, KBit7, 0 } },			// EClkGpt6_I,

   788 		{ { KPM_MPUGRPSEL_PER, KBit8, KBit9, 0 },	{ KPM_IVA2GRPSEL_PER, KBit8, KBit8, 0 } },			// EClkGpt7_I,

   789 		{ { KPM_MPUGRPSEL_PER, KBit9, KBit9, 0 },	{ KPM_IVA2GRPSEL_PER, KBit9, KBit9, 0 } },			// EClkGpt8_I,

   790 		{ { KPM_MPUGRPSEL_PER, KBit10, KBit10, 0 },	{ KPM_IVA2GRPSEL_PER, KBit10, KBit10, 0 } },			// EClkGpt9_I,

   791 		{ { KPM_MPUGRPSEL1_CORE, KBit11, KBit11, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit11, KBit11, 0 } },			// EClkGpt10_I,

   792 		{ { KPM_MPUGRPSEL1_CORE, KBit12, KBit12, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit12, KBit12, 0 } },			// EClkGpt11_I,

   793 		{ { KPM_MPUGRPSEL_WKUP, KBit1, KBit1, 0 },	{ KPM_IVA2GRPSEL_WKUP, KBit1, KBit1, 0 } },			// EClkGpt12_I,

   794 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkMailboxes_I,

   795 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkOmapSCM_I,

   796 		{ { KPM_MPUGRPSEL1_CORE, KBit4, KBit4, 0 },	{ KPM_IVA2GRPSEL1_CORE, KBit4, KBit4, 0 } },			// EClkHsUsbOtg_I,

   797 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSdrc_I,

   798 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkPka_I,

   799 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkRng_I,

   800 		{ { KPM_MPUGRPSEL3_CORE, KBit2, KBit2, 0 },	{ KPM_IVA2GRPSEL3_CORE, KBit2, KBit2, 0 } },			// EClkUsbTll_I,

   801 

   802 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSgx_I,

   803 

   804 		{ { KPM_MPUGRPSEL_WKUP, KBit9, KBit9, 0 },	{ KPM_IVA2GRPSEL_WKUP, KBit9, KBit9, 0 } },			// EClkUsim_I,

   805 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkWdt1_I,

   806 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkWdt2_I,

   807 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkWdt3_I,

   808 		{ { KPM_MPUGRPSEL_WKUP, KBit3, KBit3, 0 },	{ KPM_IVA2GRPSEL_WKUP, KBit3, KBit3, 0 } },			// EClkGpio1_I,

   809 		{ { KPM_MPUGRPSEL_PER, KBit13, KBit13, 0 },	{ KPM_IVA2GRPSEL_PER, KBit13, KBit13, 0 } },			// EClkGpio2_I,

   810 		{ { KPM_MPUGRPSEL_PER, KBit14, KBit14, 0 },	{ KPM_IVA2GRPSEL_PER, KBit14, KBit14, 0 } },			// EClkGpio3_I,

   811 		{ { KPM_MPUGRPSEL_PER, KBit15, KBit15, 0 },	{ KPM_IVA2GRPSEL_PER, KBit15, KBit15, 0 } },			// EClkGpio4_I,

   812 		{ { KPM_MPUGRPSEL_PER, KBit16, KBit16, 0 },	{ KPM_IVA2GRPSEL_PER, KBit16, KBit16, 0 } },			// EClkGpio5_I,

   813 		{ { KPM_MPUGRPSEL_PER, KBit17, KBit17, 0 },	{ KPM_IVA2GRPSEL_PER, KBit17, KBit17, 0 } },			// EClkGpio6_I,

   814 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClk32Sync_I,

   815 

   816 		{ { KPM_MPUGRPSEL_USBHOST, KBit0, KBit0, 0 },	{ KPM_IVA2GRPSEL_USBHOST, KBit0, KBit0, 0 } },			// EClkUsb_I,			///< USB host interface clock

   817 

   818 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClk48M

   819 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClk12M

   820 

   821 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSysClk

   822 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkAltClk

   823 		{ { KDummy, 0, KDummyReadAsDisabled, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } }			// EClkSysClk32k

   824 	};

   825 

   826 	__ASSERT_COMPILE( Prcm::EWakeDomainMpu == 0 );

   827 	__ASSERT_COMPILE( Prcm::EWakeDomainCore == 1 );

   828 	__ASSERT_COMPILE( Prcm::EWakeDomainIva2 == 2 );

   829 	__ASSERT_COMPILE( Prcm::EWakeDomainPeripheral == 3 );

   830 	__ASSERT_COMPILE( Prcm::EWakeDomainDss == 4 );

   831 	__ASSERT_COMPILE( Prcm::EWakeDomainWakeup == 5 );

   832 	__ASSERT_COMPILE( Prcm::KSupportedWakeupDomainCount == 6 );

   833 

   834 struct TWakeupDomainInfo

   835 	{

   836 	// To save space, there's an assumption here that all domain dependency configuration for

   837 	// a single clock is in one register, and a single bit defines the dependency,

   838 	// 1 = dependant, 0 = independant

   839 	// The bits are defined here by bit number rather than by mask

   840 	TUint32		iRegister;

   841 	TInt8		iBitNumber[ Prcm::KSupportedWakeupDomainCount ];	///< bit number to modify, -1 if not supported

   842 	};

   843 

   844 static const TWakeupDomainInfo KClockWakeupDomainTable[ Prcm::KSupportedClockCount ] =

   845 	{

   846 		// REGISTER			MPU		CORE	IVA2	PER		DSS		WAKE

   847 		{ KPM_WKDEP_MPU,	{-1,		0,		2,		7,		5,		-1 } },		// EClkMpu,		///< DPLL1

   848 		{ KPM_WKDEP_IVA2,	{1,			0,		-1,		7,		5,		4 } },		// EClkIva2Pll,	///< DPLL2

   849 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkCore,		///< DPLL3

   850 		{ KPM_WKDEP_PER,	{1,			0,		2,		-1,		-1,		4 } },		// EClkPeriph,		///< DPLL4

   851 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkPeriph2,	///< DPLL5

   852 

   853 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkPrcmInterface,

   854 

   855 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkEmu,		///< Emulation clock

   856 		{ KPM_WKDEP_NEON,	{1,			-1,		-1,		-1,		-1,		-1 } },		// EClkNeon,

   857 

   858 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkL3Domain,

   859 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkL4Domain,

   860 

   861 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency

   862 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency

   863 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkRM_F,			///< Reset manager functional clock	

   864 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClk96M,			///< 96MHz clock

   865 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClk120M,			///< 120MHz clock

   866 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSysOut,

   867 

   868 	// Functional clocks

   869 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkTv_F,

   870 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkDss1_F,

   871 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkDss2_F,

   872 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkCsi2_F,

   873 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkCam_F,

   874 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkIva2_F,

   875 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMmc1_F,

   876 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMmc2_F,

   877 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMmc3_F,

   878 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMsPro_F,

   879 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkHdq_F,

   880 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp1_F,

   881 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp2_F,

   882 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp3_F,

   883 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp4_F,

   884 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp5_F,

   885 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcSpi1_F,

   886 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcSpi2_F,

   887 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcSpi3_F,

   888 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcSpi4_F,

   889 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkI2c1_F,

   890 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkI2c2_F,

   891 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkI2c3_F,

   892 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUart1_F,

   893 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUart2_F,

   894 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUart3_F,

   895 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt1_F,

   896 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt2_F,

   897 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt3_F,

   898 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt4_F,

   899 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt5_F,

   900 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt6_F,

   901 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt7_F,

   902 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt8_F,

   903 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt9_F,

   904 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt10_F,

   905 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt11_F,

   906 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUsbTll_F,

   907 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkTs_F,

   908 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkCpeFuse_F,

   909 

   910 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSgx_F,

   911 

   912 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUsim_F,

   913 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSmartReflex2_F,

   914 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSmartReflex1_F,

   915 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkWdt2_F,

   916 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkWdt3_F,

   917 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio1_F,

   918 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio2_F,

   919 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio3_F,

   920 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio4_F,

   921 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio5_F,

   922 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio6_F,

   923 

   924 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUsb120_F,		///< USB host 120MHz functional clock

   925 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUsb48_F,		///< USB host 48MHz functional clock

   926 

   927 

   928 	// Interface clocks

   929 		{ KPM_WKDEP_DSS,	{1,		-1,		2,		-1,		-1,		4 } },		// EClkDss_I,

   930 		{ KPM_WKDEP_CAM,	{1,		-1,		2,		-1,		-1,		4 } },		// EClkCam_I,

   931 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkIcr_I,

   932 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMmc1_I,

   933 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMmc2_I,

   934 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMmc3_I,

   935 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMsPro_I,

   936 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkHdq_I,

   937 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkAes1_I,

   938 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkAes2_I,

   939 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSha11_I,

   940 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSha12_I,

   941 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkDes1_I,

   942 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkDes2_I,

   943 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp1_I,

   944 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp2_I,

   945 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp3_I,

   946 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp4_I,

   947 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcBsp5_I,

   948 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkI2c1_I,

   949 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkI2c2_I,

   950 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkI2c3_I,

   951 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUart1_I,

   952 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUart2_I,

   953 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUart3_I,

   954 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcSpi1_I,

   955 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcSpi2_I,

   956 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcSpi3_I,

   957 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMcSpi4_I,

   958 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt1_I,

   959 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt2_I,

   960 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt3_I,

   961 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt4_I,

   962 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt5_I,

   963 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt6_I,

   964 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt7_I,

   965 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt8_I,

   966 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt9_I,

   967 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt10_I,

   968 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt11_I,

   969 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpt12_I,

   970 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkMailboxes_I,

   971 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkOmapSCM_I,

   972 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkHsUsbOtg_I,

   973 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSdrc_I,

   974 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkPka_I,

   975 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkRng_I,

   976 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUsbTll_I,

   977 

   978 		{ KPM_WKDEP_SGX,	{1,		-1,		2,		-1,		-1,		4 } },		// EClkSgx_I,

   979 

   980 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkUsim_I,

   981 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkWdt1_I,

   982 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkWdt2_I,

   983 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkWdt3_I,

   984 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio1_I,

   985 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio2_I,

   986 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio3_I,

   987 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio4_I,

   988 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio5_I,

   989 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkGpio6_I,

   990 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClk32Sync_I,

   991 

   992 		{ KPM_WKDEP_USBHOST,	{1,	0,		2,		-1,		-1,		4	} },		// EClkUsb_I,			///< USB host interface clock

   993 

   994 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClk48M

   995 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClk12M

   996 		

   997 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSysClk

   998 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkAltClk

   999 		{ KDummy,		{-1,		-1,		-1,		-1,		-1,		-1 } },		// EClkSysClk32k

  1000 		// REGISTER			MPU		CORE	IVA2	PER		DSS		WAKE

  1001 	};

  1002 

  1003 struct TPowerDomainControl

  1004 	{

  1005 	TUint32		iRegister;

  1006 	TUint8		iShift;			///< shift to move bits into position

  1007 	TUint8		iAllowedMask;	///< mask of which modes are supported

  1008 	TUint8		__spare[2];

  1009 	};

  1010 

  1011 const TUint8	KPowerAllowedOff		= 1 << Prcm::EPowerOff;

  1012 const TUint8	KPowerAllowedOn			= 1 << Prcm::EPowerOn;

  1013 const TUint8	KPowerAllowedRetention	= 1 << Prcm::EPowerRetention;

  1014 const TUint8	KPowerAllowedOnOffRetention	=	(KPowerAllowedOff bitor KPowerAllowedOn bitor KPowerAllowedRetention);

  1015 const TUint8	KPowerModeMask			= 0x3;

  1016 

  1017 static const TPowerDomainControl KPowerDomainControl[] =

  1018 	{

  1019 		// iRegister			iShift	iAllowedMask

  1020 		{ KPM_PWSTCTRL_MPU,		0,		KPowerAllowedOnOffRetention	},	// EPowerDomainMpu,

  1021 		{ KPM_PWSTCTRL_IVA2,	0,		KPowerAllowedOnOffRetention	},	// EPowerDomainIva2,

  1022 		{ KPM_PWSTCTRL_NEON,	0,		KPowerAllowedOnOffRetention	},	// EPowerDomainNeon,

  1023 		{ KPM_PWSTCTRL_CORE,	0,		KPowerAllowedOnOffRetention },	// EPowerDomainCore,

  1024 		{ KPM_PWSTCTRL_SGX,		0,		KPowerAllowedOnOffRetention },	// EPowerDomainSgx,

  1025 		{ KPM_PWSTCTRL_DSS,		0,		KPowerAllowedOnOffRetention	},	// EPowerDomainDss,

  1026 		{ KPM_PWSTCTRL_CAM,		0,		KPowerAllowedOnOffRetention	},	// EPowerDomainCamera,

  1027 		{ KPM_PWSTCTRL_USBHOST,	0,		KPowerAllowedOnOffRetention	},	// EPowerDomainUsb,

  1028 		{ KPM_PWSTCTRL_PER,		0,		KPowerAllowedOnOffRetention	}	// EPowerDomainPer,

  1029 	};

  1030 __ASSERT_COMPILE( (sizeof(KPowerDomainControl) / sizeof( KPowerDomainControl[0] )) == Prcm::KSupportedPowerDomainCount );

  1031 

  1032 struct TGptClkSelInfo

  1033 	{

  1034 	TUint32	iRegister;

  1035 	TUint32	iMask;

  1036 	};

  1037 

  1038 static const TGptClkSelInfo KGptClockSourceInfo[ Prcm::KSupportedGptCount ] =

  1039 	{

  1040 		{ KCM_CLKSEL_WKUP, KBit0 },	//	EGpt1,

  1041 		{ KCM_CLKSEL_PER, KBit0 },	//	EGpt2,

  1042 		{ KCM_CLKSEL_PER, KBit1 },	//	EGpt3,

  1043 		{ KCM_CLKSEL_PER, KBit2 },	//	EGpt4,

  1044 		{ KCM_CLKSEL_PER, KBit3 },	//	EGpt5,

  1045 		{ KCM_CLKSEL_PER, KBit4 },	//	EGpt6,

  1046 		{ KCM_CLKSEL_PER, KBit5 },	//	EGpt7,

  1047 		{ KCM_CLKSEL_PER, KBit6 },	//	EGpt8,

  1048 		{ KCM_CLKSEL_PER, KBit7 },	//	EGpt9, 

  1049 		{ KCM_CLKSEL_CORE, KBit6 },	//	EGpt10,

  1050 		{ KCM_CLKSEL_CORE, KBit7 },	//	EGpt11,

  1051 		{ KDummy, 0 },			//	EGpt12	- clocked from security block

  1052 	};

  1053 

  1054 // This table is used to find the source clock for a given clock. That is, by looking up a

  1055 // specific clock in this table, you can find out which DPLL/divider it was derived from.

  1056 // Following the chain backwards to SYSCLK allows building of the total multiply and

  1057 // divide applied to SYSCLK to get the given clock

  1058 enum TClockSourceType

  1059 	{

  1060 	EIgnore,	// not implemented yet...

  1061 	EDpll,		// this clock is derived from a PLL

  1062 	EDivider,	// this clock is divied from a given clock

  1063 	EDivMux,	// divider fed by mux-selectable input clock

  1064 	EMux,		// fed by mux-selectable input clock

  1065 	EDuplicate,	// this clock is a duplicate of another clock

  1066 	E96MMux,	// 96MHz mux-selected clock source

  1067 	E54MMux,	// 54MHz mux-selected clock source

  1068 	E48MMux,	// 48MHz mux-selected clock source

  1069 	EDiv4,		// specified clock source divided by 4

  1070 	};

  1071 

  1072 struct TClockSourceInfo

  1073 	{

  1074 	TClockSourceType	iType : 8;	// type of the source for this clock

  1075 	union	{

  1076 		Prcm::TClock	iClock : 8;		// the clock that feeds this divider, or which this is a duplicate of

  1077 		Prcm::TPll		iPll : 8;		// the PLL that generates this clock

  1078 		Prcm::TGpt		iGpt : 8;		// conversion to TGpt type for the clock we are interested in

  1079 		};

  1080 	};

  1081 

  1082 static const TClockSourceInfo KClockSourceInfo[] =

  1083 	{

  1084 		{ EDpll,		(Prcm::TClock)Prcm::EDpll1 },			// EClkMpu,

  1085 		{ EDpll,		(Prcm::TClock)Prcm::EDpll2 },			// EClkIva2Pll,

  1086 		{ EDpll,		(Prcm::TClock)Prcm::EDpll3 },			// EClkCore,

  1087 		{ EDpll,		(Prcm::TClock)Prcm::EDpll4 },			// EClkPeriph,

  1088 		{ EDpll,		(Prcm::TClock)Prcm::EDpll5 },			// EClkPeriph2,

  1089 		{ EDuplicate,	Prcm::EClkSysClk },		// EClkPrcmInterface,

  1090 		{ EIgnore,		(Prcm::TClock)0 },		// EClkEmu,

  1091 		{ EDuplicate,	Prcm::EClkMpu },		// EClkNeon,

  1092 		{ EDivider,		Prcm::EClkCore },		// EClkL3Domain,

  1093 		{ EDivider,		Prcm::EClkL3Domain },	// EClkL4Domain,

  1094 		{ EDivider,		Prcm::EClkCore },		// EClkMpuPll_Bypass,

  1095 		{ EDivider,		Prcm::EClkCore },		// EClkIva2Pll_Bypass,

  1096 		{ EDivider,		Prcm::EClkL4Domain },	// EClkRM_F,

  1097 		{ E96MMux,		Prcm::EClkPeriph },		// EClk96M,

  1098 		{ EDivider,		Prcm::EClkPeriph2 },	// EClk120M,

  1099 		{ EDivMux,		(Prcm::TClock)0 },		// EClkSysOut,

  1100 

  1101 	// Functional clocks

  1102 		{ E54MMux,		Prcm::EClkPeriph },

  1103 		{ EDivider,		Prcm::EClkPeriph },		// EClkDss1_F,

  1104 		{ EDuplicate,	Prcm::EClkSysClk },		// EClkDss2_F,

  1105 		{ EDuplicate,	Prcm::EClk96M },		// EClkCsi2_F,

  1106 		{ EDivider,		Prcm::EClkPeriph },		// EClkCam_F,

  1107 		{ EDuplicate,	Prcm::EClkIva2Pll },	// EClkIva2_F,

  1108 		{ EDuplicate,	Prcm::EClk96M },		// EClkMmc1_F,

  1109 		{ EDuplicate,	Prcm::EClk96M },		// EClkMmc2_F,

  1110 		{ EDuplicate,	Prcm::EClk96M },		// EClkMmc3_F,

  1111 		{ EDuplicate,	Prcm::EClk96M },		// EClkMsPro_F,

  1112 		{ EDuplicate,	Prcm::EClk12M },		// EClkHdq_F,

  1113 		{ EDuplicate,	Prcm::EClk96M },		// EClkMcBsp1_F,

  1114 		{ EDuplicate,	Prcm::EClk96M },		// EClkMcBsp2_F,

  1115 		{ EDuplicate,	Prcm::EClk96M },		// EClkMcBsp3_F,

  1116 		{ EDuplicate,	Prcm::EClk96M },		// EClkMcBsp4_F,

  1117 		{ EDuplicate,	Prcm::EClk96M },		// EClkMcBsp5_F,

  1118 		{ EDuplicate,	Prcm::EClk48M },		// EClkMcSpi1_F,

  1119 		{ EDuplicate,	Prcm::EClk48M },		// EClkMcSpi2_F,

  1120 		{ EDuplicate,	Prcm::EClk48M },		// EClkMcSpi3_F,

  1121 		{ EDuplicate,	Prcm::EClk48M },		// EClkMcSpi4_F,

  1122 		{ EDuplicate,	Prcm::EClk96M },		// EClkI2c1_F,

  1123 		{ EDuplicate,	Prcm::EClk96M },		// EClkI2c2_F,

  1124 		{ EDuplicate,	Prcm::EClk96M },		// EClkI2c3_F,

  1125 		{ EDuplicate,	Prcm::EClk48M },		// EClkUart1_F,

  1126 		{ EDuplicate,	Prcm::EClk48M },		// EClkUart2_F,

  1127 		{ EDuplicate,	Prcm::EClk48M },		// EClkUart3_F,

  1128 		{ EMux,			(Prcm::TClock)Prcm::EGpt1 },			// EClkGpt1_F,

  1129 		{ EMux,			(Prcm::TClock)Prcm::EGpt2 },			// EClkGpt2_F,

  1130 		{ EMux,			(Prcm::TClock)Prcm::EGpt3 },			// EClkGpt3_F,

  1131 		{ EMux,			(Prcm::TClock)Prcm::EGpt4 },			// EClkGpt4_F,

  1132 		{ EMux,			(Prcm::TClock)Prcm::EGpt5 },			// EClkGpt5_F,

  1133 		{ EMux,			(Prcm::TClock)Prcm::EGpt6 },			// EClkGpt6_F,

  1134 		{ EMux,			(Prcm::TClock)Prcm::EGpt7 },			// EClkGpt7_F,