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1 ; Copyright (c) 2003-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 ; All rights reserved. |
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3 ; This component and the accompanying materials are made available |
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4 ; under the terms of the License "Eclipse Public License v1.0" |
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5 ; which accompanies this distribution, and is available |
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6 ; at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 ; |
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8 ; Initial Contributors: |
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9 ; Nokia Corporation - initial contribution. |
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10 ; |
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11 ; Contributors: |
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12 ; |
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13 ; Description: |
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14 ; omap3530/beagleboard/bootstrap/beagle.s |
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15 ; Template for platform specific boot code |
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16 ; |
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17 |
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18 GBLL __VARIANT_S__ ; indicates that this is platform-specific code |
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19 GBLL __BEAGLEBOARD_S__ ; indicates which source file this is |
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20 |
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21 INCLUDE bootcpu.inc |
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22 |
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23 ; |
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24 ;******************************************************************************* |
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25 ; |
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26 ; Platform specific constant definitions |
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27 |
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28 DRamBankBase EQU 0x80000000 ; 128M of DRAM |
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29 DRamBankMaxSize EQU 0x08000000 |
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30 |
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31 ; HW used by bootstrap |
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32 Serial0PhysBase EQU 0x4806A000 |
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33 Serial1PhysBase EQU 0x4806C000 |
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34 Serial2PhysBase EQU 0x49020000 |
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35 PrimaryIOBase EQU 0xC6000000 ; c.f. KPrimaryIOBase in mmboot.h |
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36 Serial0LinBase EQU PrimaryIOBase + 0x0006A000 |
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37 Serial1LinBase EQU PrimaryIOBase + 0x0006C000 |
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38 Serial2LinBase EQU PrimaryIOBase + 0x00420000 |
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39 |
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40 SuperPageAddr EQU 0x85000000 ; boot stack goes just after this |
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41 TheHwvd EQU 0x09080001 ; this is arbitary 0908 are CPU and ASSP 01 is variant |
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42 |
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43 ; |
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44 ;******************************************************************************* |
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45 ; |
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46 |
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47 AREA |Boot$$Code|, CODE, READONLY, ALIGN=6 |
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48 |
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49 ; |
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50 ;******************************************************************************* |
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51 ; |
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52 |
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53 |
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54 |
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55 |
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56 ;******************************************************************************* |
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57 ; Initialise Hardware |
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58 ; Initialise CPU registers |
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59 ; Determine the hardware configuration |
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60 ; Determine the reset reason. If it is wakeup from a low power mode, perform |
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61 ; whatever reentry sequence is required and jump back to the kernel. |
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62 ; Set up the memory controller so that at least some RAM is available |
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63 ; Set R10 to point to the super page or to a temporary version of the super page |
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64 ; with at least the following fields valid: |
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65 ; iBootTable, iCodeBase, iActiveVariant, iCpuId |
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66 ; In debug builds initialise the debug serial port |
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67 ; |
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68 ; Enter with: |
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69 ; R12 points to TRomHeader |
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70 ; NO STACK |
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71 ; R14 = return address (as usual) |
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72 ; |
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73 ; All registers may be modified by this call |
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74 ;******************************************************************************* |
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75 IF CFG_BootLoader |
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76 ; For bootloader we only get here on a full reset |
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77 ; Other resets will simply jump back into the previously-loaded image |
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78 EXPORT DoInitialiseHardware |
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79 DoInitialiseHardware ROUT |
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80 ELSE |
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81 EXPORT InitialiseHardware |
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82 InitialiseHardware ROUT |
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83 ENDIF |
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84 MOV r13, lr ; save return address |
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85 ADRL r1, ParameterTable ; pass address of parameter table |
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86 BL InitCpu ; initialise CPU/MMU registers |
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87 |
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88 ; Put your hardware initialising code here |
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89 |
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90 IF CFG_DebugBootRom |
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91 BL InitDebugPort |
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92 ENDIF |
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93 |
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94 ; Set up the required super page values |
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95 LDR r10, =SuperPageAddr ; initial super page |
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96 LDR r0, =TheHwvd ; variant code |
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97 STR r0, [r10, #SSuperPageBase_iActiveVariant] |
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98 STR r0, [r10, #SSuperPageBase_iHwStartupReason] ; reset reason (from hardware) |
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99 ADD r1, r10, #CpuPageOffset |
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100 STR r1, [r10, #SSuperPageBase_iMachineData] |
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101 ADRL r0, BootTable |
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102 STR r0, [r10, #SSuperPageBase_iBootTable] ; Set the boot function table |
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103 STR r12, [r10, #SSuperPageBase_iCodeBase] ; Set the base address of bootstrap code |
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104 MRC p15, 0, r0, c0, c0, 0 ; read CPU ID from CP15 (remove if no CP15) |
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105 STR r0, [r10, #SSuperPageBase_iCpuId] |
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106 |
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107 MOV pc, r13 ; return |
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108 |
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109 |
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110 |
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111 |
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112 |
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113 ;******************************************************************************* |
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114 ; Notify an unrecoverable error during the boot process |
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115 ; |
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116 ; Enter with: |
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117 ; R14 = address at which fault detected |
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118 ; |
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119 ; Don't return |
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120 ;******************************************************************************* |
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121 EXPORT Fault |
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122 Fault ROUT |
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123 B BasicFaultHandler ; generic handler dumps registers via debug |
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124 ; serial port |
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125 |
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126 |
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127 |
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128 |
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129 |
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130 ;******************************************************************************* |
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131 ; Reboot the system |
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132 ; |
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133 ; Enter with: |
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134 ; R0 = reboot reason code |
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135 ; |
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136 ; Don't return (of course) |
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137 ;******************************************************************************* |
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138 ALIGN 32, 0 |
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139 EXPORT RestartEntry |
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140 RestartEntry ROUT |
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141 ; save R0 parameter in HW dependent register which is preserved over reset |
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142 ; put HW specific code here to reset system |
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143 SUB pc, pc, #8 |
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144 |
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145 |
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146 |
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147 |
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148 |
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149 ;******************************************************************************* |
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150 ; Get a pointer to the list of RAM banks |
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151 ; |
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152 ; The pointer returned should point to a list of {BASE; MAXSIZE;} pairs, where |
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153 ; BASE is the physical base address of the bank and MAXSIZE is the maximum |
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154 ; amount of RAM which may be present in that bank. MAXSIZE should be a power of |
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155 ; 2 and BASE should be a multiple of MAXSIZE. The generic code will examine the |
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156 ; specified range of addresses and determine the actual amount of RAM if any |
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157 ; present in the bank. The list is terminated by an entry with zero size. |
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158 ; |
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159 ; The pointer returned will usually be to constant data, but could equally well |
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160 ; point to RAM if dynamic determination of the list is required. |
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161 ; |
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162 ; Enter with : |
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163 ; R10 points to super page |
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164 ; R12 points to ROM header |
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165 ; R13 points to valid stack |
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166 ; |
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167 ; Leave with : |
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168 ; R0 = pointer |
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169 ; Nothing else modified |
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170 ;******************************************************************************* |
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171 GetRamBanks ROUT |
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172 ADR r0, %FT1 |
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173 MOV pc, lr |
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174 1 |
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175 ; DRAM has been set-up by boot loader so no need to configure or probe |
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176 DCD DRamBankBase | RAM_VERBATIM, DRamBankMaxSize |
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177 DCD 0,0 ; terminator |
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178 |
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179 |
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180 |
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181 |
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182 |
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183 ;******************************************************************************* |
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184 ; Get a pointer to the list of ROM banks |
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185 ; |
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186 ; The pointer returned should point to a list of entries of SRomBank structures, |
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187 ; usually declared with the ROM_BANK macro. |
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188 ; The list is terminated by a zero size entry (four zero words) |
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189 ; |
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190 ; ROM_BANK PB, SIZE, LB, W, T, RS, SS |
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191 ; PB = physical base address of bank |
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192 ; SIZE = size of bank |
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193 ; LB = linear base if override required - usually set this to 0 |
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194 ; W = bus width (ROM_WIDTH_8, ROM_WIDTH_16, ROM_WIDTH_32) |
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195 ; T = type (see TRomType enum in kernboot.h) |
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196 ; RS = random speed |
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197 ; SS = sequential speed |
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198 ; |
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199 ; Only PB, SIZE, LB are used by the rest of the bootstrap. |
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200 ; The information given here can be modified by the SetupRomBank call, if |
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201 ; dynamic detection and sizing of ROMs is required. |
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202 ; |
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203 ; Enter with : |
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204 ; R10 points to super page |
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205 ; R12 points to ROM header |
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206 ; R13 points to valid stack |
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207 ; |
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208 ; Leave with : |
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209 ; R0 = pointer |
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210 ; Nothing else modified |
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211 ;******************************************************************************* |
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212 GetRomBanks ROUT |
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213 ADR r0, %FT1 |
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214 MOV pc, lr |
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215 1 |
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216 DCD 0,0,0,0 ; terminator |
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217 |
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218 |
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219 |
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220 |
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221 |
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222 ;******************************************************************************* |
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223 ; Get a pointer to the list of hardware banks |
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224 ; |
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225 ; The pointer returned should point to a list of hardware banks declared with |
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226 ; the HW_MAPPING and/or HW_MAPPING_EXT macros. A zero word terminates the list. |
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227 ; For the direct memory model, all hardware on the system should be mapped here |
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228 ; and the mapping will set linear address = physical address. |
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229 ; For the moving or multiple model, only the hardware required to boot the kernel |
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230 ; and do debug tracing needs to be mapped here. The linear addresses used will |
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231 ; start at KPrimaryIOBase and step up as required with the order of banks in |
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232 ; the list being maintained in the linear addresses used. |
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233 ; |
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234 ; HW_MAPPING PB, SIZE, MULT |
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235 ; This declares a block of I/O with physical base PB and address range SIZE |
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236 ; blocks each of which has a size determined by MULT. The page size used for |
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237 ; the mapping is determined by MULT. The linear address base of the mapping |
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238 ; will be the next free linear address rounded up to the size specified by |
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239 ; MULT. |
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240 ; The permissions used for the mapping are the standard I/O permissions (BTP_Hw). |
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241 ; |
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242 ; HW_MAPPING_EXT PB, SIZE, MULT |
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243 ; This declares a block of I/O with physical base PB and address range SIZE |
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244 ; blocks each of which has a size determined by MULT. The page size used for |
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245 ; the mapping is determined by MULT. The linear address base of the mapping |
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246 ; will be the next free linear address rounded up to the size specified by |
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247 ; MULT. |
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248 ; The permissions used for the mapping are determined by a BTP_ENTRY macro |
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249 ; immediately following this macro in the HW bank list or by a DCD directive |
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250 ; specifying a different standard permission type. |
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251 ; |
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252 ; HW_MAPPING_EXT2 PB, SIZE, MULT, LIN |
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253 ; This declares a block of I/O with physical base PB and address range SIZE |
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254 ; blocks each of which has a size determined by MULT. The page size used for |
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255 ; the mapping is determined by MULT. The linear address base of the mapping |
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256 ; is specified by the LIN parameter. |
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257 ; The permissions used for the mapping are the standard I/O permissions (BTP_Hw). |
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258 ; |
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259 ; HW_MAPPING_EXT3 PB, SIZE, MULT, LIN |
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260 ; This declares a block of I/O with physical base PB and address range SIZE |
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261 ; blocks each of which has a size determined by MULT. The page size used for |
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262 ; the mapping is determined by MULT. The linear address base of the mapping |
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263 ; is specified by the LIN parameter. |
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264 ; The permissions used for the mapping are determined by a BTP_ENTRY macro |
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265 ; immediately following this macro in the HW bank list or by a DCD directive |
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266 ; specifying a different standard permission type. |
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267 ; |
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268 ; Configurations without an MMU need not implement this function. |
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269 ; |
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270 ; Enter with : |
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271 ; R10 points to super page |
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272 ; R12 points to ROM header |
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273 ; R13 points to valid stack |
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274 ; |
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275 ; Leave with : |
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276 ; R0 = pointer |
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277 ; Nothing else modified |
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278 ;******************************************************************************* |
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279 GetHwBanks ROUT |
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280 ADR r0, %FT1 |
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281 MOV pc, lr |
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282 1 |
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283 HW_MAPPING 0x48000000, 4, HW_MULT_1M ; L4-Core KPrimaryIOBase |
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284 HW_MAPPING 0x49000000, 1, HW_MULT_1M ; L4-Per KPrimaryIOBase + 0x00400000 |
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285 HW_MAPPING 0x50000000, 1, HW_MULT_64K ; SGX Graphic accelerator slave port KPrimaryIOBase + 0x00500000 |
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286 HW_MAPPING 0x54000000, 8, HW_MULT_1M ; L4-Emu KPrimaryIOBase + 0x00600000 |
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287 HW_MAPPING 0x68000000, 1, HW_MULT_1M ; L3 Control Registers KPrimaryIOBase + 0x00E00000 |
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288 HW_MAPPING 0x6E000000, 1, HW_MULT_1M ; GPMC registers KPrimaryIOBase + 0x00F00000 |
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289 |
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290 ; HW_MAPPING 0x5C000000, 48, HW_MULT_1M ; IVA2.2 SS KPrimaryIOBase + 0x01910000 |
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291 ; HW_MAPPING 0x70000000,128, HW_MULT_1M ; SDRC-SMS virtual address space 0 KPrimaryIOBase + 0x08910000 |
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292 ; HW_MAPPING 0x78000000,128, HW_MULT_1M ; Continued |
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293 |
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294 DCD 0 ; terminator |
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295 |
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296 ;******************************************************************************* |
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297 ; Set up RAM bank |
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298 ; |
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299 ; Do any additional RAM controller initialisation for each RAM bank which wasn't |
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300 ; done by InitialiseHardware. |
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301 ; Called twice for each RAM bank :- |
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302 ; First with R3 = 0xFFFFFFFF before bank has been probed |
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303 ; Then, if RAM is present, with R3 indicating validity of each byte lane, ie |
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304 ; R3 bit 0=1 if D0-7 are valid, bit1=1 if D8-15 are valid etc. |
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305 ; For each call R1 specifies the bank physical base address. |
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306 ; |
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307 ; Enter with : |
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308 ; R10 points to super page |
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309 ; R12 points to ROM header |
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310 ; R13 points to stack |
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311 ; R1 = physical base address of bank |
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312 ; R3 = width (bottom 4 bits indicate validity of byte lanes) |
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313 ; 0xffffffff = preliminary initialise |
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314 ; |
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315 ; Leave with : |
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316 ; No registers modified |
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317 ;******************************************************************************* |
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318 SetupRamBank ROUT |
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319 MOV pc, lr |
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320 |
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321 |
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322 |
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323 |
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324 |
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325 ;******************************************************************************* |
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326 ; Set up ROM bank |
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327 ; |
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328 ; Do any required autodetection and autosizing of ROMs and any additional memory |
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329 ; controller initialisation for each ROM bank which wasn't done by |
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330 ; InitialiseHardware. |
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331 ; |
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332 ; The first time this function is called R11=0 and R0 points to the list of |
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333 ; ROM banks returned by the BTF_RomBanks call. This allows any preliminary setup |
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334 ; before autodetection begins. |
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335 ; |
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336 ; This function is subsequently called once for each ROM bank with R11 pointing |
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337 ; to the current information held about that ROM bank (SRomBank structure). |
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338 ; The structure pointed to by R11 should be updated with the size and width |
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339 ; determined. The size should be set to zero if there is no ROM present in the |
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340 ; bank. |
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341 ; |
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342 ; Enter with : |
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343 ; R10 points to super page |
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344 ; R12 points to ROM header |
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345 ; R13 points to stack |
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346 ; R11 points to SRomBank info for this bank |
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347 ; R11 = 0 for preliminary initialise (all banks) |
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348 ; |
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349 ; Leave with : |
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350 ; Update SRomBank info with detected size/width |
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351 ; Set the size field to 0 if the ROM bank is absent |
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352 ; Can modify R0-R4 but not other registers |
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353 ; |
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354 ;******************************************************************************* |
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355 SetupRomBank ROUT |
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356 MOV pc, lr |
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357 |
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358 |
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359 |
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360 |
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361 |
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362 ;******************************************************************************* |
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363 ; Reserve physical memory |
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364 ; |
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365 ; Reserve any physical RAM needed for platform-specific purposes before the |
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366 ; bootstrap begins allocating RAM for page tables/kernel data etc. |
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367 ; |
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368 ; There are two methods for this: |
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369 ; 1. The function ExciseRamArea may be used. This will remove a contiguous |
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370 ; region of physical RAM from the RAM bank list. That region will never |
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371 ; again be identified as RAM. |
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372 ; 2. A list of excluded physical address ranges may be written at [R11]. |
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373 ; This should be a list of (base,size) pairs terminated by a (0,0) entry. |
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374 ; This RAM will still be identified as RAM by the kernel but will not |
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375 ; be allocated by the bootstrap and will subsequently be marked as |
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376 ; allocated by the kernel immediately after boot. |
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377 ; |
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378 ; Enter with : |
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379 ; R10 points to super page |
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380 ; R11 indicates where preallocated RAM list should be written. |
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381 ; R12 points to ROM header |
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382 ; R13 points to stack |
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383 ; |
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384 ; Leave with : |
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385 ; R0-R3 may be modified. Other registers should be preserved. |
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386 ;******************************************************************************* |
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387 ReservePhysicalMemory ROUT |
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388 MOV pc, lr |
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389 |
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390 |
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391 |
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392 |
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393 |
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394 ;******************************************************************************* |
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395 ; Return parameter specified by R0 (see TBootParam enum) |
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396 ; |
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397 ; Enter with : |
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398 ; R0 = parameter number |
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399 ; |
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400 ; Leave with : |
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401 ; If parameter value is supplied, R0 = value and N flag clear |
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402 ; If parameter value is not supplied, N flag set. In this case the |
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403 ; parameter may be defaulted or the system may fault. |
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404 ; R0,R1,R2 modified. No other registers modified. |
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405 ; |
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406 ;******************************************************************************* |
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407 GetParameters ROUT |
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408 ADR r1, ParameterTable |
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409 B FindParameter |
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410 ParameterTable |
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411 ; Include any parameters specified in TBootParam enum here |
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412 ; if you want to override them. |
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413 DCD BPR_UncachedLin, 0 ; parameter number, parameter value |
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414 IF :DEF: CFG_CPU_ARM1136 :LAND: (:LNOT: :DEF: CFG_CPU_ARM1136_ERRATUM_364296_FIXED) |
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415 DCD BPR_FinalMMUCRSet, ExtraMMUCR + MMUCR_FI |
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416 DCD BPR_AuxCRSet, DefaultAuxCRSet + 0x80000000 |
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417 ENDIF |
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418 DCD -1 ; terminator |
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419 |
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420 |
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421 |
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422 |
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423 |
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424 ;******************************************************************************* |
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425 ; Do final platform-specific initialisation before booting the kernel |
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426 ; |
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427 ; Typical uses for this call would be: |
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428 ; 1. Mapping cache flushing areas |
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429 ; 2. Setting up pointers to routines in the bootstrap which are used by |
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430 ; the variant or drivers (eg idle code). |
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431 ; |
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432 ; Enter with : |
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433 ; R10 points to super page |
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434 ; R11 points to TRomImageHeader for the kernel |
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435 ; R12 points to ROM header |
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436 ; R13 points to stack |
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437 ; |
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438 ; Leave with : |
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439 ; R0-R9 may be modified. Other registers should be preserved. |
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440 ; |
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441 ;******************************************************************************* |
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442 FinalInitialise ROUT |
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443 STMFD sp!, {lr} |
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444 LDMFD sp!, {pc} |
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445 |
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446 |
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447 |
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448 |
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449 KHwUartSsr EQU 0x44 ; Supplementary status register |
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450 KTxFifoFullMask EQU 0x01 |
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451 KHwUartThr EQU 0x00 ; Transmit holding register |
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452 |
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453 KHwUartSysC EQU 0x54 ; System configuration register |
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454 KSoftResetMask EQU 0x02 |
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455 KHwUartLcr EQU 0x0C ; Line control register |
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456 KConfigurationModeB EQU 0xBF |
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457 KConfigurationModeA EQU 0x80 |
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458 KOperationMode EQU 0x00 |
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459 K8BitsNoParity1Stop EQU 0x03 |
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460 KHwUartEfr EQU 0x08 ; Enhanced feature register |
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461 KEnhancedEnMask EQU 0x10 |
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462 KHwUartMcr EQU 0x10 |
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463 KTcrTlr EQU 0x40 |
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464 KHwUartFcr EQU 0x08 |
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465 KFifoConfiguration EQU 0x01 ; 8 deep Rx, 8 deep Tx, FIFO Enable |
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466 KHwUartDll EQU 0x00 ; Divisor latch low |
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467 K115k2L EQU 0x1A |
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468 K230k4L EQU 0x0D |
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469 K460k8L EQU 0x08 |
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470 K921k6L EQU 0x04 |
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471 KHwUartMdr1 EQU 0x20 ; Mode definition register 1 |
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472 KUART16XMode EQU 0x00 |
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473 |
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474 ;******************************************************************************* |
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475 ; Output a character to the debug port |
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476 ; |
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477 ; Enter with : |
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478 ; R0 = character to output |
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479 ; R13 points to valid stack |
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480 ; |
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481 ; Leave with : |
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482 ; nothing modified |
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483 ;******************************************************************************* |
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484 DoWriteC ROUT |
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485 IF CFG_DebugBootRom |
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486 STMFD sp!, {r1,lr} |
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487 BL GetDebugPortBase |
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488 |
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489 1 LDR lr, [r1, #KHwUartSsr] ; Check status |
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490 TST lr, #KTxFifoFullMask ; If transmit data full, wait |
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491 BNE %BT1 |
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492 STR r0, [r1, #KHwUartThr] ; Store to data register |
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493 |
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494 LDMFD sp!, {r1,pc} |
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495 ELSE |
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496 MOV pc, lr |
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497 ENDIF |
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498 |
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499 IF CFG_DebugBootRom |
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500 |
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501 ;******************************************************************************* |
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502 ; Initialise the debug port |
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503 ; |
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504 ; Enter with : |
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505 ; R12 points to ROM header |
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506 ; There is no valid stack |
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507 ; |
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508 ; Leave with : |
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509 ; R0-R2 modified |
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510 ; Other registers unmodified |
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511 ;******************************************************************************* |
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512 InitDebugPort ROUT ; Based on the OMAP3530TRM 17.5.1.1 Quick Start |
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513 MOV r0, lr |
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514 BL GetDebugPortBase ; r1 = base address of debug port |
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515 MOV lr, r0 |
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516 |
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517 MOV r2, #KSoftResetMask |
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518 STR r2, [r1, #KHwUartSysC] ; Perform a soft reset of the UART |
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519 |
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520 MOV r2, #KConfigurationModeB |
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521 STR r2, [r1, #KHwUartLcr] ; UART to configuration mode B |
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522 |
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523 LDR r2, [r1, #KHwUartEfr] |
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524 ORR r2, #KEnhancedEnMask |
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525 STR r2, [r1, #KHwUartEfr] ; Enable the IER, FCR, MCR |
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526 |
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527 MOV r2, #KConfigurationModeA |
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528 STR r2, [r1, #KHwUartLcr] ; UART to configuration mode A |
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529 |
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530 LDR r2, [r1, #KHwUartMcr] |
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531 ORR r2, #KTcrTlr |
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532 STR r2, [r1, #KHwUartMcr] ; Enable the TCR, TLR |
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533 |
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534 MOV r2, #KFifoConfiguration |
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535 STR r2, [r1, #KHwUartFcr] ; FIFO |
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536 |
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537 MOV r2, #KConfigurationModeB |
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538 STR r2, [r1, #KHwUartLcr] ; UART to configuration mode B |
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539 |
|
540 LDR r2, [r1, #KHwUartEfr] |
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541 AND r2, #~KEnhancedEnMask |
|
542 STR r2, [r1, #KHwUartEfr] ; Disable the IER, FCR, MCR |
|
543 |
|
544 MOV r2, #KConfigurationModeA |
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545 STR r2, [r1, #KHwUartLcr] ; UART to configuration mode A |
|
546 |
|
547 LDR r2, [r1, #KHwUartMcr] |
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548 AND r2, #~KTcrTlr |
|
549 STR r2, [r1, #KHwUartMcr] ; Disable the TCR, TLR |
|
550 |
|
551 MOV r2, #KOperationMode |
|
552 STR r2, [r1, #KHwUartLcr] ; UART to operation mode |
|
553 |
|
554 ; 17.5.1.1.3 |
|
555 |
|
556 ; MDR1[2:0] is 0x7(Disable) from reset |
|
557 |
|
558 MOV r2, #KConfigurationModeB |
|
559 STR r2, [r1, #KHwUartLcr] ; UART to configuration mode B |
|
560 |
|
561 LDR r2, [r1, #KHwUartEfr] |
|
562 ORR r2, #KEnhancedEnMask |
|
563 STR r2, [r1, #KHwUartEfr] ; Enable the IER, FCR, MCR |
|
564 |
|
565 ; IER is clear from Reset |
|
566 |
|
567 MOV r2, #K115k2L |
|
568 STR r2, [r1, #KHwUartDll] ; Set baud rate |
|
569 ; DLH is 00 from Reset |
|
570 |
|
571 ; IER is clear from Reset |
|
572 |
|
573 MOV r2, #K8BitsNoParity1Stop |
|
574 STR r2, [r1, #KHwUartLcr] |
|
575 |
|
576 MOV r2, #KUART16XMode |
|
577 STR r2, [r1, #KHwUartMdr1] |
|
578 |
|
579 |
|
580 MOV r1, #0x19000 ; Set up delay loop to allow line to settle |
|
581 SUBS r1, r1, #1 |
|
582 SUBNE pc, pc, #12 |
|
583 |
|
584 MOV pc, lr |
|
585 |
|
586 ;******************************************************************************* |
|
587 ; Get the base address of the debug UART |
|
588 ; |
|
589 ; Enter with : |
|
590 ; R12 points to ROM header |
|
591 ; There may be no stack |
|
592 ; |
|
593 ; Leave with : |
|
594 ; R1 = base address of port |
|
595 ; No other registers modified |
|
596 ;******************************************************************************* |
|
597 GetDebugPortBase ROUT |
|
598 LDR r1, [r12, #TRomHeader_iDebugPort] |
|
599 CMP r1, #42 ; JTAG? |
|
600 MOVEQS r1, #0 |
|
601 MOVEQ pc, lr ; yes - return 0 and set Z |
|
602 |
|
603 CMP r1, #2 |
|
604 BNE %FA1 ; skip if not port 2 |
|
605 GET_ADDRESS r1, Serial2PhysBase, Serial2LinBase |
|
606 MOVS r1, r1 ; clear Z |
|
607 MOV pc, lr |
|
608 1 |
|
609 CMP r1, #1 |
|
610 BNE %FA1 ; skip if not port 1 |
|
611 GET_ADDRESS r1, Serial1PhysBase, Serial1LinBase |
|
612 MOVS r1, r1 ; clear Z |
|
613 MOV pc, lr |
|
614 1 |
|
615 GET_ADDRESS r1, Serial0PhysBase, Serial0LinBase |
|
616 MOVS r1, r1 ; clear Z |
|
617 MOV pc, lr |
|
618 |
|
619 ENDIF ; CFG_DebugBootRom |
|
620 |
|
621 |
|
622 |
|
623 |
|
624 |
|
625 ;******************************************************************************* |
|
626 ; BOOT FUNCTION TABLE |
|
627 ;******************************************************************************* |
|
628 |
|
629 BootTable |
|
630 DCD DoWriteC ; output a debug character |
|
631 DCD GetRamBanks ; get list of RAM banks |
|
632 DCD SetupRamBank ; set up a RAM bank |
|
633 DCD GetRomBanks ; get list of ROM banks |
|
634 DCD SetupRomBank ; set up a ROM bank |
|
635 DCD GetHwBanks ; get list of HW banks |
|
636 DCD ReservePhysicalMemory ; reserve physical RAM if required |
|
637 DCD GetParameters ; get platform dependent parameters |
|
638 DCD FinalInitialise ; Final initialisation before booting the kernel |
|
639 DCD HandleAllocRequest ; allocate memory |
|
640 DCD GetPdeValue ; usually in generic code |
|
641 DCD GetPteValue ; usually in generic code |
|
642 DCD PageTableUpdate ; usually in generic code |
|
643 DCD EnableMmu ; Enable the MMU (usually in generic code) |
|
644 |
|
645 ; These entries specify the standard MMU permissions for various areas |
|
646 ; They can be omitted if MMU is absent |
|
647 BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; ROM |
|
648 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; kernel data/stack/heap |
|
649 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; super page/CPU page |
|
650 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page directory/tables |
|
651 BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; exception vectors |
|
652 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; hardware registers |
|
653 DCD 0 ; unused (minicache flush) |
|
654 DCD 0 ; unused (maincache flush) |
|
655 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page table info |
|
656 BTP_ENTRY CLIENT_DOMAIN, PERM_RWRW, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; user RAM |
|
657 BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_STRONGLY_ORDERED, 1, 1, 0, 0 ; temporary identity mapping |
|
658 BTP_ENTRY CLIENT_DOMAIN, UNC_PERM, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; uncached |
|
659 |
|
660 END |