| author | Lukasz Forynski <lukasz.forynski@gmail.com> |
| Wed, 22 Sep 2010 23:33:25 +0100 | |
| branch | Beagle_BSP_dev |
| changeset 82 | 65b40f262685 |
| parent 77 | e5fd00cbb70a |
| child 83 | bcf33365fd8d |
--- a/omap3530/beagle_drivers/led/led.cpp Tue Sep 21 02:30:11 2010 +0100 +++ b/omap3530/beagle_drivers/led/led.cpp Wed Sep 22 23:33:25 2010 +0100 @@ -41,7 +41,7 @@ { GPIO::SetPinMode(KGPIO_LED0, GPIO::EEnabled); GPIO::SetOutputState(KGPIO_LED0, GPIO::ELow); - iTimer.OneShot(NKern::TimerTicks(KBeatTimeInSeconds * 1000)); + iTimer.OneShot(NKern::TimerTicks(KBeatTimeInSeconds * 1000)); } else {
--- a/omap3530/omap3530_drivers/spi/master.cpp Tue Sep 21 02:30:11 2010 +0100 +++ b/omap3530/omap3530_drivers/spi/master.cpp Wed Sep 22 23:33:25 2010 +0100 @@ -50,6 +50,7 @@ iIrqId = KMcSpiIrqId[iChannelNumber]; iHwBase = KMcSpiRegBase[iChannelNumber]; iState = EIdle; + iCurrSS = -1; DBGPRINT(Kern::Printf("DSpiMasterBeagle::DSpiMasterBeagle: at 0x%x, iChannelNumber = %d", this, iChannelNumber)); } @@ -184,7 +185,7 @@ iCurrHeader = newHeader; //copy the header.. return ETrue; } - return ETrue; + return EFalse; } // Init the hardware with the data provided in the transaction and slave-address field @@ -193,7 +194,7 @@ { DBGPRINT(Kern::Printf("ConfigureInterface()")); - // soft reset the SPI..(Channel 3 for now) + // soft reset the SPI.. TUint val = AsspRegister::Read32(iHwBase + MCSPI_SYSCONFIG); val = MCSPI_SYSCONFIG_SOFTRESET; // issue reset @@ -261,9 +262,20 @@ // CS (SS) pin direction.. val = MCSPI_SYST_SPIDATDIR0; - // drive csx pin hight or low - val |= (iCurrHeader.iSSPinActiveMode == ESpiCSPinActiveLow)? 1 << iCurrSS : 0; - AsspRegister::Write32(iHwBase + MCSPI_SYST, val); + // drive csx pin high or low +// val |= (iCurrHeader.iSSPinActiveMode == ESpiCSPinActiveLow)? 1 << iCurrSS : 0; +// AsspRegister::Modify32(iHwBase + MCSPI_SYST, val); + + if(iCurrHeader.iSSPinActiveMode == ESpiCSPinActiveLow) + { + AsspRegister::Modify32(iHwBase + MCSPI_SYST, 1u << iCurrSS, MCSPI_SYST_SPIDATDIR0); + } + else + { + AsspRegister::Modify32(iHwBase + MCSPI_SYST, 0, (1u << iCurrSS) | MCSPI_SYST_SPIDATDIR0); + } + + // Set the MS bit to 0 to provide the clock (ie. to setup as master) #ifndef SINGLE_MODE @@ -455,17 +467,17 @@ AsspRegister::Write32(iHwBase + MCSPI_CHxCTRL(iCurrSS), MCSPI_CHxCTRL_EN); AsspRegister::Modify32(iHwBase + MCSPI_IRQSTATUS, 0, - MCSPI_IRQ_TX_EMPTY(iCurrSS) /*| MCSPI_IRQ_TX_UNDERFLOW(iCurrSS)*/); + MCSPI_IRQ_TX_EMPTY(iCurrSS) /*| MCSPI_IRQ_TX_UNDERFLOW(iCurrSS)*/); AsspRegister::Modify32(iHwBase + MCSPI_IRQENABLE, 0, - MCSPI_IRQ_TX_EMPTY(iCurrSS) /*| MCSPI_IRQ_TX_UNDERFLOW(iCurrSS)*/); + MCSPI_IRQ_TX_EMPTY(iCurrSS) /*| MCSPI_IRQ_TX_UNDERFLOW(iCurrSS)*/); #ifdef SINGLE_MODE // in SINGLE mode needs to manually assert CS line for current AsspRegister::Modify32(iHwBase + MCSPI_CHxCONF(iCurrSS), 0, MCSPI_CHxCONF_FORCE); // change the pad config - now the SPI drives the line appropriately.. - SetCsActive(iChannelNumber, iCurrSS, iCurrHeader.iSSPinActiveMode); + SetCsActive(iChannelNumber, iCurrSS); #endif /*SINGLE_MODE*/ #ifdef USE_TX_FIFO @@ -526,7 +538,7 @@ AsspRegister::Modify32(iHwBase + MCSPI_CHxCONF(iCurrSS), 0, MCSPI_CHxCONF_FORCE); // change the pad config - now the SPI drives the line appropriately.. - SetCsActive(iChannelNumber, iCurrSS, iCurrHeader.iSSPinActiveMode); + SetCsActive(iChannelNumber, iCurrSS); #endif /*SINGLE_MODE*/ } else
--- a/omap3530/omap3530_drivers/spi/omap3530_spi.h Tue Sep 21 02:30:11 2010 +0100 +++ b/omap3530/omap3530_drivers/spi/omap3530_spi.h Wed Sep 22 23:33:25 2010 +0100 @@ -21,6 +21,7 @@ #define __OMAP3530_SPI_H__ #include <assp/omap3530_assp/omap3530_scm.h> +#include <assp/omap3530_assp/omap3530_gpio.h> #define BIT_MASK(shift,len) (((1u << (len)) - 1) << (shift)) @@ -325,26 +326,13 @@ //---------------------------------- // PAD (PIN) configuration for SPI //---------------------------------- - -//#define SPI_CHANNEL_3_PIN_OPTION_2 // TODO - move this to mmp file! -//#define SPI_CHANNEL_3_PIN_OPTION_3 - -// flags for CS signal pins - in order to keep them in certain state when SPI is inactive.. -const TUint KCsPinUp = SCM::EPullUdEnable | SCM::EPullTypeSelect; // -const TUint KCsPinDown = SCM::EPullUdEnable; // - -const TUint KCsPinOffHi = SCM::EOffOutEnable | SCM::EOffOutValue; // -const TUint KCsPinOffLow = SCM::EOffOutEnable; // - -const TUint KCsPinModeUp = /*KCsPinUp |*//* KCsPinOffHi |*/ SCM::EInputEnable; -const TUint KCsPinModeDown = KCsPinDown | KCsPinOffLow; - const TUint KMaxSpiChannelsPerModule = 4; // there are max 4 channels (McSPI 1) struct TPinConfig { TLinAddr iAddress; SCM::TLowerHigherWord iMswLsw; + TUint8 iPinNumber; TUint16 iFlags; }; @@ -358,82 +346,82 @@ const TSpiPinConfig TSpiPinConfigMcSpi1 = { - {CONTROL_PADCONF_MCSPI1_CLK, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi1_clk - {CONTROL_PADCONF_MCSPI1_CLK, SCM::EMsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi1_simo - {CONTROL_PADCONF_MCSPI1_SOMI, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi1_somi + {CONTROL_PADCONF_MCSPI1_CLK, SCM::ELsw, 171, SCM::EMode0 | SCM::EInputEnable}, // mcspi1_clk + {CONTROL_PADCONF_MCSPI1_CLK, SCM::EMsw, 172, SCM::EMode0 | SCM::EInputEnable}, // mcspi1_simo + {CONTROL_PADCONF_MCSPI1_SOMI, SCM::ELsw, 173, SCM::EMode0 | SCM::EInputEnable}, // mcspi1_somi { - {CONTROL_PADCONF_MCSPI1_SOMI, SCM::EMsw, SCM::EMode1}, // mcspi1_cs0 - {CONTROL_PADCONF_MCSPI1_CS1, SCM::ELsw, SCM::EMode1}, // mcspi1_cs1 - {CONTROL_PADCONF_MCSPI1_CS1, SCM::EMsw, SCM::EMode1}, // mcspi1_cs2 - {CONTROL_PADCONF_MCSPI1_CS3, SCM::ELsw, SCM::EMode1}, // mcspi1_cs3 + {CONTROL_PADCONF_MCSPI1_SOMI, SCM::EMsw, 174, SCM::EMode0}, // mcspi1_cs0 + {CONTROL_PADCONF_MCSPI1_CS1, SCM::ELsw, 175, SCM::EMode0}, // mcspi1_cs1 + {CONTROL_PADCONF_MCSPI1_CS1, SCM::EMsw, 176, SCM::EMode0}, // mcspi1_cs2 + {CONTROL_PADCONF_MCSPI1_CS3, SCM::ELsw, 177, SCM::EMode0}, // mcspi1_cs3 } }; const TSpiPinConfig TSpiPinConfigMcSpi2 = { - {CONTROL_PADCONF_MCSPI1_CS3, SCM::EMsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi2_clk - {CONTROL_PADCONF_MCSPI2_SIMO, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi2_simo - {CONTROL_PADCONF_MCSPI2_SIMO, SCM::EMsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi2_somi + {CONTROL_PADCONF_MCSPI1_CS3, SCM::EMsw, 178, SCM::EMode0 | SCM::EInputEnable}, // mcspi2_clk + {CONTROL_PADCONF_MCSPI2_SIMO, SCM::ELsw, 179, SCM::EMode0 | SCM::EInputEnable}, // mcspi2_simo + {CONTROL_PADCONF_MCSPI2_SIMO, SCM::EMsw, 180, SCM::EMode0 | SCM::EInputEnable}, // mcspi2_somi { - {CONTROL_PADCONF_MCSPI2_CS0, SCM::ELsw, SCM::EMode1}, // mcspi2_cs0 - {CONTROL_PADCONF_MCSPI2_CS0, SCM::EMsw, SCM::EMode1}, // mcspi2_cs1 - {0, SCM::ELsw, 0}, // not supported - {0, SCM::ELsw, 0}, // not supported + {CONTROL_PADCONF_MCSPI2_CS0, SCM::ELsw, 181, SCM::EMode0}, // mcspi2_cs0 + {CONTROL_PADCONF_MCSPI2_CS0, SCM::EMsw, 182, SCM::EMode0}, // mcspi2_cs1 + {0, SCM::ELsw, 0, 0}, // not supported + {0, SCM::ELsw, 0, 0}, // not supported } }; -#if defined(SPI_CHANNEL_3_PIN_OPTION_2) +#if defined(SPI_MODULE_3_PIN_OPTION_2) const TSpiPinConfig TSpiPinConfigMcSpi3 = { - {CONTROL_PADCONF_DSS_DATA18, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_clk - {CONTROL_PADCONF_DSS_DATA18, SCM::EMsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_simo - {CONTROL_PADCONF_DSS_DATA20, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_somi + {CONTROL_PADCONF_DSS_DATA18, SCM::ELsw, 88, SCM::EMode2 | SCM::EInputEnable}, // mcspi3_clk + {CONTROL_PADCONF_DSS_DATA18, SCM::EMsw, 89, SCM::EMode2 | SCM::EInputEnable}, // mcspi3_simo + {CONTROL_PADCONF_DSS_DATA20, SCM::ELsw, 90, SCM::EMode2 | SCM::EInputEnable}, // mcspi3_somi { - {CONTROL_PADCONF_DSS_DATA20, SCM::EMsw, SCM::EMode1}, // mcspi3_cs0 - {CONTROL_PADCONF_DSS_DATA20, SCM::ELsw, SCM::EMode1}, // mcspi3_cs1 - {0, SCM::ELsw, 0}, // not supported - {0, SCM::ELsw, 0}, // not supported + {CONTROL_PADCONF_DSS_DATA20, SCM::EMsw, 91, SCM::EMode2}, // mcspi3_cs0 + {CONTROL_PADCONF_DSS_DATA22, SCM::ELsw, 92, SCM::EMode2}, // mcspi3_cs1 + {0, SCM::ELsw, 0, 0}, // not supported + {0, SCM::ELsw, 0, 0}, // not supported } }; -#elif defined(SPI_CHANNEL_3_PIN_OPTION_3) +#elif defined(SPI_MODULE_3_PIN_OPTION_3) const TSpiPinConfig TSpiPinConfigMcSpi3 = { - {CONTROL_PADCONF_ETK_D2, SCM::EMsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_clk - {CONTROL_PADCONF_ETK_D0, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_simo - {CONTROL_PADCONF_ETK_D0, SCM::EMsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_somi + {CONTROL_PADCONF_ETK_D2, SCM::EMsw, 17, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_clk + {CONTROL_PADCONF_ETK_D0, SCM::ELsw, 14, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_simo + {CONTROL_PADCONF_ETK_D0, SCM::EMsw, 15, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_somi { - {CONTROL_PADCONF_ETK_D2, SCM::ELsw, SCM::EMode1}, // mcspi3_cs0 - {CONTROL_PADCONF_ETK_D6, SCM::EMsw, SCM::EMode1}, // mcspi3_cs1 - {0, SCM::ELsw, 0}, // not supported - {0, SCM::ELsw, 0}, // not supported + {CONTROL_PADCONF_ETK_D2, SCM::ELsw, 16, SCM::EMode1}, // mcspi3_cs0 + {CONTROL_PADCONF_ETK_D6, SCM::EMsw, 21, SCM::EMode1}, // mcspi3_cs1 + {0, SCM::ELsw, 0, 0}, // not supported + {0, SCM::ELsw, 0, 0}, // not supported } }; #else // default option (for beagle- these are pins on the extension header) const TSpiPinConfig TSpiPinConfigMcSpi3 = { - {CONTROL_PADCONF_MMC2_CLK, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_clk - {CONTROL_PADCONF_MMC2_CLK, SCM::EMsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_simo - {CONTROL_PADCONF_MMC2_DAT0, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_somi + {CONTROL_PADCONF_MMC2_CLK, SCM::ELsw, 130, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_clk + {CONTROL_PADCONF_MMC2_CLK, SCM::EMsw, 131, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_simo + {CONTROL_PADCONF_MMC2_DAT0, SCM::ELsw, 132, SCM::EMode1 | SCM::EInputEnable}, // mcspi3_somi { - {CONTROL_PADCONF_MMC2_DAT2, SCM::EMsw, SCM::EMode1}, // mcspi3_cs0 - {CONTROL_PADCONF_MMC2_DAT2, SCM::ELsw, SCM::EMode1}, // mcspi3_cs1 - {0, SCM::ELsw, 0}, // not supported - {0, SCM::ELsw, 0}, // not supported + {CONTROL_PADCONF_MMC2_DAT2, SCM::EMsw, 135, SCM::EMode1}, // mcspi3_cs0 + {CONTROL_PADCONF_MMC2_DAT2, SCM::ELsw, 134, SCM::EMode1}, // mcspi3_cs1 + {0, SCM::ELsw, 0, 0}, // not supported + {0, SCM::ELsw, 0, 0}, // not supported } }; #endif const TSpiPinConfig TSpiPinConfigMcSpi4 = { - {CONTROL_PADCONF_MCBSP1_CLKR, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi4_clk - {CONTROL_PADCONF_MCBSP1_DX, SCM::ELsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi4_simo - {CONTROL_PADCONF_MCBSP1_DX, SCM::EMsw, SCM::EMode1 | SCM::EInputEnable}, // mcspi4_somi + {CONTROL_PADCONF_MCBSP1_CLKR, SCM::ELsw, 156, SCM::EMode1 | SCM::EInputEnable}, // mcspi4_clk + {CONTROL_PADCONF_MCBSP1_DX, SCM::ELsw, 158, SCM::EMode1 | SCM::EInputEnable}, // mcspi4_simo + {CONTROL_PADCONF_MCBSP1_DX, SCM::EMsw, 159, SCM::EMode1 | SCM::EInputEnable}, // mcspi4_somi { - {CONTROL_PADCONF_MCBSP_CLKS, SCM::EMsw, SCM::EMode1}, // mcspi3_cs0 - {0, SCM::ELsw, 0}, // not supported - {0, SCM::ELsw, 0}, // not supported - {0, SCM::ELsw, 0}, // not supported + {CONTROL_PADCONF_MCBSP_CLKS, SCM::EMsw, 161, SCM::EMode1}, // mcspi3_cs0 + {0, SCM::ELsw, 0, 0}, // not supported + {0, SCM::ELsw, 0, 0}, // not supported + {0, SCM::ELsw, 0, 0}, // not supported } };
--- a/omap3530/omap3530_drivers/spi/omap3530_spi.inl Tue Sep 21 02:30:11 2010 +0100 +++ b/omap3530/omap3530_drivers/spi/omap3530_spi.inl Wed Sep 22 23:33:25 2010 +0100 @@ -18,28 +18,28 @@ // This sets the CS line to inactive mode (Specify aActiveMode as appropriate for configuration) -// The CS pin will be put back to the opposite mode - using GPIO.. +// The CS pin will be put back to the opposite mode - using GPIO.. THis is in order to always keep +// the CS line in an 'inactive' state (de-asserted) when the SPI is disabled. inline void SetCsInactive(TInt aModule, TInt aChannel, TSpiSsPinMode aActiveMode) { //__ASSERT_DEBUG(aModule < KMaxSpiChannelsPerModule, Kern::Fault("omap3530_spi.inl, line: ", __LINE__)); // aChannel > module channels // set the pin to the opposite to the currently active CS mode.. - TUint16 csPinOptions = aActiveMode == ESpiCSPinActiveLow ? KCsPinModeUp : KCsPinModeDown; const TPinConfig& csConf = ModulePinConfig[aModule].iCs[aChannel]; __ASSERT_DEBUG(csConf.iAddress, Kern::Fault("omap3530_spi.inl, line: ", __LINE__)); // aChannel > module channels - // now switch the pin mode.. - SCM::SetPadConfig(csConf.iAddress, csConf.iMswLsw, SCM::EMode4 | csPinOptions); // always go to mode 4 (gpio) + // now switch the pin mode..(making sure it is at the proper level before that) + GPIO::SetOutputState(csConf.iPinNumber, aActiveMode == ESpiCSPinActiveLow ? GPIO::EHigh : GPIO::ELow); + SCM::SetPadConfig(csConf.iAddress, csConf.iMswLsw, SCM::EMode4); // always go to mode 4 (gpio) } -void SetCsActive(TInt aModule, TInt aChannel, TSpiSsPinMode aActiveMode) +void SetCsActive(TInt aModule, TInt aChannel) { //__ASSERT_DEBUG(aModule < KMaxSpiChannelsPerModule, Kern::Fault("omap3530_spi.inl, line: ", __LINE__)); // aChannel > module channels - TUint16 csPinOptions = aActiveMode == ESpiCSPinActiveLow ? KCsPinModeUp : KCsPinModeDown; const TPinConfig &csConf = ModulePinConfig[aModule].iCs[aChannel]; __ASSERT_DEBUG(csConf.iAddress, Kern::Fault("omap3530_spi.inl, line: ", __LINE__)); // aChannel > module channels // now switch the pin mode back to the SPI - SCM::SetPadConfig(csConf.iAddress, csConf.iMswLsw, csConf.iFlags | csPinOptions); // revert to intended mode + SCM::SetPadConfig(csConf.iAddress, csConf.iMswLsw, csConf.iFlags | SCM::EInputEnable); // revert to intended mode } @@ -51,7 +51,20 @@ SCM::SetPadConfig(pinCnf.iClk.iAddress, pinCnf.iClk.iMswLsw, pinCnf.iClk.iFlags); SCM::SetPadConfig(pinCnf.iSimo.iAddress, pinCnf.iSimo.iMswLsw, pinCnf.iSimo.iFlags); SCM::SetPadConfig(pinCnf.iSomi.iAddress, pinCnf.iSomi.iMswLsw, pinCnf.iSomi.iFlags); - // Cs pins are set dynamically during operations. + + // Setup GPIO mode/direction for all CS pins only once - here. + for(TInt i = 0; i < KMaxSpiChannelsPerModule; i++) + { + if(pinCnf.iCs[i].iPinNumber) + { + GPIO::SetPinDirection(pinCnf.iCs[i].iPinNumber, GPIO::EOutput); + GPIO::SetPinMode(pinCnf.iCs[i].iPinNumber, GPIO::EEnabled); + } + else + { + break; + } + } } // helper function - returns appropriate value for the register for a given mode
--- a/omap3530/omap3530_drivers/spi/spi.mmp Tue Sep 21 02:30:11 2010 +0100 +++ b/omap3530/omap3530_drivers/spi/spi.mmp Wed Sep 22 23:33:25 2010 +0100 @@ -41,6 +41,13 @@ SOURCE slave.cpp #endif +// define one of the below values to switch PIN modes for McSPI3 to match your PCB connections. +// i.e. McSPI3 can be routed to 3 different pin sets using below defines - if both commented out +// the default routing is used, which takes McSPI3 out to the extension header (beagleboard). +// See omap3530_spi.h for more details. +//macro SPI_MODULE_3_PIN_OPTION_2 +//macro SPI_MODULE_3_PIN_OPTION_3 + // PIL source #include "../../../../../os/kernelhwsrv/kernel/eka/drivers/iic/iic_channel.mmh" @@ -51,6 +58,7 @@ TARGET AsspTarget(spi,dll) TARGETTYPE kext LINKAS spi.dll + //DEFFILE ./def/~/spi.def NOSTRICTDEF
--- a/omap3530/omap3530_drivers/spi/test/d_spi_client_m.cpp Tue Sep 21 02:30:11 2010 +0100 +++ b/omap3530/omap3530_drivers/spi/test/d_spi_client_m.cpp Wed Sep 22 23:33:25 2010 +0100 @@ -331,7 +331,7 @@ TPckgBuf<TConfigSpiV01> header(KHeader); // create transfer object - const TInt KBuffLength = 64; + const TInt KBuffLength = 10; // tTODO temp .. TBuf8<KBuffLength> txTransferBuf; // txbuffer.. // fill it with some data..(this will also set the length of the buffer) @@ -349,6 +349,10 @@ // queue the transaction synchronously r = IicBus::QueueTransaction(busId, &transaction); + // TODO - temporary added here.. + SET_SLAVE_ADDR(busId, 1); + r = IicBus::QueueTransaction(busId, &transaction); + LOG_FUNCTION_RETURN; return r; }
--- a/omap3530/omap3530_drivers/spi/test/t_spi_client_m.cpp Tue Sep 21 02:30:11 2010 +0100 +++ b/omap3530/omap3530_drivers/spi/test/t_spi_client_m.cpp Wed Sep 22 23:33:25 2010 +0100 @@ -72,6 +72,8 @@ test.Next(_L("TestSynchronousOperation()")); test.Next(_L("HalfDuplexSingleWrite()")); + + while(1) TestError(testLdd.HalfDuplexSingleWrite()); test.Next(_L("HalfDuplexMultipleWrite()"));