author | Ryan Harkin <ryan.harkin@nokia.com> |
Tue, 28 Sep 2010 18:00:05 +0100 | |
changeset 0 | 5de814552237 |
permissions | -rw-r--r-- |
0
5de814552237
Initial contribution supporting NaviEngine 1
Ryan Harkin <ryan.harkin@nokia.com>
parents:
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1 |
; |
5de814552237
Initial contribution supporting NaviEngine 1
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; Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
5de814552237
Initial contribution supporting NaviEngine 1
Ryan Harkin <ryan.harkin@nokia.com>
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; All rights reserved. |
5de814552237
Initial contribution supporting NaviEngine 1
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; This component and the accompanying materials are made available |
5de814552237
Initial contribution supporting NaviEngine 1
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; under the terms of "Eclipse Public License v1.0" |
5de814552237
Initial contribution supporting NaviEngine 1
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; which accompanies this distribution, and is available |
5de814552237
Initial contribution supporting NaviEngine 1
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; at the URL "http://www.eclipse.org/legal/epl-v10.html". |
5de814552237
Initial contribution supporting NaviEngine 1
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; |
5de814552237
Initial contribution supporting NaviEngine 1
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; Initial Contributors: |
5de814552237
Initial contribution supporting NaviEngine 1
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; Nokia Corporation - initial contribution. |
5de814552237
Initial contribution supporting NaviEngine 1
Ryan Harkin <ryan.harkin@nokia.com>
parents:
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; |
5de814552237
Initial contribution supporting NaviEngine 1
Ryan Harkin <ryan.harkin@nokia.com>
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; Contributors: |
5de814552237
Initial contribution supporting NaviEngine 1
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; |
5de814552237
Initial contribution supporting NaviEngine 1
Ryan Harkin <ryan.harkin@nokia.com>
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; Description: |
5de814552237
Initial contribution supporting NaviEngine 1
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; |
5de814552237
Initial contribution supporting NaviEngine 1
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|
5de814552237
Initial contribution supporting NaviEngine 1
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; |
5de814552237
Initial contribution supporting NaviEngine 1
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; NE1_TBVariant bootstrap configuration file |
5de814552237
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|
5de814552237
Initial contribution supporting NaviEngine 1
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; Include to enable tracing |
5de814552237
Initial contribution supporting NaviEngine 1
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; GBLL CFG_DebugBootRom |
5de814552237
Initial contribution supporting NaviEngine 1
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|
5de814552237
Initial contribution supporting NaviEngine 1
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; Include to initialise debug port in bootstrap without enabling bootstrap |
5de814552237
Initial contribution supporting NaviEngine 1
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; trace. Useful for __EARLY_DEBUG__ mode. |
5de814552237
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; GBLL CFG_InitDebugPort |
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|
5de814552237
Initial contribution supporting NaviEngine 1
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; Include one of these to select the CPU |
5de814552237
Initial contribution supporting NaviEngine 1
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GBLL CFG_CPU_ARM11MP |
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|
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; Include the following line if this is a bootloader bootstrap |
5de814552237
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; GBLL CFG_BootLoader |
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|
5de814552237
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; Use the alternate entrypoint into the bootstrap code |
5de814552237
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GBLL CFG_AlternateEntryPoint |
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|
5de814552237
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; Defining CFG_CopyRomToAddress will trigger the generic bootstrap code to copy the rom to the nominated location. |
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Initial contribution supporting NaviEngine 1
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INIT_NUMERIC_CONSTANT CFG_CopyRomToAddress, 0x86000000 |
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|
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; If you want to supply a custom set of initial vectors (including reset vector) include the following line |
5de814552237
Initial contribution supporting NaviEngine 1
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; GBLL CFG_CustomVectors |
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; |
5de814552237
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; and provide a custom_vectors.inc file |
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|
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; Variant Number |
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INIT_NUMERIC_CONSTANT CFG_HWVD, 0x09080001 |
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|
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; Include the following line if default memory mapping should use shared memory. |
5de814552237
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; Should be defined on multicore (SMP) devices. |
5de814552237
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GBLL CFG_USE_SHARED_MEMORY |
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|
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Initial contribution supporting NaviEngine 1
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; On ARM architecture 6 processors, include the following line to override the threshold |
5de814552237
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; on total physical RAM size at which the multiple memory model switches into large address space mode |
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; i.e. size>threshold -> 2Gb per process, size<=threshold -> 1Gb per process |
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; Defaults to 32Mb. |
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; INIT_NUMERIC_CONSTANT CFG_ARMV6_LARGE_CONFIG_THRESHOLD, <value> |
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|
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; For the direct memory model only, include the following line if you wish the exception vectors at the |
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; start of the bootstrap to be used at all times. This is only relevant if an MMU is present - this option |
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; is mandatory if not. |
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; GBLL CFG_UseBootstrapVectors |
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; |
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; If the above option is in use (including if no MMU is present) the following symbol should be defined |
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; to specify the offset from the bootstrap to the kernel image. |
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INIT_NUMERIC_CONSTANT KernelCodeOffset, 0x4000 |
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|
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; Include the following line if you wish to include the ROM autodetection code based on data bus |
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; capacitance and image repeats. |
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; GBLL CFG_AutoDetectROM |
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|
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; Include the following line to minimise the initial kernel heap size |
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; On the direct memory model the size of the kernel data area (super page to end of kernel heap) |
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; is rounded up to the next 1Mb if this is not included, 4K if it is. |
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; On the moving and multiple models, the size of the initial kernel heap area is rounded up to |
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; the next 64K if this is not included, 4K if it is. |
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; GBLL CFG_MinimiseKernelHeap |
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|
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; On the moving or multiple memory models, include either or both of the following lines to |
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; specify the size of the initial kernel heap |
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; INIT_NUMERIC_CONSTANT CFG_KernelHeapMultiplier, <multiplier> |
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; INIT_NUMERIC_CONSTANT CFG_KernelHeapBaseSize, <base> |
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; |
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; The initial kernel heap size is MAX( <base> + <multiplier> * N / 16, value specified in ROMBUILD ) |
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; where N is the total physical RAM size in pages. |
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; <base> defaults to 24K and <multiplier> defaults to 9*16 (ie 9 bytes per page). |
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|
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; Uncomment if using ARM1136 processor and ARM1136 Erratum 353494 |
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; "Rare conditions can cause corruption of the Instruction Cache" |
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; is fixed on this hardware. |
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; |
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; NOTE: The boot table should use this macro to determine whether RONO or RORO permissions |
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; are used for the exception vectors. If the erratum is not fixed, RORO must be used. |
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; |
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; GBLL CFG_CPU_ARM1136_ERRATUM_353494_FIXED |
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|
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; Uncomment if using ARM1136 processor and ARM1136 Erratum 364296 |
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; "Possible Cache Data Corruption with Hit-Under-Miss" |
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; is fixed on this hardware. |
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; |
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; GBLL CFG_CPU_ARM1136_ERRATUM_364296_FIXED |
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|
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; Uncomment if using ARM1136 processor and ARM1136 Erratum 399234 |
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; "Write back data cache entry evicted by write through entry causes data corruption" |
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; is fixed on this hardware. |
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; Workaround |
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; The erratum may be avoided by marking all cacheable memory as one of write through or write back. |
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; This requires the memory attributes described in the translation tables to be modified by software |
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; appropriately, or the use of the remapping capability to remap write through regions to non cacheable. |
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; |
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; If this macro is enabled, it should be accompanied by: |
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; "#define __CPU_ARM1136_ERRATUM_399234_FIXED" in variant.mmh |
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; GBLL CFG_CPU_ARM1136_ERRATUM_399234_FIXED |
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|
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|
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; Uncomment if: |
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115 |
; 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache |
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; operation might fail to invalidate some lines if coincident with linefill" |
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; is fixed on this hardware, or |
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118 |
; 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache |
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; operation might fail to invalidate some lines if coincident with linefill |
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; is fixed on this hardware. |
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; Workaround: |
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; 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. |
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; 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. |
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; If this macro is enabled, it should be accompanied by: |
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; "#define __CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh |
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126 |
; |
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; GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED |
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|
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|
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; Uncomment if using ARM1136 processor and ARM1136 Erratum 415662: "Invalidate Instruction Cache by |
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; Index might corrupt cache when used with background prefetch range" is fixed on this hardware. |
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132 |
; Workaround: |
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133 |
; Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. |
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134 |
; |
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; GBLL CFG_CPU_ARM1136_ERRATUM_415662_FIXED |
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136 |
|
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137 |
|
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; Uncomment if this variant config needs to support the Shadow Memory Regions |
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139 |
; (SMR) feature in the kernel. Basically allows media based images to be copied |
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; into memory which is later reserved by the Kernel RAM Allocator. |
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; One user of the SMR feature is the HCR component when used with media based |
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; setting repository. Thus variant configs that support the new MHA HCR |
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; component and expect media based settings must define this macro e.g. NAND |
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; Core Image ROM, but not BootLoader ROM etc. |
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145 |
; |
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; GBLL CFG_ENABLE_SMR_SUPPORT |
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|
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|
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; These are deduced from the supplied configuration |
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; CFG_ARMV6 |
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151 |
; CFG_MMUPresent |
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152 |
; CFG_CachePresent |
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; CFG_WriteBufferPresent |
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; CFG_SplitCache |
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; CFG_SplitTLB |
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; CFG_AltDCachePresent |
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; CFG_WriteBackCache |
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158 |
; CFG_CacheWriteAllocate |
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159 |
; CFG_CachePhysicalTag |
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; CFG_CacheFlushByDataRead |
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; CFG_CacheFlushByWaySetIndex |
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; CFG_CacheFlushByLineAlloc |
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; CFG_CachePolicyInPTE |
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164 |
; CFG_TEX |
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; CFG_SingleEntryDCacheFlush |
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; CFG_SingleEntryICacheFlush |
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; CFG_SingleEntryITLBFlush |
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; CFG_SingleEntryTLBFlush |
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; CFG_CacheTypeReg |
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; CFG_BTBPresent |
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; CFG_CARPresent |
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172 |
; CFG_PrefetchBuffer |
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; CFG_FCSE_Present |
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; CFG_ASID_Present |
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; CFG_IncludeRAMAllocator |
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|
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177 |
END |