/*

* Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).

* All rights reserved.

* This component and the accompanying materials are made available

* under the terms of "Eclipse Public License v1.0"

* which accompanies this distribution, and is available

* at the URL "http://www.eclipse.org/legal/epl-v10.html".

*

* Initial Contributors:

* Nokia Corporation - initial contribution.

*

* Contributors:

*

* Description: 

*

*/

#include <drivers/iic.h>

#include <drivers/iic_channel.h>

#include <assp/naviengine/naviengine_priv.h>

#include <drivers/gpio.h>

#include "csi_psl.h"

#include "csi_master.h"

#include "hcrconfig.h"

#include "hcrconfig_csi.h"

// This method ensures, that all Timers have been canceled..

// interrupts disabled prior to completing the request.

// This method is used to complete request and notify PIL in various situations.

void DCsiChannelMaster::ExitComplete(TInt aErr, TBool aComplete /*= ETrue*/)

	{

	__KTRACE_OPT(KIIC, Kern::Printf("ExitComplete, r %d, complete %d", aErr, aComplete));

	// make sure we've disabled ints and canceled dfcs/timers..

	// Disable interrupts for CSI

	Interrupt::Disable(iInterruptId);

	// cancel timers and DFCs..

	CancelTimeOut();

	iHwGuardTimer.Cancel();

	iTransferEndDfc.Cancel();

	// change state to EIdle..

	iState = EIdle;

	// complete the request..calling the PIL method

	if(aComplete)

		{

		CompleteRequest(aErr);

		}

	}

// this is call-back for iHwGuard timer. It is called in the ISR context

// if the iHwGuardTimer expires.

// It will change the iTransactionStatus to KErrTimedOut to allow exiting from the while-loop..

void DCsiChannelMaster::TimeoutCallback(TAny* aPtr)

	{

	__KTRACE_OPT(KIIC, Kern::Printf("DCsiChannelMaster::TimeoutCallback"));

	DCsiChannelMaster *a = (DCsiChannelMaster*) aPtr;

	a->iTransactionStatus = KErrTimedOut;

	}

// This method is called by the PIL in the case of timeout for the transaction expiration.

// The PIL will call CompleteRequest() after this function returns, so we need only to clean-up

// and de-assert the SS line.

TInt DCsiChannelMaster::HandleSlaveTimeout()

	{

	__KTRACE_OPT(KIIC, Kern::Printf("HandleSlaveTimeout"));

	// make sure, that CSIE bit is cleared (disable the interface)

	AsspRegister::Modify32(iChannelBase + KHoCSIModeControl, KHtCSIModeEnable, 0);

	// stop the driver's operation..

	ExitComplete(KErrTimedOut, EFalse);

	// bring the CS signal pin back to inactive state..

	GPIO::SetOutputState(iSSPin, iSSPinActiveStateOff);

	return KErrTimedOut;

	}

//DFC for TransferComplete

void DCsiChannelMaster::TransferEndDfc(TAny* aPtr)

	{

	__KTRACE_OPT(KIIC, Kern::Printf("DCsiChannelMaster::TransferEndDfc"));

	DCsiChannelMaster *a = (DCsiChannelMaster*) aPtr;

	// we are still receiving the data, so must wait until the end of the transmission

	// start the guard timer, which - in case of the following while got stucked - will

	// unblock this dfc by changing iTransactionStatus

	a->iTransactionStatus = KErrNone;

	a->iHwGuardTimer.OneShot(NKern::TimerTicks(a->iHwTimeoutValue));

	// active wait until the transfer has finished

	while((AsspRegister::Read32(a->iChannelBase + KHoCSIModeControl) & KHtCSIModeTransferState) &&

	      (a->iTransactionStatus == KErrNone));

	// bring the CS signal pin back to inactive state, but only if this is not an extended transaction,

	// in which case we want to leave the bus alone so that the multiple transactions making up the

	// extended transaction become one big transaction as far as the bus is concerned

	if (!(a->iCurrTransaction->Flags() & KTransactionWithMultiTransc))

		{

		GPIO::SetOutputState(a->iSSPin, a->iSSPinActiveStateOff);

		}

	// clear CSIE bit..

	AsspRegister::Modify32(a->iChannelBase + KHoCSIModeControl, KHtCSIModeEnable, 0);

	// check if the the guard timer or transaction timer hasn't expired..

	if(a->iTransactionStatus != KErrNone)

		{

		__KTRACE_OPT(KIIC, Kern::Printf("CsiChannelMaster::TransferEndDfc(): Transaction timed-out"));

		a->ExitComplete(a->iTransactionStatus); // report the error situation..

		return;

		}

	else

		{

		a->iHwGuardTimer.Cancel();

		}

	// drain the Rx FIFO buffer (there might be one item left)

	if(a->iOperation.iOp.iIsReceiving)

		{

		if(AsspRegister::Read32(a->iChannelBase + KHoCSIIFifoL) &&

		  (a->iRxDataEnd - a->iRxData >= a->iWordSize))

			{

			TUint16 val = AsspRegister::Read32(a->iChannelBase + KHoCSIIFifo);

			// we're big-endian.. (AB)..

			// so in 16bit mode we need to read MSB first..

			if(a->iWordSize > 1)

				{

				*a->iRxData = val >> 8; // MSB shifted down..

				*(a->iRxData + 1) = val & 0xff; // LSB..

				}

			else

				{

				*a->iRxData = val;

				}

			// increment the pointer..

			a->iRxData += a->iWordSize;

			}

		}

	// else - we don't care about the read data, it will be flushed before the next transfer..

	// check, if there are more transfers in this transaction

	if(a->iState == EBusy)

		{

		TInt err = a->ProcessNextTransfers();

		// if for any reason coudln't start next transfer-complete the transaction with err..

		if(err != KErrNone)

			{

			a->ExitComplete(err);

			}

		}

	}

// ISR Handler

void DCsiChannelMaster::CsiIsr(TAny* aPtr)

	{

	DCsiChannelMaster *a = (DCsiChannelMaster*) aPtr;

	// read the interrupt flags - to see, what was causing the interrupt..

	TUint32 status = AsspRegister::Read32(a->iChannelBase + KHoCSIIntStatus);

	// process TEND end interrupts

	// this ISR happens every time ONE unit has been transfered..

	if(status & KHtCSIIntStatusTEnd)

		{

		// clear TxEnd interrupt..

		AsspRegister::Write32(a->iChannelBase + KHoCSIIntStatus, KHtCSIIntStatusTEnd);

		if(a->iTxData == a->iTxDataEnd)

			{

			// if the Tx FIFO is empty (this was the last item transferred)

			// confirm that the transfer was completed successfully:

			// - set the transfer status as KErrNone

			// - disable interrupts..

			// - queue a DFC, which will finish the Tx-asserting/de-asserting CS line

			// and start another transfer in the transaction or complete transaction

			if(!AsspRegister::Read32(a->iChannelBase + KHoCSIOFifoL))

				{

				Interrupt::Disable(a->iInterruptId);

				a->iTransferEndDfc.Add();

				}

			}

		else

			{

			// if tere's more data to be sent - copy next item to the FIFO window register.

			// if we are in 'receive-only' mode - (e.g. simple read request) we're only

			// sending '0' (or other value defined as KValueSentOnRead) - to generate a clock for the slave.

			if(a->iOperation.iOp.iIsTransmitting)

				{

				// copy data to the FIFO..

				TUint16 val;

				// in 16bit mode we need to write two bytes as once MSB first..

				if(a->iWordSize > 1)

					{

					val = (*a->iTxData) << 8; // MSB shifted up..

					val |= *(a->iTxData + 1) & 0xff; // LSB..

					}

				else

					{

					val = *a->iTxData;

					}

				// write this value to the register..

				AsspRegister::Write32(a->iChannelBase + KHoCSIOFifo, val);

				// increment the pointer..

				a->iTxData += a->iWordSize;

				}

			}

		} //end of TXEnd processing

	// process receive threshold interrupt

	if(status & KHtCSIIntStatusRxTrgIE)

		{

		// read data from the FIFO ..

		if(a->iOperation.iOp.iIsReceiving)

			{

			while(AsspRegister::Read32(a->iChannelBase + KHoCSIIFifoL))

				{

				// if there's still some place in the buffer - put it into buffer..

				if((a->iRxDataEnd - a->iRxData) >= a->iWordSize)

					{

					// copy data from the FIFO if tere's more space in the buffer

					TUint16 val = AsspRegister::Read32(a->iChannelBase + KHoCSIIFifo);

					// we're big-endian.. (AB)..

					// so in 16bit mode we need to read MSB first..

					if(a->iWordSize > 1)

						{

						*a->iRxData = val >> 8; // MSB shifted down..

						*(a->iRxData + 1) = val & 0xff; // LSB..

						}

					else

						{

						*a->iRxData = val;

						}

					}

				else

					{

					// overrun, i.e Slave has sent more data than expected by the client

					// (e.g. too small buffer size for the transmission)

					a->iTransactionStatus = KErrOverflow;

					break;

					}

				// increment the pointer..

				a->iRxData += a->iWordSize;

				}

			}

		else

			{

			// or drop the data, writing 0 to the FIFOL register

			AsspRegister::Write32(a->iChannelBase + KHoCSIIFifoL, 0);

			}

		// if we are in the 'half-duplex' 'receive only' mode,

		// once the receive buffer is full we are to finish the transmission..

		if((a->iOperation.iValue == TCsiOperationType::EReceiveOnly) &&

		   (a->iRxDataEnd == a->iRxData))

			{

			Interrupt::Disable(a->iInterruptId);

			a->iTransferEndDfc.Add();

			}

		// Clear the  RxThreshold interrupt

		AsspRegister::Write32(a->iChannelBase + KHoCSIIntStatus, KHtCSIIntStatusRxTrgIE);

		} // end of reception processing..

	}

// constructor 1-st stage

DCsiChannelMaster::DCsiChannelMaster(TInt aChannelNumber, TBusType aBusType, TChannelDuplex aChanDuplex) :

	DIicBusChannelMaster(aBusType, aChanDuplex), // !!call overloaded base class constructor..

	iTransferEndDfc(TransferEndDfc, this, KCsiDfcPriority),

	iHwGuardTimer(TimeoutCallback, this)

	{

    iHwTimeoutValue = -1;

	iSSPin = 0;

	iChannelNumber = aChannelNumber; //Set the iChannelNumber of the Base Class

	iState = EIdle;

	__KTRACE_OPT(KIIC, Kern::Printf("DCsiChannelMaster::DCsiChannelMaster: iChannelNumber = %d", iChannelNumber));

	}

// 2nd stage construction..

TInt DCsiChannelMaster::DoCreate()

	{

	__KTRACE_OPT(KIIC, Kern::Printf("\nDCsiChannelMaster::DoCreate() ch: %d \n", iChannelNumber)); //__THREAD_AND_CPU;

	TInt32 interruptId;

	TUint32 channelBase;

	HCR::TSettingId settingId;

	settingId.iCat = KHcrCat_MHA_Interrupt;

	HCR::TSettingId channelBaseId;

	channelBaseId.iCat = KHcrCat_MHA_HWBASE;

	TInt r = KErrNone;

	switch(iChannelNumber)

		{

		case 0:

			settingId.iKey = KHcrKey_Interrupt_CSI0;

			channelBaseId.iKey = KHcrKey_HwBase_CSI0;

			break;

		case 1:

			settingId.iKey = KHcrKey_Interrupt_CSI1;

			channelBaseId.iKey = KHcrKey_HwBase_CSI1;

			break;

		default:

			__KTRACE_OPT(KIIC, Kern::Printf("Wrong ChannelNumber specified (%d)", iChannelNumber));

			return KErrArgument;

		}

	r = HCR::GetUInt(channelBaseId, channelBase);

	iChannelBase = channelBase;

	if(r != KErrNone)

		{

		__KTRACE_OPT(KIIC, Kern::Printf("Failed to read HCR setting for category = %d and key = %d\n", channelBaseId.iCat, channelBaseId.iKey));

		return r;

		}

	r = HCR::GetInt(settingId, interruptId);

	if(r != KErrNone)

		{

		__KTRACE_OPT(KIIC, Kern::Printf("Failed to read HCR setting for category = %d and key = %d\n", settingId.iCat, settingId.iKey));

		return r;

		}

	//Read the timeout value from HCR

	//The value will not be changed during transaction, so it needs to be read only once from HCR

	if(iHwTimeoutValue == -1) 

        {

        // csiTimeout values was not yet read from HCR; read it

        HCR::TSettingId settingId;

        settingId.iCat = KHcrCat_HWServ_CSI;

        settingId.iKey = KHcrKey_CSI_Timeout;

        r = HCR::GetInt(settingId, iHwTimeoutValue);

        if(r != KErrNone) 

            {

            __KTRACE_OPT(KIIC, Kern::Printf("Failed to read HCR setting for category = %d and key = %d\n", settingId.iCat, settingId.iKey));

            return r;

            }

        }

	// Create kernel DFCQ (thread) for the driver..

	if(!iDfcQ)

		{

		TBuf8<KMaxName> threadName (KSpiThreadName);

		threadName.AppendNum(iChannelNumber);

		TDynamicDfcQue* dynamicDfcQ;

		r = Kern::DynamicDfcQCreate(dynamicDfcQ, KSpiThreadPriority, threadName);

		if(r != KErrNone)

			{

			__KTRACE_OPT(KIIC, Kern::Printf("DFC Queue creation failed, ch: %d, r = %d\n", iChannelNumber, r));

			return r;

			}

		iDfcQ = dynamicDfcQ;

		}

	// PIL Base class initialization. This must!! be called prior to SetDfcQ(iDfcQ) ..

	r = Init();

	if(r == KErrNone)

		{

		// set iDFCQ

		SetDfcQ(iDfcQ); // base class..

		iTransferEndDfc.SetDfcQ(iDfcQ); // transfer-end DFC

#ifdef CPU_AFFINITY_ANY

		NKern::ThreadSetCpuAffinity((NThread*)(iDfcQ->iThread), KCpuAffinityAny);

#endif

		// Bind the Interrupt.

		iInterruptId = Interrupt::Bind(interruptId, CsiIsr, this);

		// this returns interruptId or error code(err < 0)

		if(iInterruptId < KErrNone)

			{

			__KTRACE_OPT(KIIC, Kern::Printf("ERROR: InterruptBind error.. %d", r));

			r = iInterruptId;

			iInterruptId = 0;

			}

		}

	return r;

	}

// static method used to construct the DCsiChannelMaster object.

// Export the channel creating function for client use in controller-less mode

#ifdef STANDALONE_CHANNEL

EXPORT_C

#endif

DCsiChannelMaster* DCsiChannelMaster::New(TInt aChannelNumber, const TBusType aBusType, const TChannelDuplex aChanDuplex)

	{

	__KTRACE_OPT(KIIC, Kern::Printf("DCsiChannelMaster::NewL(): aChannelNumber = %d, BusType =%d", aChannelNumber, aBusType));

	DCsiChannelMaster *pChan = new DCsiChannelMaster(aChannelNumber, aBusType, aChanDuplex);

	TInt r = KErrNoMemory;

	if(pChan)

		{

		r = pChan->DoCreate();

		}

	if(r != KErrNone)

		{

		delete pChan;

		pChan = NULL;

		}

	return pChan;

	}

#ifdef STANDALONE_CHANNEL

DCsiChannelMaster::~DCsiChannelMaster()

	{

	// This destructor will only be called in controller-less mode, when iDfcQ is a TDynamicDfcQ,

	// In here, detroy the dfc queue and unbind the interrupt for next channel creation 	

	// stop the Hardware

	// clear CISE bit..(disables CSI)

	AsspRegister::Modify32(iChannelBase + KHoCSIModeControl, KHtCSIModeEnable, 0);

	// set CSIRST bit..

	AsspRegister::Modify32(iChannelBase + KHoCSIControl, 0, KHtCSIControlCSIRst);

	if(iInterruptId)

	    {

	    Interrupt::Unbind(iInterruptId);

	    }

	if(iDfcQ)

		{

		((TDynamicDfcQue*)iDfcQ)->Destroy();

		}

	}

#endif

// this method compares if the previous transaction header and slave-select(chip-select) pin are different

// If configuration is the same - HW will not be re-initialized. It also makes a copy of the new header

// and new pin number used to configure the interface.

TBool DCsiChannelMaster::TransConfigDiffersFromPrev()

	{

	TConfigSpiBufV01* headerBuf = (TConfigSpiBufV01*) (GetTransactionHeader(iCurrTransaction));

	TConfigSpiV01 &spiHeader = (*headerBuf)();

	// the busId - has a SlaveAddress which in the case of SPI is a SlaveSelect pin (GPIO pin number)

	TUint32 busId = ((TIicBusTransaction*)iCurrTransaction)->GetBusId();

	// get the slave address

	TUint16 csPin;

	csPin = GET_SLAVE_ADDR(busId);

	// compare it to the previous configuration..

	if(csPin                            != iSSPin ||

	   spiHeader.iWordWidth             != iSpiHeader.iWordWidth ||

	   spiHeader.iClkSpeedHz            != iSpiHeader.iClkSpeedHz ||

	   spiHeader.iClkMode               != iSpiHeader.iClkMode ||

	   spiHeader.iTimeoutPeriod         != iSpiHeader.iTimeoutPeriod ||

	   spiHeader.iBitOrder              != iSpiHeader.iBitOrder ||

	   spiHeader.iTransactionWaitCycles != iSpiHeader.iTransactionWaitCycles ||

	   spiHeader.iSSPinActiveMode       != iSpiHeader.iSSPinActiveMode)

		{

		iSSPin = csPin; // copy CsPin number.

		iSpiHeader = spiHeader; // copy the new config params

#ifdef _DEBUG

		DumpConfiguration(spiHeader, iSSPin);

#endif

		return ETrue;

		}

	return EFalse;

	}

// Validates various fields in the transaction header

// this pure-virtual method is called by the PIL in the context of the

// client's thread - whenever he makes a call to QueueTransaction().

TInt DCsiChannelMaster::CheckHdr(TDes8* aHdrBuff)

	{

	TInt r = KErrNone;

	if(!aHdrBuff)

		{

		r = KErrArgument;

		}

	else

		{

		TConfigSpiBufV01* headerBuf = (TConfigSpiBufV01*) aHdrBuff;

		TConfigSpiV01 &spiHeader = (*headerBuf)();

		if(spiHeader.iTransactionWaitCycles > 15) // (can be 0 - 15)

			{

			__KTRACE_OPT(KIIC, Kern::Printf("iTransactionWaitCycles not supported"));

			r = KErrNotSupported;

			}

		else

			{

			if(spiHeader.iWordWidth != ESpiWordWidth_8 &&

			spiHeader.iWordWidth != ESpiWordWidth_16)

				{

				__KTRACE_OPT(KIIC, Kern::Printf("iWordWidth not supported"));

				r = KErrNotSupported;

				}

			else

				{

				if(spiHeader.iClkSpeedHz != 130000  &&

				   spiHeader.iClkSpeedHz != 260000  &&

                   spiHeader.iClkSpeedHz != 521000  &&

                   spiHeader.iClkSpeedHz != 1040000 &&

                   spiHeader.iClkSpeedHz != 2080000 &&

                   spiHeader.iClkSpeedHz != 4170000 &&

                   spiHeader.iClkSpeedHz != 16670000)

					{

					__KTRACE_OPT(KIIC, Kern::Printf("iClock not supported"));

					r = KErrNotSupported;

					}

				}

			}

		}