/*

* Copyright (c) 2008-2010 Nokia Corporation and/or its subsidiary(-ies).

* All rights reserved.

* This component and the accompanying materials are made available

* under the terms of "Eclipse Public License v1.0"

* which accompanies this distribution, and is available

* at the URL "http://www.eclipse.org/legal/epl-v10.html".

*

* Initial Contributors:

* Nokia Corporation - initial contribution.

*

* Contributors:

*

* Description: 

* naviengine_assp\dmapsl.cpp

* DMA Platform Specific Layer (PSL) for Navi Engine.

*

*/

#include <kernel/kern_priv.h>

#include <assp.h>

#include <naviengine_priv.h>

#include <navienginedma.h>

#include <dma.h>

#include <dma_hai.h>

// This macro was used to print debug info in the DMAC64 isr.

// It may be useful to reenable it as it appears to provoke an SMP

// race condition, which needs fixing

//#define _DEBUG_PRINT_ISR

// Debug support

static const char KDmaPanicCat[] = "DMA PSL";

static const TInt KDesCount = 1024;	// DMA descriptor count - sufficient to serve all channels at the time.

/* Maps logical DMA channels into physical ones */

static const TDMAChannelLocator KDMAChannelLocator[EDmaChannelCount]=

    {

  // controller, 	 group,	subchannel   DCHS (exc. SEL) TransferShiftSize

	{EDMACtrl32  	,2     ,2			,KHvDMACHC_SDR,		1}, //EDMAChannelSD0,

	{EDMACtrl32  	,2     ,3			,KHvDMACHC_SDW,		1},	//EDMAChannelSD1,

	{EDMACtrl32  	,3     ,0			,KHvDMACHC_I2SR,	1},	//EDMAChannelI2S0RX,

	{EDMACtrl32  	,3     ,1			,KHvDMACHC_I2SW,	1},	//EDMAChannelI2S0TX,

	{EDMACtrl32  	,3     ,2			,KHvDMACHC_I2SR,	1},	//EDMAChannelI2S1RX,

	{EDMACtrl32  	,3     ,3			,KHvDMACHC_I2SW,	1},	//EDMAChannelI2S1TX,

	{EDMACtrl32  	,3     ,4			,KHvDMACHC_I2SR,	1},	//EDMAChannelI2S2RX,

	{EDMACtrl32  	,3     ,5			,KHvDMACHC_I2SW,	1},	//EDMAChannelI2S2TX,

	{EDMACtrl32  	,3     ,6			,KHvDMACHC_I2SR,	1},	//EDMAChannelI2S3RX,

	{EDMACtrl32  	,3     ,7			,KHvDMACHC_I2SW,	1},	//EDMAChannelI2S3TX,

	{EDMACtrl32  	,0     ,2			,KHvDMACHC_SW,		2},	//EDMAChannelUART0RX,

	{EDMACtrl32  	,0     ,3			,KHvDMACHC_SW,		2},	//EDMAChannelUART0TX,

	{EDMACtrl32  	,0     ,4			,KHvDMACHC_SW,		2},	//EDMAChannelUART1RX,

	{EDMACtrl32  	,0     ,5			,KHvDMACHC_SW,		2},	//EDMAChannelUART1TX,

	{EDMACtrl32  	,0     ,6			,KHvDMACHC_SW,		2},	//EDMAChannelUART2RX,

	{EDMACtrl32  	,0     ,7			,KHvDMACHC_SW,		2},	//EDMAChannelUART2TX,

	{EDMACtrl32  	,0     ,0			,KHvDMACHC_SW,		2},	//EDmaMemToMem0,

	{EDMACtrl32		,0     ,1			,KHvDMACHC_SW,		2},	//EDmaMemToMem1,

	{EDMACtrl32		,2     ,4			,KHvDMACHC_SW,		2},	//EDmaMemToMem2,

	{EDMACtrl32		,2     ,5			,KHvDMACHC_SW,		2},	//EDmaMemToMem3,

	{EDmaCtrl64		,NULL  ,NULL		,NULL,		NULL},	//EDma64MemToMem0,

	{EDmaCtrl64		,NULL  ,NULL		,NULL,		NULL},	//EDma64MemToMem1,

	{EDmaCtrl64		,NULL  ,NULL		,NULL,		NULL},	//EDma64MemToMem2,

	{EDmaCtrl64		,NULL  ,NULL		,NULL,		NULL},	//EDma64MemToMem3,

    };

/* Maps physical EDMACtrl32 channels into logical ones */

static const int DMAC32_HWChannelsLocator[KDmaHWCtrl32Count][KDmaCtrl32HWSubChannelCount] = 

	{

	{EDmaMemToMem0,EDmaMemToMem1,EDMAChannelUART0RX,EDMAChannelUART0TX,

								EDMAChannelUART1RX,EDMAChannelUART1TX,EDMAChannelUART2RX,EDMAChannelUART2TX},

	{-1,-1,-1,-1,-1,-1,-1,-1},

	{-1,-1,EDMAChannelSD0,EDMAChannelSD1,EDmaMemToMem2,EDmaMemToMem3,-1,-1},

	{ EDMAChannelI2S0RX,EDMAChannelI2S0TX,EDMAChannelI2S1RX,EDMAChannelI2S1TX,

									EDMAChannelI2S2RX,EDMAChannelI2S2TX,EDMAChannelI2S3RX,EDMAChannelI2S3TX},

	{-1,-1,-1,-1,-1,-1,-1,-1},

	};

class TDmaDesc

//

// Hardware DMA descriptor

//

	{

public:

	TPhysAddr iSrcAddr;

	TPhysAddr iDestAddr;

	TUint iCount;	      // Transfer counter in bytes

	};

//

// Test Support

//

//The list of S/W channels to be tested by t_dma

TUint32 TestNEChannels[] = { EDmaMemToMem0, EDmaMemToMem1, EDmaMemToMem2, EDmaMemToMem3};

//Sg channels on the 64 bit controller

TUint32 TestNESgChannels[] = { EDma64MemToMem0, EDma64MemToMem1, EDma64MemToMem2, EDma64MemToMem3};

const TInt TestNESgChannelsSize = sizeof(TestNESgChannels)/sizeof(TestNESgChannels[0]);

/**

Information about the DMA drivers and available

channel cookies for the test harness

*/

TDmaTestInfo TestInfo =

	{

	4 * KMaxDMAUnitTransferLen, //a word is a unit of transfer for mem-to-mem DMA

	3,	// Word alignement applies fow S/W (mem-to-mem) transfer

	0,  // No need for cookie.

	4,	// The number of S/W DMA channels to test

	TestNEChannels,

	0,

	NULL,

	TestNESgChannelsSize,

	TestNESgChannels,

	};

EXPORT_C const TDmaTestInfo& DmaTestInfo()

	{

	return TestInfo;

	}

/**

Information about the DMA drivers and available

channel cookies for the test harness (V2)

*/

TDmaV2TestInfo TestInfov2 =

	{

	4 * KMaxDMAUnitTransferLen, //a word is a unit of transfer for mem-to-mem DMA

	3,	// Word alignement applies fow S/W (mem-to-mem) transfer

	0,  // No need for cookie.

	4,	// The number of S/W DMA channels to test

	{EDmaMemToMem0, EDmaMemToMem1, EDmaMemToMem2, EDmaMemToMem3},

	0,

	{NULL,},

	TestNESgChannelsSize,

	{EDma64MemToMem0, EDma64MemToMem1, EDma64MemToMem2, EDma64MemToMem3}

	};

EXPORT_C const TDmaV2TestInfo& DmaTestInfoV2()

	{

	return TestInfov2;

	}

//

// Helper Functions

//

inline TBool IsHwDesAligned(const TAny* aDes)

//

// We do no need H/W descriptors to be aligned as Navi Engine DMA32 cotroller doesn't

// support linked descriptors. Instead, they are linked by S/W. Therefore, the ordinary

// word alignement applies (which is enforced by compiler).

//

	{

	return ((TLinAddr)aDes & 0x3) == 0;

	}

// Channel class.

// For double buffering, TDmaDbChannel::DoQueue must be overridden.

// NE DMA has two sets of registers (base & work) - which is not supported by the original

#if defined(NE1_DMA_DOUBLE_BUFFER)

class TNE1DmaChannel : public TDmaDbChannel

#else

class TNE1DmaChannel : public TDmaSbChannel

#endif

	{

public:

	TNE1DmaChannel();

	void ProcessIrq();

	void ProcessErrorIrq();

	void StopTransfer();

	void Close();

	inline TBool IsIdle() const;

private:

#if defined(NE1_DMA_DOUBLE_BUFFER)

	virtual void DoQueue(const DDmaRequest& aReq);

#endif

	virtual void QueuedRequestCountChanged();

	inline void ProcessTC(TBool aClearStatus);

	inline void ProcessEnd(TBool aClearStatus);

	inline void ClearStatus(TUint32 aBitmask);

	inline void HandleIsr(TBool aIsComplete);

public:

	TInt iHWCtrlBase;// Base address of H/W registers for this channel.

	TInt iSubChannel;// Subchannel number (0-7) within H/W controller.

	TInt iDMACHCReg; // The content of configuration (CHC) register for this channel.

	TInt iTransferDataShift;//log2 of basic unit of transfer. See TDMAChannelLocator::iTransferShiftSize

	// The following members are public so that they can be

	// modified by the TNaviEngineDmac class

	/**

	This flag is set when the base register set is filled

	It allows the ISR to detect the case where a base to work

	register set changeover has happened (END interrupt) but has been masked by

	the completion of the work register set

	*/

	TBool iBaseValidSet;

	/**

	This counter is incremented each time a LaunchTransfer is started

	and decremented when the ISR handles the transfer complete (TC

	bit). Ie. it does not keep count of the number of times the base

	register set is filled. This allows missed TC interrupts to be

	detected.

	*/

	TInt iTcIrqCount;

	/**

	This spinlock is used to protect both the iBaseValidSet and iTcIrqCount

	variables. It synchronises access between threads and the ISR.

	For the ISR the setting of iBaseValidSet must appear to be atomic with

	the launch of the transfer.

	For iTcIrqCount The spinlock makes the transfer launch and subsequent

	increase of the count appear atomic to the ISR. Otherwise it could

	observe a completed transfer before the count was incremented or

	vice-versa

	*/

	TSpinLock iIsrLock;

	};

//

// Derived Controller Class

//

using namespace Dma64;

class TNaviEngineDmac : public TDmac

	{

public:

	TNaviEngineDmac();

	TInt Create();

	friend void TNE1DmaChannel::HandleIsr(TBool); // Allow channel HandleIsr to call TDmac::HandleIsr

private:

	// from TDmac (PIL pure virtual)

	virtual void StopTransfer(const TDmaChannel& aChannel);

	virtual TBool IsIdle(const TDmaChannel& aChannel);

	virtual TUint MaxTransferLength(TDmaChannel& aChannel, TUint aSrcFlags, TUint aDstFlags, TUint32 aPslInfo);

	virtual TUint AddressAlignMask(TDmaChannel& aChannel, TUint aSrcFlags, TUint aDstFlags, TUint32 aPslInfo);

	// from TDmac (PIL virtual)

	virtual void Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr);

	virtual TInt InitHwDes(const SDmaDesHdr& aHdr, const TDmaTransferArgs& aTransferArgs);

	virtual TInt UpdateHwDes(const SDmaDesHdr& aHdr, TUint32 aSrcAddr, TUint32 aDstAddr,

							 TUint aTransferCount, TUint32 aPslRequestInfo);

	virtual void ChainHwDes(const SDmaDesHdr& aHdr, const SDmaDesHdr& aNextHdr);

	virtual void AppendHwDes(const TDmaChannel& aChannel, const SDmaDesHdr& aLastHdr,

							 const SDmaDesHdr& aNewHdr);

	virtual void UnlinkHwDes(const TDmaChannel& aChannel, SDmaDesHdr& aHdr);

	// other

	static void DMAC32_Isr(TAny* aThis, TInt aController, TInt aTcsMask, TInt aCompleted);

	static void DMAC32_0_End_Isr(TAny* aThis);

	static void DMAC32_0_Err_Isr(TAny* aThis);

	static void DMAC32_2_End_Isr(TAny* aThis);

	static void DMAC32_2_Err_Isr(TAny* aThis);

	static void DMAC32_3_End_Isr(TAny* aThis);

	static void DMAC32_3_Err_Isr(TAny* aThis);

	static void InitHWChannel (ENaviEngineDmaController aNEController, TInt aGroup, TInt aSubChannel);

	static void InitAllHWChannels ();

	inline TDmaDesc* HdrToHwDes(const SDmaDesHdr& aHdr);

private:

	static const SCreateInfo KInfo;

public:

	void PopulateWorkSet(TNE1DmaChannel& aChannel, const SDmaDesHdr& aHdr);

	void LaunchTransfer(TNE1DmaChannel& aChannel, TBool aBaseSetValid);

#if defined(NE1_DMA_DOUBLE_BUFFER)

	void PopulateBaseSet(TNE1DmaChannel& aChannel, const SDmaDesHdr& aHdr);

	void ContinueTransfer(TNE1DmaChannel& aChannel, TBool aBaseSetValid);

#endif

	TNE1DmaChannel iChannels[EDmaChannelCount];

	static const SDmacCaps KCaps;

	};

static TNaviEngineDmac Controller;

// The following values report to the PIL what the PSL has been implemented

// to support, not necessarily what the hardware actually supports.

const SDmacCaps TNaviEngineDmac::KCaps =

	{0,										// TInt iChannelPriorities;

	 EFalse,								// TBool iChannelPauseAndResume;

	 ETrue,									// TBool iAddrAlignedToElementSize;

	 EFalse,								// TBool i1DIndexAddressing;

	 EFalse,								// TBool i2DIndexAddressing;

	 KDmaSyncAuto,						   // TUint iSynchronizationTypes;

	 KDmaBurstSizeAny,					   // TUint iBurstTransactions;

	 EFalse,							   // TBool iDescriptorInterrupt;

	 EFalse,							   // TBool iFrameInterrupt;

	 EFalse,							   // TBool iLinkedListPausedInterrupt;

	 EFalse,							   // TBool iEndiannessConversion;

	 KDmaGraphicsOpNone,				   // TUint iGraphicsOps;

	 EFalse,							   // TBool iRepeatingTransfers;

	 EFalse,							   // TBool iChannelLinking;

	 ETrue,								   // TBool iHwDescriptors; // DMAC does not really use Hw descriptors

	 EFalse,							   // TBool iSrcDstAsymmetry;

	 EFalse,							   // TBool iAsymHwDescriptors;

	 EFalse,							   // TBool iBalancedAsymSegments;

	 EFalse,							   // TBool iAsymCompletionInterrupt;

	 EFalse,							   // TBool iAsymDescriptorInterrupt;

	 EFalse,							   // TBool iAsymFrameInterrupt;

	 {0, 0, 0, 0, 0}					   // TUint32 iReserved[5];

	};

const TDmac::SCreateInfo TNaviEngineDmac::KInfo =

	{

	ETrue,													// iCapsHwDes

	KDesCount,												// iDesCount

	sizeof(TDmaDesc),										// iDesSize

	EMapAttrSupRw | EMapAttrFullyBlocking					// iDesChunkAttribs

	};

//////////////////////////////////////////////////////////////////////////////

// AXI 64bit DMAC - (Scatter Gather

//////////////////////////////////////////////////////////////////////////////

class TNaviEngineDmac64Sg;

class TNeSgChannel : public TDmaSgChannel

	{

	friend class TNaviEngineDmac64Sg;

public:

	TNeSgChannel();

	TNeSgChannel(TInt aPslId);

	inline TUint BaseAddr() {return iBaseAddr;}

#ifdef _DEBUG_PRINT_ISR

	void Print();

#endif

	inline void Pause()

		{

		using namespace Channel;

		AsspRegister::Modify32(iBaseAddr + Ctrl::KHoBase, NULL, Ctrl::KHtSetSuspend);

		}

	inline void Resume()

		{

		using namespace Channel;

		AsspRegister::Modify32(iBaseAddr + Ctrl::KHoBase, NULL, Ctrl::KHtClrSuspend);

		}

	inline void MaskInterrupt()

		{

		using namespace Channel;

		AsspRegister::Modify32(iBaseAddr + Cfg::KHoBase, NULL, Cfg::KHtEndMask|Cfg::KHtCompMask);

		}

	inline TUint32 CurrSrcAddr() const

		{

		using namespace Channel;

		return AsspRegister::Read32(iBaseAddr + RegSet::KHoBases[RegSet::ECurrent] + RegSet::KHoSrcAddr);

		}

	inline TUint32 CurrDstAddr() const

		{

		using namespace Channel;

		return AsspRegister::Read32(iBaseAddr + RegSet::KHoBases[RegSet::ECurrent] + RegSet::KHoDstAddr);

		}

	inline TUint32 CurrByteCount() const

		{

		using namespace Channel;

		return AsspRegister::Read32(iBaseAddr + RegSet::KHoBases[RegSet::ECurrent] + RegSet::KHoTranByte);

		}

	inline TUint32 Status() const

		{

		return AsspRegister::Read32(iBaseAddr + Channel::Status::KHoBase);

		}

	inline TUint32 Config() const

		{

		return AsspRegister::Read32(iBaseAddr + Channel::Cfg::KHoBase);

		}

	inline TUint32 NextLink() const

		{

		return AsspRegister::Read32(iBaseAddr + Channel::KHoNxtLnkAddr);

		}

	inline TUint32 CurrLink() const

		{

		return AsspRegister::Read32(iBaseAddr + Channel::KHoCurrtLnkAddr);

		}

	virtual void QueuedRequestCountChanged();

	inline TBool IsIdle() const

		{

		const TUint channelStatus = Status();

		using namespace Channel::Status;

		const TBool isIdle = (channelStatus & (KHtEnabled | KHtDescLoad)) == 0;

		return isIdle;

		}

	void Transfer(TDma64Desc* aHwDes);

	void Close();

private:

	TUint32 iBaseAddr;

	TInt iTransferCount;

	TSpinLock iLock;

	};

/**

Represents the 64 bit controller on the AXI bus - in scatter gather

mode. The controller supports both scatter gather and double buffered

mode but the framework dicatates that separate logical DMACs are

required for each mode of operation.

*/

class TNaviEngineDmac64Sg : public TDmac

	{

public:

	TNaviEngineDmac64Sg();

	TInt Create();

private:

	// from TDmac (PIL pure virtual)

	virtual void StopTransfer(const TDmaChannel& aChannel);

	virtual TBool IsIdle(const TDmaChannel& aChannel);

	virtual TUint MaxTransferLength(TDmaChannel& aChannel, TUint aSrcFlags, TUint aDstFlags, TUint32 aPslInfo);

	virtual TUint AddressAlignMask(TDmaChannel& aChannel, TUint aSrcFlags, TUint aDstFlags, TUint32 aPslInfo);

	// from TDmac (PIL virtual)

	virtual void Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr);

	virtual TInt InitHwDes(const SDmaDesHdr& aHdr, const TDmaTransferArgs& aTransferArgs);

	virtual TInt UpdateHwDes(const SDmaDesHdr& aHdr, TUint32 aSrcAddr, TUint32 aDstAddr,

							 TUint aTransferCount, TUint32 aPslRequestInfo);

	virtual void ChainHwDes(const SDmaDesHdr& aHdr, const SDmaDesHdr& aNextHdr);

	virtual void AppendHwDes(const TDmaChannel& aChannel, const SDmaDesHdr& aLastHdr,

							 const SDmaDesHdr& aNewHdr);

	virtual void UnlinkHwDes(const TDmaChannel& aChannel, SDmaDesHdr& aHdr);

	// other

	static void IsrEnd(TAny* aThis);

	static void IsrErr(TAny* aThis);

	inline TDma64Desc* HdrToHwDes(const SDmaDesHdr& aHdr);

	static void JoinHwDes(TDma64Desc& aHwDes, const TDma64Desc& aNextHwDes);

private:

	static const SCreateInfo KInfo;

public:

	TNeSgChannel iChannels[Dma64::KChannelCount];

	static const SDmacCaps KCaps;

	};

static TNaviEngineDmac64Sg Controller64;

// The following values report to the PIL what the PSL has been implemented

// to support, not necessarily what the hardware actually supports.

const SDmacCaps TNaviEngineDmac64Sg::KCaps =

	{0,										// TInt iChannelPriorities;

	 EFalse,								// TBool iChannelPauseAndResume;

	 EFalse,								// TBool iAddrAlignedToElementSize;

	 EFalse,								// TBool i1DIndexAddressing;

	 EFalse,								// TBool i2DIndexAddressing;

	 KDmaSyncAuto,						   // TUint iSynchronizationTypes;

	 KDmaBurstSizeAny,					   // TUint iBurstTransactions;

	 EFalse,							   // TBool iDescriptorInterrupt;

	 EFalse,							   // TBool iFrameInterrupt;

	 EFalse,							   // TBool iLinkedListPausedInterrupt;

	 EFalse,							   // TBool iEndiannessConversion;

	 KDmaGraphicsOpNone,				   // TUint iGraphicsOps;

	 EFalse,							   // TBool iRepeatingTransfers;

	 EFalse,							   // TBool iChannelLinking;

	 ETrue,								   // TBool iHwDescriptors;

	 EFalse,							   // TBool iSrcDstAsymmetry;

	 EFalse,							   // TBool iAsymHwDescriptors;

	 EFalse,							   // TBool iBalancedAsymSegments;

	 EFalse,							   // TBool iAsymCompletionInterrupt;

	 EFalse,							   // TBool iAsymDescriptorInterrupt;

	 EFalse,							   // TBool iAsymFrameInterrupt;

	 {0, 0, 0, 0, 0}					   // TUint32 iReserved[5];

	};

const TDmac::SCreateInfo TNaviEngineDmac64Sg::KInfo =

	{

	ETrue,													// iCapsHwDes

	KDesCount,												// iDesCount

	sizeof(TDma64Desc),										// iDesSize

	EMapAttrSupRw | EMapAttrFullyBlocking					// iDesChunkAttribs

	};

TNaviEngineDmac::TNaviEngineDmac()

//

// Constructor.

//

	: TDmac(KInfo)

	{

	}

TInt TNaviEngineDmac::Create()

//

// Second phase construction.

//

	{

	TInt r = TDmac::Create(KInfo);							// Base class Create()

	if (r == KErrNone)

		{

		// Read KDMAChannelLocator constants and populate the values in channel objects.

		for (TInt i=0; i < EDma32ChannelCount; ++i)

			{

			TUint ctrlBase = 0;

			switch (KDMAChannelLocator[i].iDMACtrl)

				{

				case EDmaCtrlExBus: ctrlBase = KDMACExBusBase; break;

				case EDMACtrl32:	ctrlBase = KDMAC32Base;	   break;

				default:			__DMA_CANT_HAPPEN();