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1 ; |
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2 ; Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 ; All rights reserved. |
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4 ; This component and the accompanying materials are made available |
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5 ; under the terms of "Eclipse Public License v1.0" |
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6 ; which accompanies this distribution, and is available |
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7 ; at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 ; |
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9 ; Initial Contributors: |
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10 ; Nokia Corporation - initial contribution. |
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11 ; |
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12 ; Contributors: |
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13 ; |
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14 ; Description: |
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15 ; \ne1_tb\bootstrap\miniboot.s |
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16 ; Code to retrieve the core loader image from the NAND flash and |
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17 ; run it. Expects that the system is in a state where NAND can be |
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18 ; read and SDRAM can be written. |
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19 ; See variant_bootstrap.inc for the variant specfic constants |
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20 ; Where in RAM should the core loader be copied to (LINKBASE of coreldr) |
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21 ; There is a companion to this value in the coreloader makefile, they must |
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22 ; match! |
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23 ; |
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24 |
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25 INCLUDE e32rom.inc |
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26 INCLUDE naviengine.inc |
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27 |
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28 KMinibootStackAddr EQU 0x820003FC |
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29 KRAMBase EQU 0x80000000 ; base of ram |
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30 |
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31 KNandPageSize EQU 2048 |
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32 KPageByteShift EQU 11 |
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33 |
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34 ;Command Set Reg Bits |
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35 KNandBusyBit EQU 0x0100 |
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36 KNandPageReadBM EQU 0x0101 |
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37 KNandResetBM EQU 0x0106 |
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38 |
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39 ;ECC Reg Bits |
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40 KNandECCDRC EQU 0x0080 |
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41 |
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42 ; NAND Register Addresses |
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43 KNandDataWndw EQU 0x18019000; |
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44 KNandPgeAdr1Reg EQU 0x18019840; |
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45 KNandPgeAdr2Reg EQU 0x18019842; |
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46 KNandPgeAdrMskReg0 EQU 0x18019844; |
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47 KNandPgeAdrMskReg1 EQU 0x18019846; |
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48 KNandPgeAdrMskReg2 EQU 0x18019848; |
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49 KNandPgeAdrMskReg3 EQU 0x1801984A; |
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50 KNandCmdSetReg EQU 0x1801984E; |
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51 KNandDataAreaECCReg EQU 0x18019850; |
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52 KNandROMTypeSetup1 EQU 0x18019852; |
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53 KNandROMTypeSetup2 EQU 0x18019854; |
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54 KNandChipSelect EQU 0x18019856; |
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55 |
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56 |
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57 ; Which page in NAND holds the Coreldr image |
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58 KSymbianCoreldrPage EQU 1 ; |
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59 KSymbianCoreldrSizePages EQU 64 ; 64 * 2048B = 128KB |
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60 |
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61 ; Export the miniboot's only entry point |
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62 EXPORT GetCoreldr |
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63 |
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64 ; |
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65 ; Area definition for ARMLD linker |
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66 ; |
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67 AREA |Boot$$Code|, CODE, READONLY, ALIGN=6 |
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68 |
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69 ;****************************************************************************** |
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70 ; Boot Entry point for bootloader's miniboot code |
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71 ; |
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72 ; Always runs |
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73 ; after the bootloader has initialised the memory subsystem |
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74 ; with the SRAM/SDRAM devices available. (RAM >0x8000.0000) |
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75 ; |
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76 ; Tasks |
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77 ; Confirm NAND device is as expected |
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78 ; read TOC structure at the start of the NAND (in page 0) |
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79 ; search TOC array for coreloader image entry |
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80 ; load coreloader sized image from NAND offset (from TOC) |
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81 ; jump to coreloader entry point |
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82 ; |
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83 ;****************************************************************************** |
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84 |
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85 GetCoreldr |
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86 ; create a stack so that we can use ordinary function calls |
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87 ldr r13, =KMinibootStackAddr |
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88 |
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89 ; RESET_NAND |
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90 LDR r0, =KNandResetBM ; CMD_RESET | XROMC_BUSY_BIT_MASK |
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91 LDR r4, =KNandCmdSetReg ; XROMC |
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92 STRH r0, [r4] |
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93 |
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94 ; POLLED_WAIT_FOR_RDY |
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95 1 |
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96 LDR r4, =KNandCmdSetReg |
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97 LDRH r0, [r4] ; Get contents of Command setup register |
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98 TST r0, #KNandBusyBit |
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99 BNE %B1 |
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100 |
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101 ; Start from a clean, ready system state |
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102 ; INIT_PNL_DEVICE |
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103 LDR r0, =0xF000 ;Unmask address for XROMM0-3 |
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104 LDR r4, =KNandPgeAdrMskReg0 |
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105 STRH r0, [r4] |
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106 |
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107 LDR r4, =KNandPgeAdrMskReg1 |
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108 STRH r0, [r4] |
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109 |
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110 LDR r4, =KNandPgeAdrMskReg2 |
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111 STRH r0, [r4] |
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112 |
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113 LDR r4, =KNandPgeAdrMskReg3 |
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114 STRH r0, [r4] |
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115 |
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116 ;Configure the NAND Type |
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117 ;CS1 NAND Config: 8bit, 2K |
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118 ;CS2 NAND Config: 8bit, 2K |
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119 LDR r0, =0x0101 |
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120 LDR r4, =KNandROMTypeSetup1 |
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121 STRH r0, [r4] |
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122 ;CS3 NAND Config: 8bit, 2K |
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123 LDR r0, =0x01 |
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124 LDR r4, =KNandROMTypeSetup2 |
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125 STRH r0, [r4] |
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126 |
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127 ; Select chipset 0 to be used (navi supports upto 4 NAND chips) |
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128 LDR r0, =0x0000 ;Select ChipSet 0 |
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129 LDR r4, =KNandChipSelect |
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130 STRH r0, [r4] |
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131 |
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132 LDR r4,=KNandDataAreaECCReg |
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133 LDRH r0, [r4] ; get contents of register |
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134 BIC r0, r0, #0x1 |
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135 STRH r0, [r4] |
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136 |
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137 |
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138 ; Normally Read the device ID and confirm nand device is as expected |
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139 ; NAND Controller on NaviEngine doesn't allow the Device id to be read |
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140 |
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141 bl readhdr16 ; read header of 16bit device |
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142 ; Readhdr16 -> parse_header -> find/load Symbian coreldr -> run coreldr |
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143 |
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144 |
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145 ;------------------------------------------------------------------------ |
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146 ; |
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147 ; strcmp - bytewise compare of two strings |
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148 ; r0->string A |
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149 ; r1->string B |
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150 ; r3->size of string A |
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151 ; |
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152 ; if string A == string B return 0 in r0 |
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153 ; else returns non zero in r0 |
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154 ; |
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155 ;------------------------------------------------------------------------ |
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156 strcmp ROUT |
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157 stmfd r13!, {r4-r6,lr} |
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158 |
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159 mov r4, r0 |
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160 mov r5, r1 |
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161 mov r6, r3 |
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162 |
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163 strloop |
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164 ldrb r2, [r4], #1 |
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165 ldrb r3, [r5], #1 |
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166 |
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167 subs r0, r2, r3 |
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168 cmp r2, #0 |
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169 beq strreturn |
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170 subs r6, r6, #1 |
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171 bne strloop |
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172 strreturn |
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173 ldmfd r13!, {r4-r6,pc} |
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174 |
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175 |
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176 ;--------------------------------------------------------------------------------- |
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177 ; readpage16 |
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178 ; |
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179 ; read 1 page (2048KB) of NAND device, |
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180 ; starting at page (r0) |
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181 ; put data into address (r1) |
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182 ; |
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183 ;--------------------------------------------------------------------------------- |
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184 readpage16 ROUT |
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185 stmfd r13!, {r4-r7,lr} |
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186 |
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187 ; set the page start addresss [r0] |
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188 ; need multiple by page size to get correct address |
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189 MOV r6, #KNandPageSize ; 2048 |
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190 |
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191 ;Set Address Reg1 (lower range) |
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192 MUL r7, r0, r6 |
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193 LDR r4, =KNandPgeAdr1Reg |
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194 STRH r7, [r4] |
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195 |
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196 ;Set Address Reg2 (upper range) |
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197 ;MUL r7, r0, r6 |
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198 LSR r7, r7, #0x10; |
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199 LDR r4, =KNandPgeAdr2Reg |
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200 STRH r7, [r4] |
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201 |
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202 ; Issue Read Command |
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203 LDR r5, =KNandPageReadBM ; CMD_READ | XROMC_BUSY_BIT_MASK |
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204 LDR r4, =KNandCmdSetReg ; XROMC |
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205 STRH r5, [r4] |
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206 |
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207 ; Poll Busy Bit |
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208 1 |
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209 LDRH r5, [r4] ; Get contents of Command setup register |
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210 TST r5, #KNandBusyBit |
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211 BNE %B1 |
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212 |
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213 ; Poll status DRC(Data Read Complete) |
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214 2 |
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215 LDR r4, =KNandDataAreaECCReg |
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216 LDRH r5, [r4] ; Get contents of ECC register |
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217 TST r5, #KNandECCDRC |
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218 BNE %B2 |
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219 |
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220 ;Copy page (2048) into address [r1] |
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221 LDR r4, =KNandDataWndw |
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222 MOV r6, #KNandPageSize ; 2048 |
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223 read |
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224 LDRH r5, [r4] |
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225 STRH r5, [r1], #2 ; save at target |
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226 ADD r4, r4, #2 ; move data wndw pointer |
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227 SUBS r6, r6, #2 ; end of page? |
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228 BNE read ; no => copy some more ;) |
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229 |
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230 ldmfd r13!, {r4-r7,pc} ; yes, return |
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231 |
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232 ;----------------------------------------------------------------------------------- |
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233 ; readpages16 |
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234 ; |
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235 ; read <r2> pages of NAND, |
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236 ; starting at page <r0> |
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237 ; placing data starting at <r1> |
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238 ; |
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239 ;----------------------------------------------------------------------------------- |
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240 readpages16 ROUT |
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241 stmfd r13!, {r4-r6,lr} |
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242 mov r4, r0 |
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243 mov r5, r1 |
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244 mov r6, r2 |
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245 loop16 |
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246 bl readpage16 |
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247 subs r6, r6, #1 |
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248 ldmeqfd r13!, {r4-r6,pc} |
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249 add r0, r0, #1 |
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250 b loop16 |
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251 |
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252 ;----------------------------------------------------------------------------------- |
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253 ; |
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254 ; readhdr16 |
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255 ; |
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256 ; Read the NAND header from flash into ram so it may be examined for a Symbian |
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257 ; signature. |
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258 ; |
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259 ;----------------------------------------------------------------------------------- |
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260 readhdr16 |
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261 ; read the header of a 16b device |
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262 ;Print page |
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263 |
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264 ldr r0, =0x0 ; header pag |
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265 ldr r1, =KCoreLoaderAddress ; |
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266 bl readpage16 |
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267 |
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268 b parse_header |
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269 |
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270 ;--------------------------------------------------------------------------- |
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271 ; |
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272 ; At this point the header buffer contains the first NAND page |
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273 ; Determine whether the NAND device has been formatted according to the |
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274 ; new style Symbian FBR layout |
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275 ; |
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276 ;--------------------------------------------------------------------------- |
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277 |
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278 parse_header |
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279 bl find_symbian_coreldr |
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280 cmp r0, #0 |
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281 beq load_symbian_coreldr |
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282 |
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283 ; Use a label rather than a SUB/PC as it makes a symbol for a debugger. |
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284 SymbianCoreldrNotFound |
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285 |
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286 b SymbianCoreldrNotFound ; spin forever |
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287 |
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288 ; NOTREACHED |
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289 |
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290 ;--------------------------------------------------------------------------------- |
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291 ; |
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292 ; find_symbian_coreldr |
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293 ; |
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294 ; searches for the Symbian1 signature in the FBR then assumes |
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295 ; that the coreldr will be stored in the 30 pages (15k) starting |
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296 ; at page 4. |
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297 ; |
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298 ;--------------------------------------------------------------------------------- |
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299 |
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300 Symbian_Signature DCB "1naibmyS" |
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301 Symbian_Signature_size EQU 8 |
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302 |
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303 |
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304 find_symbian_coreldr ROUT |
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305 stmfd r13!, {r4,lr} |
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306 ldr r0, =KCoreLoaderAddress |
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307 add r0, r0, #4 ; signature at byte 4 in page 0 |
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308 ADR r1, Symbian_Signature |
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309 ldr r3, =Symbian_Signature_size |
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310 bl strcmp |
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311 ldmfd r13!, {r4,pc} |
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312 |
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313 ;--------------------------------------------------------------------------------- |
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314 ; |
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315 ; load_symbian_coreldr |
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316 ; |
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317 ; Assumses Coreloader starts at page 1 and can be as big as 64 pages (128KB) |
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318 ; |
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319 ;--------------------------------------------------------------------------------- |
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320 load_symbian_coreldr ROUT |
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321 |
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322 mov r0, #KSymbianCoreldrPage |
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323 ldr r1, =KCoreLoaderAddress |
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324 mov r2, #KSymbianCoreldrSizePages |
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325 bl readpages16 |
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326 |
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327 ; restart CPUs, by calling restart vertor. |
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328 mov r0, #KtRestartReasonCoreLdr |
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329 add pc, r12, #TRomHeader_iRestartVector |
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330 |
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331 ; NOTREACHED |
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332 END |