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1 ; |
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2 ; Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 ; All rights reserved. |
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4 ; This component and the accompanying materials are made available |
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5 ; under the terms of "Eclipse Public License v1.0" |
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6 ; which accompanies this distribution, and is available |
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7 ; at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 ; |
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9 ; Initial Contributors: |
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10 ; Nokia Corporation - initial contribution. |
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11 ; |
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12 ; Contributors: |
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13 ; |
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14 ; Description: |
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15 ; ne1_tb/bootstrap/ne1_tb.s |
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16 ; NE1_TBVariant for platform specific boot code |
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17 ; |
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18 |
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19 GBLL __VARIANT_S__ ; indicates that this is platform-specific code |
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20 GBLL __NE1_TB_S__ ; indicates which source file this is |
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21 |
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22 INCLUDE bootcpu.inc |
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23 INCLUDE arm_types.inc |
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24 INCLUDE naviengine.inc |
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25 |
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26 IF CFG_DebugBootRom |
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27 GBLL CFG_InitDebugPort |
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28 ENDIF |
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29 INIT_LOGICAL_SYMBOL CFG_InitDebugPort |
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30 |
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31 IF :DEF: CFG_AlternateEntryPoint; NOTE: Bootloader is defined by this macro |
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32 IMPORT GetCoreldr |
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33 ENDIF |
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34 |
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35 ;******************************************************************************* |
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36 ; |
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37 ; Platform specific constant definitions |
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38 |
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39 IF :DEF: CFG_AlternateEntryPoint :LOR: CFG_MMDirect |
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40 RamBank0MaxSize EQU 0x08000000 ; for bootloader or direct, the upper half is reserverd for the image |
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41 ELSE |
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42 RamBank0MaxSize EQU 0x10000000 |
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43 ENDIF |
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44 |
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45 PrimaryRomBase EQU 0x00000000 |
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46 PrimaryRomSize EQU 0x04000000 |
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47 ExtensionRomBase EQU 0x08000000 |
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48 ExtensionRomSize EQU 0x00000000 |
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49 |
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50 |
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51 ;******************************************************************************* |
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52 |
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53 ; ASSP Specific constants |
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54 |
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55 IF :LNOT: CFG_MMDirect |
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56 |
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57 ;Serial Ports Linear Addresses: |
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58 |
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59 Serial0LinBase EQU KPrimaryIOBase |
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60 Serial1LinBase EQU KPrimaryIOBase + (KHwUART1Phys - KHwUART0Phys) |
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61 |
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62 ENDIF |
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63 |
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64 ;Serial Port Register Offsets |
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65 Serial_DLL EQU 0 |
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66 Serial_DLH EQU 4 |
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67 Serial_LCR EQU 0xc |
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68 Serial_THR EQU 0 |
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69 Serial_LSR EQU 0x14 |
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70 |
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71 |
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72 IF :LNOT: CFG_MMDirect |
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73 |
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74 SysCtrlUnitLinBase EQU KPrimaryIOBase + (0x1000*3)+0x1c00 |
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75 ; ... as the value in ne1_tb_bootloader\inc\bootloader_variantconfig.h |
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76 ENDIF |
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77 |
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78 ;******************************************************************************* |
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79 ; There are 4 red LEDs that can be controlled by a 16 bit register in the FPGA. |
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80 ; Each LED has a bit in the register, where 0==off and 1==on |
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81 ; We use each register to show the CPU status, where: |
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82 ; off is "not started" |
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83 ; on is "started" |
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84 ; once the system is running, the OS may use the LEDs for other purposes |
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85 ;******************************************************************************* |
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86 KHwFpgaLedsPhyicalBase EQU KHwFPGAPhys + KHoFpgaLeds; |
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87 |
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88 IF :LNOT: CFG_MMDirect |
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89 KHwFpgaLedsLinBase EQU KPrimaryIOBase + 0xB000 + KHoFpgaLeds; |
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90 ENDIF |
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91 |
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92 |
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93 ;******************************************************************************* |
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94 ; struct SSmrIF |
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95 ; interface between Core Loader and Bootstrap |
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96 ; See: bootstrap_smrif.h |
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97 ;******************************************************************************* |
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98 SSmrIF_iNumOfShwPart EQU 0x00000000 |
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99 SSmrIF_iSmribSize EQU 0x00000004 |
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100 SSmrIF_iSmrBanks EQU 0x00000008 |
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101 SSmrIF_sz EQU 0x0000000c |
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102 |
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103 |
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104 |
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105 ;******************************************************************************* |
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106 ; |
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107 |
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108 AREA |Boot$$Code|, CODE, READONLY, ALIGN=6 |
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109 |
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110 ; |
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111 ;******************************************************************************* |
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112 ; |
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113 |
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114 |
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115 ;*************************************************************************************** |
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116 ; Determine variant required when running on NaviEngine NE1-TB |
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117 ; Enter with: |
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118 ; R12 points to TRomHeader |
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119 ; NO STACK |
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120 ; R14 = return address (as usual) |
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121 ; |
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122 ; Return with: |
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123 ; R10 = Super page address |
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124 ;*************************************************************************************** |
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125 ; |
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126 ; The SuperPage is placed at the start of the free RAM. |
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127 EXPORT CalculateSuperPageAddress |
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128 CalculateSuperPageAddress |
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129 MOV r7, lr |
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130 ANDS r10, pc, #KHwDDR2RamBasePhys ; running from RAM? if not, r10=0 |
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131 MOVEQ r10, #KHwDDR2RamBasePhys ; if running from flash, super page is at base of RAM bank 0 |
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132 BLNE SetupSuperPageRunningFromRAM ; if running from RAM, super page goes after ROM image(s) |
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133 MOV lr, r7 |
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134 MOV pc, lr |
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135 |
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136 ;******************************************************************************* |
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137 ; Initialise Hardware |
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138 ; Initialise CPU registers |
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139 ; Determine the hardware configuration |
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140 ; Determine the reset reason. If it is wakeup from a low power mode, perform |
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141 ; whatever reentry sequence is required and jump back to the kernel. |
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142 ; Set up the memory controller so that at least some RAM is available |
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143 ; Set R10 to point to the super page or to a temporary version of the super page |
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144 ; with at least the following fields valid: |
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145 ; iBootTable, iCodeBase, iActiveVariant, iCpuId |
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146 ; and optionally: |
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147 ; iSmrData |
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148 ; In debug builds initialise the debug serial port |
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149 ; |
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150 ; Enter with: |
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151 ; R2 = value as at entry to ResetEntry, preserved unmodified |
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152 ; R3 = value of cpsr on entry to ResetEntry |
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153 ; R12 = points to TRomHeader |
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154 ; NO STACK |
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155 ; R14 = return address (as usual) |
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156 ; |
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157 ; Leave with : |
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158 ; R10 = physical address of super page |
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159 ; |
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160 ; All registers may be modified by this call |
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161 ; |
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162 ;******************************************************************************* |
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163 EXPORT InitialiseHardware |
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164 InitialiseHardware ROUT |
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165 MOV r13, lr ; save return address |
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166 |
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167 MOV r8, r2 ; Preserve r2, r3 (cpsr) till later |
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168 MOV r9, r3 ; S/P initialisation by boot processor |
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169 |
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170 IF :DEF: CFG_AlternateEntryPoint; NOTE: Bootloader is defined by this macro |
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171 |
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172 LDR r1, =KHwSYSCTRLPhys + 0x00C ; Reset status |
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173 LDR r1, [r1] |
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174 ANDS r1, r1, #0x00030000 ; soft-reset or hot-reset? |
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175 BNE changed_wtop_mode |
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176 |
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177 LDR r1, =KHwSYSCTRLPhys + 0x11C ; WTOP |
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178 LDR r0, [r1] |
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179 ANDS r0, r0, #0xFFFFFFFE ; clear bit 0b to be normal mode |
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180 STR r0, [r1] |
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181 |
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182 LDR r1, =KHwSYSCTRLPhys + 0x00C ; Reset status |
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183 MOV r0, #0x00000001 |
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184 STR r0, [r1] ; soft reset is executed |
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185 |
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186 changed_wtop_mode |
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187 ; Fix the WFE JTAG problem: WFE operations disconnected the JTAG debugger |
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188 ; 0x18037d08 = 0; // SCU CPU status = 0 |
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189 LDR r0, =KHwSYSCTRLPhys |
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190 MOV r1, #0 |
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191 STR r1, [r0, #0x108] |
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192 |
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193 ARM_DSB |
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194 |
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195 ; 0xC0000008 = 0; // SCU CPU status = 0 |
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196 LDR r0, =KHwBaseMPcorePrivatePhys |
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197 MOV r1, #0 |
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198 STR r1, [r0, #0x08] |
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199 |
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200 ARM_DSB |
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201 |
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202 ; Check boot reason in the SCU Memo register |
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203 ; Using ADRL as when CFG_DebugBootRom defined, SysCtrlUnitPhysicalAdr |
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204 ; beyond range for an ADR instruction. |
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205 ADRL r1, SysCtrlUnitPhysicalAdr |
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206 LDR r1, [r1] |
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207 LDR r0, [r1] |
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208 |
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209 ; Check if miniboot has run, and we're ready for the coreldr |
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210 TST r0, #KtRestartReasonCoreLdr |
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211 MOVNE r5, #KCoreLoaderAddress ; Jump into coreldr, NO RETURN! |
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212 BNE all_cores_run_r5 |
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213 |
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214 TST r0, #KtRestartReasonBootRestart |
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215 BEQ check_cpu_id |
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216 MOV r5, #KRamTargetAddr |
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217 |
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218 all_cores_run_r5 |
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219 ; There is something for all cores to run (coreldr or new image) |
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220 ; at the address in r5. |
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221 ; But, before we start, we need to get CPU0 to initialise the ASSP |
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222 ; to make RAM accessible, and reset the Memo register. |
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223 ; Otherwise, if the board reboots again (eg. if the user presses the reset switch) |
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224 ; then the BootLoader will attempt to boot the RAM image again. And after the |
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225 ; reset switch, RAM is not longer valid. |
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226 |
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227 ; Is this the boot processor ? |
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228 MRC p15, 0, r0, c0, c0, 5 |
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229 ANDS r0, r0, #0x0f ; r0 = CPU number 0-3 |
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230 BNE skip_init_step ; Branch out if CPU != 0 (!= boot processor) |
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231 |
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232 ; Initialise RAM controller etc. Only if NOT running from RAM |
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233 CMP PC, #KHwDDR2RamBasePhys |
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234 BLLS AsspInitialiseHardware |
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235 |
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236 ; Set SCU Memo register using CPU0 |
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237 ADR r1, SysCtrlUnitPhysicalAdr |
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238 LDR r1, [r1] |
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239 MOV r0, #0 |
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240 STR r0, [r1] ; clear restart reason to 0 |
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241 |
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242 skip_init_step |
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243 LDR r0, =KHwSYSCTRLPhys + 0x014 ; Peripheral reset control |
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244 LDR r1, [r0] |
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245 CMP r1, #0 |
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246 BNE skip_init_step ; wait for AsspInitialiseHardware to complete |
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247 |
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248 MOV pc, r5 ; Jump into loaded code, NO RETURN! |
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249 |
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250 ENDIF |
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251 |
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252 check_cpu_id |
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253 ; Is this the boot processor ? |
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254 MRC p15, 0, r0, c0, c0, 5 |
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255 ANDS r0, r0, #0x0f ; r0 = CPU number 0-3 |
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256 BEQ IsBootProcessor ; Branch out if CPU 0 (= boot processor) |
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257 |
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258 ; No - this is an AP |
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259 IF SMP |
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260 LDR r11, =KHwBaseMPcorePrivatePhys ; r11 points to SCU |
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261 ADD r8, r11, #0x1000 ; Physical address of GIC Distributor |
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262 ADD r9, r11, #0x100 ; Physical address of GIC CPU Interface |
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263 B APResetEntry ; NO RETURN! |
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264 ELSE |
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265 1 |
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266 mov r0, #0 |
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267 mcr p15, 0, r0, c7, c0, 4 |
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268 B %BA1 ; NO RETURN! |
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269 ENDIF |
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270 |
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271 ; This is the boot processor |
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272 IsBootProcessor |
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273 ; Initialise RAM controller etc. Only if NOT running from RAM |
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274 CMP PC, #KHwDDR2RamBasePhys |
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275 BLLS AsspInitialiseHardware |
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276 |
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277 IF :DEF: CFG_AlternateEntryPoint; NOTE: Bootloader is defined by this macro |
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278 ; Check for Alternate boot reasons (other than KtRestartReasonBootRestart) |
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279 ADR r1, SysCtrlUnitPhysicalAdr |
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280 LDR r1, [r1] |
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281 LDR r0, [r1] |
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282 |
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283 TST r0, #KtRestartReasonNANDImage ; Check for specific nand boot restart reason |
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284 BNE GetCoreldr ; try booting from NAND flash, NO RETURN! |
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285 ENDIF |
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286 |
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287 ; Turn on LED for CPU 0 and turn off LEDs for CPU 1, 2, 3 |
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288 GET_ADDRESS r0, KHwFpgaLedsPhyicalBase, KHwFpgaLedsLinBase |
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289 ; r0 is the address of the 16bit LED register in FPGA, aka FLED |
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290 MOV r1, #KHtFpgaLed0 ; Turn on LED for CPU0 and turn off the other LEDs |
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291 STRH r1, [r0] ; write r1 back to the FLED register |
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292 |
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293 IF :DEF: CFG_USE_SHARED_MEMORY |
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294 ; Switch on Snoop Control Unit. |
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295 ; The whole procedure for switching to SMP is: |
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296 ; - Set SCU on. : Done here |
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297 ; - Disable INTs : Alreday disabled |
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298 ; - Flush DCache : See InitCpu |
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299 ; - Set SMP bit in AUX reg : See InitCpu |
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300 ; - Enable INTs : Later on |
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301 MOV r0, #KHwBaseMPcorePrivatePhys |
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302 MVN r1, #0 |
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303 STR r1, [r0, #0x0C] ; invalidate all SCU ways |
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304 LDR r1, [r0] |
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305 ORR r1, r1, #1 ; SCU Enable |
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306 ORR r1, r1, #0xFE ; Enable all aliases of everything |
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307 ORR r1, r1, #0x1F |
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308 STR r1, [r0] |
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309 ENDIF |
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310 |
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311 ADRL r1, ParameterTable ; pass address of parameter table |
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312 BL InitCpu ; initialise CPU/MMU registers, r0..r7 modified |
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313 |
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314 IF CFG_InitDebugPort |
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315 BL InitDebugPort ; r0..r2 modified |
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316 ENDIF |
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317 |
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318 |
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319 ;;;;;;;;;;;; |
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320 ; Put super page at end of SDRAM for now and set up the required super page values |
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321 ;;;;;;;;;;; |
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322 |
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323 ; LDR r10, =(KHwSdramBaseAddr+(KHwRamSizeMb<<20)-0x2000) |
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324 BL CalculateSuperPageAddress |
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325 |
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326 |
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327 LDR r7, =CFG_HWVD ; variant number from config.inc |
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328 STR r7, [r10, #SSuperPageBase_iActiveVariant] |
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329 |
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330 MOV r1, #0 |
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331 STR r1, [r10, #SSuperPageBase_iHwStartupReason] ; reset reason = 0 |
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332 |
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333 ADD r1, r10, #CpuPageOffset |
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334 STR r1, [r10, #SSuperPageBase_iMachineData] |
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335 |
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336 ADRL r0, BootTable |
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337 STR r0, [r10, #SSuperPageBase_iBootTable] ; set the boot function table |
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338 |
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339 STR r12, [r10, #SSuperPageBase_iCodeBase] ; set the base address of bootstrap code |
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340 |
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341 MRC p15, 0, r0, c0, c0, 0 ; read CPU ID from CP15 |
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342 STR r0, [r10, #SSuperPageBase_iCpuId] |
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343 |
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344 |
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345 ; Process SMRIB from pre-OS Loader and copy to CPU Page. |
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346 ; |
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347 ; r8 = r2 from ResetEntry = Address of block: <SMRIB size><SMRIB entries><...> |
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348 ; r9 = r3 the CPSR from entry of ResetEntry |
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349 ; |
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350 ; SMRIB address in r2 only valid when cpsr (r3) shows ResetEntry entered |
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351 ; with System CPU mode set. Such a scenario can only be supported from |
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352 ; local media ROM boots. i.e. boot from NAND |
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353 ; |
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354 |
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355 AND r0, r9, #EMaskMode ; Check for System CPU mode |
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356 CMP r0, #ESystemMode |
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357 MVNNE r0, #0 ; Set iSmrData to KSuperPageAddressFieldUndefined when CPU |
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358 STRNE r0, [r10, #SSuperPageBase_iSmrData] ; not in system mode before |
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359 BNE NoSMRIB ; i.e. no SMRIB present/defined |
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360 |
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361 ; Proceed to copy SMRIB to Cpu Page at SP+CpuSmrTableOffset |
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362 |
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363 ADD r1, r10, #CpuSmrTableOffset ; Set the iSmrData member to the SMRIB address |
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364 STR r1, [r10, #SSuperPageBase_iSmrData] ; in the CpuPage, see bootdefs.h, space |
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365 ; for 8 SSmrBank records, max. Sets r1 for call to WordMove |
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366 |
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367 ; preparing r0, r2 for call to WordMove |
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368 LDR r0, [r8, #SSmrIF_iSmrBanks] ; Load SMR Banks starting address from SSmrIF::iSmrBanks |
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369 ; see kernboot.h |
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370 |
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371 LDR r2, [r8, #SSmrIF_iSmribSize] ; Load SMRIB size from SSmrIF::iSmribSize and validate, while |
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372 |
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373 DWORD r0, "Variant Bootstrap found SMRIB at" |
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374 DWORD r2, "With the size of the SMRIB being" |
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375 DWORD r1, "Will copy to " |
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376 |
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377 CMP r2, #SSmrBank_sz |
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378 FAULT LT ; Fault if SMRIB size < 16 |
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379 CMP r2, #CpuSmrTableTop-CpuSmrTableOffset-16 ; -16 to allow space for null entry, 7 entries allowed |
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380 FAULT GT ; Fault if SMRIB size > 112 |
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381 |
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382 BL WordMove ; r0=src addr, r1=dest addr, r2=bytes, modifies r0..r3 |
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383 ; No need to copy or add zero entry, Cpu page zerod already |
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384 NoSMRIB |
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385 |
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386 |
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387 MOV pc, r13 |
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388 ; END of InitialiseHardware() |
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389 |
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390 |
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391 |
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392 ;******************************************************************************* |
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393 ; Initialise Assp H/W (memory controllers) |
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394 ; |
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395 ; Enter with : |
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396 ; R12 points to ROM header |
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397 ; There is no valid stack |
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398 ; |
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399 ; Leave with : |
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400 ; R0-R2 modified |
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401 ; Other registers unmodified |
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402 ;******************************************************************************* |
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403 EXPORT AsspInitialiseHardware |
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404 AsspInitialiseHardware ROUT |
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405 |
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406 ADR r0,Init_data |
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407 1 |
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408 LDR r1,[r0],#4 |
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409 LDR r2,[r0],#4 |
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410 CMP r1, #0 |
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411 BEQ %FT2 |
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412 STR r2,[r1] |
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413 B %BT1 |
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414 2 |
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415 MOV pc, r14 ; return |
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416 |
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417 Init_data |
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418 ;*DDR2 Init |
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419 DCD 0x18021044,0x30022123 |
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420 DCD 0x18021058,0x00000001 |
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421 DCD 0x18021008,0x00000020 |
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422 |
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423 ;*delay(Reset Status Register dummy write) |
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424 DCD 0x18037C0C,0x00000000 |
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425 DCD 0x18021008,0x10000004 |
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426 DCD 0x18021008,0x00010002 |
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427 DCD 0x18021008,0x00018002 |
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428 DCD 0x18021008,0x00008002 |
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429 DCD 0x18021008,0X1D480002 |
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430 DCD 0x18021008,0x10000004 |
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431 DCD 0x18021008,0x00000001 |
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432 DCD 0x18021008,0x00000001 |
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433 |
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434 ;*delay(Reset Status Register dummy write) |
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435 DCD 0x18037C0C,0x00000000 |
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436 DCD 0x18037C0C,0x00000000 |
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437 DCD 0x18037C0C,0x00000000 |
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438 DCD 0x18021008,0x19480002 |
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439 DCD 0x18021008,0x01308002 |
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440 DCD 0x18021008,0x00000100 |
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441 DCD 0x18021040,0x1485A912 |
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442 DCD 0x18021034,0x00000121 |
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443 |
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444 ;*SysCon Init |
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445 ;* .word 0x18037C80,0x007F0103 |
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446 |
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447 DCD 0x18037C80,0x00000000 |
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448 |
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449 ;*ExBus Init |
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450 DCD 0x1801A000,0x0000004A |
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451 DCD 0x1801A004,0x08000049 |
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452 DCD 0x1801A008,0x0600004E |
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453 DCD 0x1801A00C,0x0400004B |
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454 DCD 0x1801A010,0x1000004A |
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455 DCD 0x1801A014,0x1400000A |
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456 DCD 0x1801A020,0x10388E7F |
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457 DCD 0x1801A024,0x10388E7E |
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458 DCD 0x1801A028,0x10388E7E |
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459 DCD 0x1801A02C,0x10388E7F |
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460 DCD 0x1801A030,0x10388E7E |
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461 DCD 0x1801A034,0x10388E7E |
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462 |
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463 ;*ExBus PCS5 UART-EX Init |
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464 DCD 0x14020003,0x00 |
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465 DCD 0x14020001,0x00 |
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466 DCD 0x14020002,0x07 |
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467 DCD 0x14020003,0x80 |
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468 DCD 0x14020000,0x1E |
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469 DCD 0x14020001,0x00 |
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470 DCD 0x14020003,0x03 |
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471 DCD 0x14020004,0x03 |
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472 |
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473 ;*ExBus PCS5 CharLED |
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474 DCD 0x14000000,0x59 |
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475 DCD 0x14000001,0x45 |
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476 DCD 0x14000002,0x53 |
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477 DCD 0x14000003,0x21 |
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478 DCD 0x14000004,0x21 |
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479 DCD 0x14000005,0x20 |
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480 DCD 0x14000006,0x20 |
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481 DCD 0x14000007,0x20 |
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482 |
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483 ;*ExBus PCS4 LED |
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484 DCD 0x10000030,0x00AA |
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485 |
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486 DCD 0x18037C14,0x00000000; reset release for all peripheral units |
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487 ; other cores are waiting for this, must be last |
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488 |
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489 ;*End |
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490 DCD 0x0, 0x0 |
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491 |
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492 |
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493 ;******************************************************************************* |
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494 ; Notify an unrecoverable error during the boot process |
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495 ; |
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496 ; Enter with: |
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497 ; R14 = address at which fault detected |
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498 ; |
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499 ; Don't return |
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500 ;******************************************************************************* |
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501 EXPORT Fault |
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502 Fault ROUT |
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503 B BasicFaultHandler ; generic handler dumps registers via debug |
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504 ; serial port |
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505 |
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506 |
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507 |
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508 |
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509 |
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510 ;******************************************************************************* |
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511 ; Reboot the system |
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512 ; This function assumes that CPU#0 is running !!! |
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513 ; |
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514 ; Enter with: |
|
515 ; R0 = reboot reason code |
|
516 ; |
|
517 ; Don't return (of course) |
|
518 ;******************************************************************************* |
|
519 ALIGN 32, 0 |
|
520 EXPORT RestartEntry |
|
521 RestartEntry ROUT |
|
522 |
|
523 ; Save R0 parameter in HW dependent register which is preserved over reset |
|
524 GET_ADDRESS r1, KHwSYSCTRLPhys, SysCtrlUnitLinBase |
|
525 STR r0, [r1] |
|
526 |
|
527 ; Set SFTRSTP to reset all peripherals and all cores |
|
528 MOV r0, #1 |
|
529 STR r0, [r1, #0xC] |
|
530 SUB pc, pc, #8 |
|
531 |
|
532 SysCtrlUnitPhysicalAdr |
|
533 DCD KHwSYSCTRLPhys |
|
534 LedPhysicalAdr |
|
535 DCD 0x4010a06 |
|
536 |
|
537 ;******************************************************************************* |
|
538 ; Get a pointer to the list of RAM banks |
|
539 ; |
|
540 ; The pointer returned should point to a list of {BASE; MAXSIZE;} pairs, where |
|
541 ; BASE is the physical base address of the bank and MAXSIZE is the maximum |
|
542 ; amount of RAM which may be present in that bank. MAXSIZE should be a power of |
|
543 ; 2 and BASE should be a multiple of MAXSIZE. The generic code will examine the |
|
544 ; specified range of addresses and determine the actual amount of RAM if any |
|
545 ; present in the bank. The list is terminated by an entry with zero size. |
|
546 ; |
|
547 ; The pointer returned will usually be to constant data, but could equally well |
|
548 ; point to RAM if dynamic determination of the list is required. |
|
549 ; |
|
550 ; Enter with : |
|
551 ; R10 points to super page |
|
552 ; R12 points to ROM header |
|
553 ; R13 points to valid stack |
|
554 ; |
|
555 ; Leave with : |
|
556 ; R0 = pointer |
|
557 ; Nothing else modified |
|
558 ;******************************************************************************* |
|
559 GetRamBanks ROUT |
|
560 ADR r0, %FT1 |
|
561 MOV pc, lr |
|
562 1 |
|
563 DCD KHwDDR2RamBasePhys | RAM_VERBATIM, RamBank0MaxSize |
|
564 DCD 0,0 ; terminator |
|
565 |
|
566 |
|
567 |
|
568 |
|
569 |
|
570 ;******************************************************************************* |
|
571 ; Get a pointer to the list of ROM banks |
|
572 ; |
|
573 ; The pointer returned should point to a list of entries of SRomBank structures, |
|
574 ; usually declared with the ROM_BANK macro. |
|
575 ; The list is terminated by a zero size entry (four zero words) |
|
576 ; |
|
577 ; ROM_BANK PB, SIZE, LB, W, T, RS, SS |
|
578 ; PB = physical base address of bank |
|
579 ; SIZE = size of bank |
|
580 ; LB = linear base if override required - usually set this to 0 |
|
581 ; W = bus width (ROM_WIDTH_8, ROM_WIDTH_16, ROM_WIDTH_32) |
|
582 ; T = type (see TRomType enum in kernboot.h) |
|
583 ; RS = random speed |
|
584 ; SS = sequential speed |
|
585 ; |
|
586 ; Only PB, SIZE, LB are used by the rest of the bootstrap. |
|
587 ; The information given here can be modified by the SetupRomBank call, if |
|
588 ; dynamic detection and sizing of ROMs is required. |
|
589 ; |
|
590 ; Enter with : |
|
591 ; R10 points to super page |
|
592 ; R12 points to ROM header |
|
593 ; R13 points to valid stack |
|
594 ; |
|
595 ; Leave with : |
|
596 ; R0 = pointer |
|
597 ; Nothing else modified |
|
598 ;******************************************************************************* |
|
599 GetRomBanks ROUT |
|
600 ADR r0, %FT1 |
|
601 MOV pc, lr |
|
602 1 |
|
603 IF CFG_MMDirect |
|
604 ROM_BANK KRamTargetAddr, 0x08000000, 0, ROM_WIDTH_32, ERomTypeXIPFlash, 0, 0 ; image in RAM |
|
605 ENDIF |
|
606 ; ROM_BANK PrimaryRomBase, PrimaryRomSize, 0, ROM_WIDTH_32, ERomTypeXIPFlash, 0, 0 |
|
607 ; ROM_BANK ExtensionRomBase, ExtensionRomSize, 0, ROM_WIDTH_32, ERomTypeXIPFlash, 0, 0 |
|
608 DCD 0,0,0,0 ; terminator |
|
609 |
|
610 |
|
611 |
|
612 |
|
613 |
|
614 ;******************************************************************************* |
|
615 ; Get a pointer to the list of hardware banks |
|
616 ; |
|
617 ; The pointer returned should point to a list of hardware banks declared with |
|
618 ; the HW_MAPPING and/or HW_MAPPING_EXT macros. A zero word terminates the list. |
|
619 ; For the direct memory model, all hardware on the system should be mapped here |
|
620 ; and the mapping will set linear address = physical address. |
|
621 ; For the moving or multiple model, only the hardware required to boot the kernel |
|
622 ; and do debug tracing needs to be mapped here. The linear addresses used will |
|
623 ; start at KPrimaryIOBase and step up as required with the order of banks in |
|
624 ; the list being maintained in the linear addresses used. |
|
625 ; |
|
626 ; HW_MAPPING PB, SIZE, MULT |
|
627 ; This declares a block of I/O with physical base PB and address range SIZE |
|
628 ; blocks each of which has a size determined by MULT. The page size used for |
|
629 ; the mapping is determined by MULT. The linear address base of the mapping |
|
630 ; will be the next free linear address rounded up to the size specified by |
|
631 ; MULT. |
|
632 ; The permissions used for the mapping are the standard I/O permissions (BTP_Hw). |
|
633 ; |
|
634 ; HW_MAPPING_EXT PB, SIZE, MULT |
|
635 ; This declares a block of I/O with physical base PB and address range SIZE |
|
636 ; blocks each of which has a size determined by MULT. The page size used for |
|
637 ; the mapping is determined by MULT. The linear address base of the mapping |
|
638 ; will be the next free linear address rounded up to the size specified by |
|
639 ; MULT. |
|
640 ; The permissions used for the mapping are determined by a BTP_ENTRY macro |
|
641 ; immediately following this macro in the HW bank list or by a DCD directive |
|
642 ; specifying a different standard permission type. |
|
643 ; |
|
644 ; HW_MAPPING_EXT2 PB, SIZE, MULT, LIN |
|
645 ; This declares a block of I/O with physical base PB and address range SIZE |
|
646 ; blocks each of which has a size determined by MULT. The page size used for |
|
647 ; the mapping is determined by MULT. The linear address base of the mapping |
|
648 ; is specified by the LIN parameter. |
|
649 ; The permissions used for the mapping are the standard I/O permissions (BTP_Hw). |
|
650 ; |
|
651 ; HW_MAPPING_EXT3 PB, SIZE, MULT, LIN |
|
652 ; This declares a block of I/O with physical base PB and address range SIZE |
|
653 ; blocks each of which has a size determined by MULT. The page size used for |
|
654 ; the mapping is determined by MULT. The linear address base of the mapping |
|
655 ; is specified by the LIN parameter. |
|
656 ; The permissions used for the mapping are determined by a BTP_ENTRY macro |
|
657 ; immediately following this macro in the HW bank list or by a DCD directive |
|
658 ; specifying a different standard permission type. |
|
659 ; |
|
660 ; Configurations without an MMU need not implement this function. |
|
661 ; |
|
662 ; Enter with : |
|
663 ; R10 points to super page |
|
664 ; R12 points to ROM header |
|
665 ; R13 points to valid stack |
|
666 ; |
|
667 ; Leave with : |
|
668 ; R0 = pointer |
|
669 ; Nothing else modified |
|
670 ;******************************************************************************* |
|
671 GetHwBanks ROUT |
|
672 ADR r0, %FT1 |
|
673 MOV pc, lr |
|
674 |
|
675 1 |
|
676 IF CFG_MMDirect |
|
677 HW_MAPPING KHwLANPhys ,1, HW_MULT_1M ; LAN, FPGA |
|
678 HW_MAPPING 0x18000000 ,1, HW_MULT_1M ; I/O registers @ 18000000 |
|
679 HW_MAPPING KHwBaseMPcorePrivatePhys,1, HW_MULT_1M ; MPCORE private range |
|
680 ELSE |
|
681 HW_MAPPING KHwUART0Phys ,1, HW_MULT_4K ; Mapped at KPrimaryIOBase + 0 |
|
682 HW_MAPPING KHwBaseMPcorePrivatePhys,2, HW_MULT_4K ; Mapped at KPrimaryIOBase + 1000h |
|
683 HW_MAPPING KHwTimer0Phys ,2, HW_MULT_4K ; Mapped at KPrimaryIOBase + 3000h |
|
684 HW_MAPPING KHwDispPhys ,4, HW_MULT_4K ; Mapped at KPrimaryIOBase + 5000h |
|
685 HW_MAPPING KHwI2CPhys ,2, HW_MULT_4K ; Mapped at KPrimaryIOBase + 9000h |
|
686 HW_MAPPING KHwFPGAPhys ,1, HW_MULT_4K ; Mapped at KPrimaryIOBase + B000h |
|
687 HW_MAPPING KHwSPDIFPhys ,1, HW_MULT_4K ; Mapped at KPrimaryIOBase + C000h |
|
688 HW_MAPPING KHwSDPhys ,1, HW_MULT_4K ; Mapped at KPrimaryIOBase + D000h |
|
689 HW_MAPPING KHwAHBEXDMACPhys ,6, HW_MULT_4K ; Mapped at KPrimaryIOBase + E000h |
|
690 HW_MAPPING KHwLANPhys ,1, HW_MULT_4K ; Mapped at KPrimaryIOBase + 14000h |
|
691 HW_MAPPING KHwGPIOPhys ,1, HW_MULT_4K ; Mapped at KPrimaryIOBase + 15000h |
|
692 HW_MAPPING KHwAHB32PCI_ExtPhys ,2, HW_MULT_4K ; Mapped at KPrimaryIOBase + 16000h |
|
693 HW_MAPPING KHwUSBHPhys ,2, HW_MULT_4K ; Mapped at KPrimaryIOBase + 18000h |
|
694 HW_MAPPING KHwAXI64DMACPhys ,1, HW_MULT_4K ; Mapped at KPrimaryIOBase + 1A000h |
|
695 ; Next to be mapped at KPrimaryIOBase + 1B000h |
|
696 ENDIF |
|
697 DCD 0 ; Terminator |
|
698 |
|
699 ;******************************************************************************* |
|
700 ; Set up RAM bank |
|
701 ; |
|
702 ; Do any additional RAM controller initialisation for each RAM bank which wasn't |
|
703 ; done by InitialiseHardware. |
|
704 ; Called twice for each RAM bank :- |
|
705 ; First with R3 = 0xFFFFFFFF before bank has been probed |
|
706 ; Then, if RAM is present, with R3 indicating validity of each byte lane, ie |
|
707 ; R3 bit 0=1 if D0-7 are valid, bit1=1 if D8-15 are valid etc. |
|
708 ; For each call R1 specifies the bank physical base address. |
|
709 ; |
|
710 ; Enter with : |
|
711 ; R10 points to super page |
|
712 ; R12 points to ROM header |
|
713 ; R13 points to stack |
|
714 ; R1 = physical base address of bank |
|
715 ; R3 = width (bottom 4 bits indicate validity of byte lanes) |
|
716 ; 0xffffffff = preliminary initialise |
|
717 ; |
|
718 ; Leave with : |
|
719 ; No registers modified |
|
720 ;******************************************************************************* |
|
721 SetupRamBank ROUT |
|
722 MOV pc, lr |
|
723 |
|
724 |
|
725 |
|
726 |
|
727 |
|
728 ;******************************************************************************* |
|
729 ; Set up ROM bank |
|
730 ; |
|
731 ; Do any required autodetection and autosizing of ROMs and any additional memory |
|
732 ; controller initialisation for each ROM bank which wasn't done by |
|
733 ; InitialiseHardware. |
|
734 ; |
|
735 ; The first time this function is called R11=0 and R0 points to the list of |
|
736 ; ROM banks returned by the BTF_RomBanks call. This allows any preliminary setup |
|
737 ; before autodetection begins. |
|
738 ; |
|
739 ; This function is subsequently called once for each ROM bank with R11 pointing |
|
740 ; to the current information held about that ROM bank (SRomBank structure). |
|
741 ; The structure pointed to by R11 should be updated with the size and width |
|
742 ; determined. The size should be set to zero if there is no ROM present in the |
|
743 ; bank. |
|
744 ; |
|
745 ; Enter with : |
|
746 ; R10 points to super page |
|
747 ; R12 points to ROM header |
|
748 ; R13 points to stack |
|
749 ; R11 points to SRomBank info for this bank |
|
750 ; R11 = 0 for preliminary initialise (all banks) |
|
751 ; |
|
752 ; Leave with : |
|
753 ; Update SRomBank info with detected size/width |
|
754 ; Set the size field to 0 if the ROM bank is absent |
|
755 ; Can modify R0-R4 but not other registers |
|
756 ; |
|
757 ;******************************************************************************* |
|
758 SetupRomBank ROUT |
|
759 MOV pc, lr |
|
760 |
|
761 |
|
762 |
|
763 |
|
764 |
|
765 ;******************************************************************************* |
|
766 ; Reserve physical memory |
|
767 ; |
|
768 ; Reserve any physical RAM needed for platform-specific purposes before the |
|
769 ; bootstrap begins allocating RAM for page tables/kernel data etc. |
|
770 ; |
|
771 ; There are two methods for this: |
|
772 ; 1. The function ExciseRamArea may be used. This will remove a contiguous |
|
773 ; region of physical RAM from the RAM bank list. That region will never |
|
774 ; again be identified as RAM. |
|
775 ; 2. A list of excluded physical address ranges may be written at [R11]. |
|
776 ; This should be a list of (base,size) pairs terminated by a (0,0) entry. |
|
777 ; This RAM will still be identified as RAM by the kernel but will not |
|
778 ; be allocated by the bootstrap and will subsequently be marked as |
|
779 ; allocated by the kernel immediately after boot. |
|
780 ; |
|
781 ; Enter with : |
|
782 ; R10 points to super page |
|
783 ; R11 indicates where preallocated RAM list should be written. |
|
784 ; R12 points to ROM header |
|
785 ; R13 points to stack |
|
786 ; |
|
787 ; Leave with : |
|
788 ; R0-R3 may be modified. Other registers should be preserved. |
|
789 ;******************************************************************************* |
|
790 ReservePhysicalMemory ROUT |
|
791 ; IF :DEF: CFG_AlternateEntryPoint |
|
792 ; IF 0 |
|
793 ; STMFD sp!, {r9,r11,lr} |
|
794 ; LDR r0, =KRamTargetAddr ; reserve the first 64MB RAM for the image to download into. |
|
795 ; MOV r1, #0x4000000 ; 64MB |
|
796 ; MOV r2, #0 |
|
797 ; MOV r11, #0 |
|
798 ; LDR r9, [r10, #SSuperPageBase_iRamBootData] |
|
799 ; BL ExciseRamArea ; remove RAM |
|
800 ; LDMFD sp!, {r9,r11,pc} |
|
801 ; ENDIF |
|
802 MOV pc, lr |
|
803 |
|
804 IF CFG_MMDirect |
|
805 INIT_NUMERIC_CONSTANT KTTBRExtraBits, 0x02 |
|
806 ELSE |
|
807 IF SMP |
|
808 INIT_NUMERIC_CONSTANT KTTBRExtraBits, 0x02 |
|
809 ELSE |
|
810 INIT_NUMERIC_CONSTANT KTTBRExtraBits, 0x08 |
|
811 ENDIF |
|
812 ENDIF |
|
813 |
|
814 |
|
815 ;******************************************************************************* |
|
816 ; Return parameter specified by R0 (see TBootParam enum) |
|
817 ; |
|
818 ; Enter with : |
|
819 ; R0 = parameter number |
|
820 ; |
|
821 ; Leave with : |
|
822 ; If parameter value is supplied, R0 = value and N flag clear |
|
823 ; If parameter value is not supplied, N flag set. In this case the |
|
824 ; parameter may be defaulted or the system may fault. |
|
825 ; R0,R1,R2 modified. No other registers modified. |
|
826 ; |
|
827 ;******************************************************************************* |
|
828 GetParameters ROUT |
|
829 ADR r1, ParameterTable |
|
830 B FindParameter |
|
831 ParameterTable |
|
832 ; Include any parameters specified in TBootParam enum here |
|
833 ; if you want to override them. |
|
834 DCD BPR_TTBRExtraBits, KTTBRExtraBits |
|
835 IF CFG_MMDirect |
|
836 DCD BPR_UncachedLin, 0x7F000000 ; parameter number, parameter value |
|
837 IF SMP |
|
838 DCD BPR_APBootLin, 0x7F001000 ; parameter number, parameter value |
|
839 ENDIF |
|
840 ; IF CFG_BootLoader |
|
841 ; DCD BPR_BootLdrImgAddr, KRamImageAddr |
|
842 ; ENDIF |
|
843 ENDIF |
|
844 DCD -1 ; terminator |
|
845 |
|
846 ;******************************************************************************* |
|
847 ; Do final platform-specific initialisation before booting the kernel |
|
848 ; |
|
849 ; Typical uses for this call would be: |
|
850 ; 1. Mapping cache flushing areas |
|
851 ; 2. Setting up pointers to routines in the bootstrap which are used by |
|
852 ; the variant or drivers (eg idle code). |
|
853 ; |
|
854 ; Enter with : |
|
855 ; R10 points to super page |
|
856 ; R11 points to TRomImageHeader for the kernel |
|
857 ; R12 points to ROM header |
|
858 ; R13 points to stack |
|
859 ; |
|
860 ; Leave with : |
|
861 ; R0-R9 may be modified. Other registers should be preserved. |
|
862 ; |
|
863 ;******************************************************************************* |
|
864 FinalInitialise ROUT |
|
865 STMFD sp!, {lr} |
|
866 |
|
867 IF SMP |
|
868 ; Handshake with APs |
|
869 |
|
870 IF CFG_MMDirect |
|
871 LDR r7, =KHwBaseMPcorePrivatePhys ; R7 points to SCU (physical address for direct memory model) |
|
872 ELSE |
|
873 LDR r7, =KPrimaryIOBase + 0x1000 ; R7 points to SCU (virtual address for other memory models) |
|
874 ENDIF |
|
875 ADD r8, r7, #0x1000 ; Virtual address of GIC Distributor |
|
876 ADD r9, r7, #0x100 ; Virtual address of GIC CPU Interface |
|
877 LDR r5, [r7, #4] ; SCU configuration register |
|
878 DWORD r5, "SCU Config" |
|
879 AND r5, r5, #3 |
|
880 ADD r5, r5, #1 ; r5 = number of CPUs |
|
881 DWORD r5, "NCPUs" |
|
882 MOV r6, #0 ; CPU number |
|
883 B %FA2 |
|
884 1 |
|
885 DWORD r6, "CPU" |
|
886 BL HandshakeAP ; handshake with this AP |
|
887 2 |
|
888 ; Turn on LED for this CPU (CPU0==LED0, etc...) |
|
889 GET_ADDRESS r0, KHwFpgaLedsPhyicalBase, KHwFpgaLedsLinBase |
|
890 ; r0 is the address of the 16 bit LED register in FPGA, aka FLED |
|
891 LDRH r1, [r0] ; read the contents of FLED into r1 |
|
892 MOV r2, #KHtFpgaLed0 |
|
893 MOV r2, r2, LSL r6 ; r2 is the LED value we want to OR in (ie, 1<<CPU number) |
|
894 ORR r1, r1, r2 ; r1 = r1 | r2 |
|
895 STRH r1, [r0] ; write r1 back to the FLED register |
|
896 |
|
897 ADD r6, r6, #1 ; r6 = CPU number of next AP |
|
898 CMP r6, r5 ; if equal to number of CPUs, finished |
|
899 BLO %BA1 ; else do next AP |
|
900 ENDIF |
|
901 |
|
902 LDMFD sp!, {pc} |
|
903 |
|
904 ;******************************************************************************* |
|
905 ; Output a character to the debug port |
|
906 ; |
|
907 ; Enter with : |
|
908 ; R0 = character to output |
|
909 ; R13 points to valid stack |
|
910 ; |
|
911 ; Leave with : |
|
912 ; nothing modified |
|
913 ;******************************************************************************* |
|
914 DoWriteC ROUT |
|
915 IF CFG_DebugBootRom |
|
916 STMFD sp!, {r1,r2,lr} |
|
917 BL GetDebugPortBase ; r1 = base address of debug port |
|
918 |
|
919 ; wait for debug port to be ready for data |
|
920 1 |
|
921 LDR r2, [r1, #Serial_LSR] |
|
922 TST r2, #0x20 |
|
923 BEQ %BT1 |
|
924 |
|
925 ; output character to debug port |
|
926 STR r0, [r1, #Serial_THR] |
|
927 |
|
928 LDMFD sp!, {r1,r2,pc} |
|
929 ELSE |
|
930 MOV pc, lr |
|
931 ENDIF |
|
932 |
|
933 |
|
934 IF CFG_InitDebugPort |
|
935 ;******************************************************************************* |
|
936 ; Initialise the debug port |
|
937 ; |
|
938 ; Enter with : |
|
939 ; R12 points to ROM header |
|
940 ; There is no valid stack |
|
941 ; |
|
942 ; Leave with : |
|
943 ; R0-R2 modified |
|
944 ; Other registers unmodified |
|
945 ;******************************************************************************* |
|
946 InitDebugPort ROUT |
|
947 MOV r0, lr |
|
948 BL GetDebugPortBase ; r1 = base address of debug port |
|
949 |
|
950 LDR r2, [r12, #TRomHeader_iDebugPort] |
|
951 MOVS r2, r2, LSL #24 ; C=1 if high speed, C=0 low speed |
|
952 |
|
953 ; set up debug port |
|
954 MOV r2, #0x83 |
|
955 STR r2, [r1, #Serial_LCR] |
|
956 MOVCS r2, #KBaudRateDiv_230400 |
|
957 MOVCC r2, #KBaudRateDiv_default |
|
958 STR r2, [r1, #Serial_DLL] |
|
959 MOV r2, #0 |
|
960 STR r2, [r1, #Serial_DLH] |
|
961 MOV r2, #0x03 |
|
962 STR r2, [r1, #Serial_LCR] |
|
963 |
|
964 MOV pc, r0 |
|
965 |
|
966 ;******************************************************************************* |
|
967 ; Get the base address of the debug UART |
|
968 ; It is uart0 (for TRomHeader::iDebugPort ==0) or uart1 otherwise |
|
969 ; Returns physical or linear address, depending on the state of MMU. |
|
970 ; |
|
971 ; Enter with : |
|
972 ; R12 points to ROM header |
|
973 ; There may be no stack |
|
974 ; |
|
975 ; Leave with : |
|
976 ; R1 = base address of port |
|
977 ; No other registers modified |
|
978 ;******************************************************************************* |
|
979 GetDebugPortBase ROUT |
|
980 LDR r1, [r12, #TRomHeader_iDebugPort] |
|
981 CMP r1, #0x100 |
|
982 BEQ %FA2 ; port 0 at 230400 |
|
983 CMP r1, #0 |
|
984 BNE %FA1 ; skip if not port 0 |
|
985 2 |
|
986 GET_ADDRESS r1, KHwUART0Phys, Serial0LinBase |
|
987 MOV pc, lr |
|
988 1 |
|
989 GET_ADDRESS r1, KHwUART1Phys, Serial1LinBase |
|
990 MOV pc, lr |
|
991 |
|
992 ENDIF ; CFG_InitDebugPort |
|
993 |
|
994 ;******************************************************************************* |
|
995 ; BOOT FUNCTION TABLE |
|
996 ;******************************************************************************* |
|
997 |
|
998 BootTable |
|
999 DCD DoWriteC ; output a debug character |
|
1000 DCD GetRamBanks ; get list of RAM banks |
|
1001 DCD SetupRamBank ; set up a RAM bank |
|
1002 DCD GetRomBanks ; get list of ROM banks |
|
1003 DCD SetupRomBank ; set up a ROM bank |
|
1004 DCD GetHwBanks ; get list of HW banks |
|
1005 DCD ReservePhysicalMemory ; reserve physical RAM if required |
|
1006 DCD GetParameters ; get platform dependent parameters |
|
1007 DCD FinalInitialise ; Final initialisation before booting the kernel |
|
1008 DCD HandleAllocRequest ; allocate memory |
|
1009 DCD GetPdeValue ; usually in generic code |
|
1010 DCD GetPteValue ; usually in generic code |
|
1011 DCD PageTableUpdate ; usually in generic code |
|
1012 DCD EnableMmu ; Enable the MMU (usually in generic code) |
|
1013 |
|
1014 IF :DEF: CFG_USE_SHARED_MEMORY |
|
1015 SharedMemory EQU 1 |
|
1016 ELSE |
|
1017 SharedMemory EQU 0 |
|
1018 ENDIF |
|
1019 |
|
1020 BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, MEMORY_FULLY_CACHED, 1, 1, 0, SharedMemory ; ROM |
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1021 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, SharedMemory ; kernel data/stack/heap |
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1022 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, SharedMemory ; super page/CPU page |
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1023 IF SMP |
|
1024 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_UNCACHED, 0, 1, 0, SharedMemory ; page directory/tables |
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1025 ELSE |
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1026 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, SharedMemory ; page directory/tables |
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1027 ENDIF |
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1028 BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_FULLY_CACHED, 1, 1, 0, SharedMemory ; exception vectors |
|
1029 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_STRONGLY_ORDERED, 0, 1, 0, SharedMemory ; hardware registers |
|
1030 DCD 0 ; unused (minicache flush) |
|
1031 DCD 0 ; unused (maincache flush) |
|
1032 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, SharedMemory ; page table info |
|
1033 BTP_ENTRY CLIENT_DOMAIN, PERM_RWRW, MEMORY_FULLY_CACHED, 1, 1, 0, SharedMemory ; user RAM |
|
1034 BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_STRONGLY_ORDERED, 1, 1, 0, SharedMemory ; temporary identity mapping |
|
1035 BTP_ENTRY CLIENT_DOMAIN, UNC_PERM, MEMORY_STRONGLY_ORDERED, 0, 1, 0, SharedMemory ; uncached |
|
1036 |
|
1037 |
|
1038 END |
|
1039 |
|
1040 |