;

; Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

; All rights reserved.

; This component and the accompanying materials are made available

; under the terms of "Eclipse Public License v1.0"

; which accompanies this distribution, and is available

; at the URL "http://www.eclipse.org/legal/epl-v10.html".

;

; Initial Contributors:

; Nokia Corporation - initial contribution.

;

; Contributors:

;

; Description:  

; ne1_tb/bootstrap/ne1_tb.s

; NE1_TBVariant for platform specific boot code

;

		GBLL	__VARIANT_S__		; indicates that this is platform-specific code

		GBLL	__NE1_TB_S__		; indicates which source file this is

		INCLUDE	bootcpu.inc

		INCLUDE	arm_types.inc

		INCLUDE naviengine.inc

	IF	CFG_DebugBootRom

	GBLL					CFG_InitDebugPort

	ENDIF

	INIT_LOGICAL_SYMBOL		CFG_InitDebugPort

	IF :DEF: CFG_AlternateEntryPoint; NOTE: Bootloader is defined by this macro

	IMPORT	GetCoreldr

	ENDIF

;*******************************************************************************

;

; Platform specific constant definitions

	IF :DEF: CFG_AlternateEntryPoint :LOR: CFG_MMDirect

RamBank0MaxSize		EQU		0x08000000 ; for bootloader or direct, the upper half is reserverd for the image

	ELSE

RamBank0MaxSize		EQU		0x10000000

	ENDIF

PrimaryRomBase		EQU		0x00000000

PrimaryRomSize		EQU		0x04000000

ExtensionRomBase	EQU		0x08000000

ExtensionRomSize	EQU		0x00000000

;*******************************************************************************

; ASSP Specific constants

	IF :LNOT: CFG_MMDirect

;Serial Ports Linear Addresses:

Serial0LinBase		EQU		KPrimaryIOBase

Serial1LinBase		EQU		KPrimaryIOBase + (KHwUART1Phys - KHwUART0Phys)

	ENDIF

;Serial Port Register Offsets

Serial_DLL			EQU		0

Serial_DLH			EQU		4

Serial_LCR			EQU		0xc

Serial_THR			EQU		0

Serial_LSR			EQU		0x14

	IF :LNOT: CFG_MMDirect

SysCtrlUnitLinBase  		EQU		KPrimaryIOBase + (0x1000*3)+0x1c00

												; ... as the value in ne1_tb_bootloader\inc\bootloader_variantconfig.h

	ENDIF												

;*******************************************************************************

; There are 4 red LEDs that can be controlled by a 16 bit register in the FPGA.

; Each LED has a bit in the register, where 0==off and 1==on

; We use each register to show the CPU status, where:

;    off is "not started"

;    on  is "started"

; once the system is running, the OS may use the LEDs for other purposes

;*******************************************************************************

KHwFpgaLedsPhyicalBase      EQU   KHwFPGAPhys                + KHoFpgaLeds;

	IF :LNOT: CFG_MMDirect

KHwFpgaLedsLinBase          EQU   KPrimaryIOBase   + 0xB000  + KHoFpgaLeds;

	ENDIF												

;*******************************************************************************

; struct SSmrIF

; interface between Core Loader and Bootstrap

; See: bootstrap_smrif.h

;*******************************************************************************

SSmrIF_iNumOfShwPart                    EQU 0x00000000

SSmrIF_iSmribSize                       EQU 0x00000004

SSmrIF_iSmrBanks                        EQU 0x00000008

SSmrIF_sz                               EQU 0x0000000c

;*******************************************************************************

;

        AREA |Boot$$Code|, CODE, READONLY, ALIGN=6

;

;*******************************************************************************

;

;***************************************************************************************

; Determine variant required when running on NaviEngine NE1-TB

; Enter with:

;	R12 points to TRomHeader

;	NO STACK

;	R14 = return address (as usual)

;

; Return with:

;	R10 = Super page address

;***************************************************************************************

;

; The SuperPage is placed at the start of the free RAM.

	EXPORT	CalculateSuperPageAddress

CalculateSuperPageAddress

		MOV		r7, lr

		ANDS	r10, pc, #KHwDDR2RamBasePhys	; running from RAM? if not, r10=0

		MOVEQ	r10, #KHwDDR2RamBasePhys		; if running from flash, super page is at base of RAM bank 0

		BLNE	SetupSuperPageRunningFromRAM	; if running from RAM, super page goes after ROM image(s)

		MOV		lr, r7

		MOV		pc, lr

;*******************************************************************************

; Initialise Hardware

;	Initialise CPU registers

;	Determine the hardware configuration

;	Determine the reset reason. If it is wakeup from a low power mode, perform

;		whatever reentry sequence is required and jump back to the kernel.

;	Set up the memory controller so that at least some RAM is available

;	Set R10 to point to the super page or to a temporary version of the super page

;		with at least the following fields valid:

;		iBootTable, iCodeBase, iActiveVariant, iCpuId

;	and optionally:

;			iSmrData

;	In debug builds initialise the debug serial port

;

; Enter with:

;		R2	= value as at entry to ResetEntry, preserved unmodified

;		R3	= value of cpsr on entry to ResetEntry

;		R12 = points to TRomHeader

;		NO STACK

;		R14 = return address (as usual)

;

; Leave with :

;		R10 = physical address of super page 

;

; All registers may be modified by this call

;

;*******************************************************************************

	EXPORT	InitialiseHardware

InitialiseHardware	ROUT

		MOV		r13, lr					; save return address

		MOV		r8, r2					; Preserve r2, r3 (cpsr) till later

		MOV		r9, r3					; S/P initialisation by boot processor

	IF :DEF: CFG_AlternateEntryPoint; NOTE: Bootloader is defined by this macro

		LDR		r1, =KHwSYSCTRLPhys + 0x00C	; Reset status

		LDR		r1,	[r1]

		ANDS	r1, r1, #0x00030000		; soft-reset or hot-reset?

		BNE		changed_wtop_mode

		LDR		r1, =KHwSYSCTRLPhys + 0x11C	; WTOP

		LDR		r0,	[r1]

		ANDS	r0, r0, #0xFFFFFFFE		; clear bit 0b to be normal mode

		STR		r0, [r1]

		LDR		r1, =KHwSYSCTRLPhys + 0x00C	; Reset status

		MOV		r0, #0x00000001

		STR		r0, [r1]			; soft reset is executed

changed_wtop_mode

		; Fix the WFE JTAG problem:  WFE operations disconnected the JTAG debugger

		; 0x18037d08 = 0;  // SCU CPU status = 0

		LDR		r0, =KHwSYSCTRLPhys

		MOV		r1, #0

		STR		r1, [r0, #0x108]

		ARM_DSB

		; 0xC0000008 = 0;  // SCU CPU status = 0

		LDR		r0, =KHwBaseMPcorePrivatePhys

		MOV		r1, #0

		STR		r1, [r0, #0x08]

		ARM_DSB

		; Check boot reason in the SCU Memo register

		; Using ADRL as when CFG_DebugBootRom defined, SysCtrlUnitPhysicalAdr 

		; beyond range for an ADR instruction.

		ADRL 	r1, SysCtrlUnitPhysicalAdr

		LDR		r1, [r1]

		LDR		r0, [r1]

		; Check if miniboot has run, and we're ready for the coreldr

		TST		r0, #KtRestartReasonCoreLdr

		MOVNE	r5, #KCoreLoaderAddress		; Jump into coreldr, NO RETURN!

		BNE		all_cores_run_r5

		TST		r0,	#KtRestartReasonBootRestart

		BEQ		check_cpu_id

		MOV		r5, #KRamTargetAddr

all_cores_run_r5

		; There is something for all cores to run (coreldr or new image)

		; at the address in r5.

		; But, before we start, we need to get CPU0 to initialise the ASSP

		; to make RAM accessible, and reset the Memo register.

		; Otherwise, if the board reboots again (eg. if the user presses the reset switch)

		; then the BootLoader will attempt to boot the RAM image again.  And after the

		; reset switch, RAM is not longer valid.

		; Is this the boot processor ?

		MRC		p15, 0, r0, c0, c0, 5

		ANDS	r0, r0, #0x0f			; r0 = CPU number 0-3

		BNE		skip_init_step			; Branch out if CPU != 0 (!= boot processor)

		; Initialise RAM controller etc. Only if NOT running from RAM

		CMP		PC, #KHwDDR2RamBasePhys

		BLLS	AsspInitialiseHardware

		; Set SCU Memo register using CPU0

		ADR 	r1, SysCtrlUnitPhysicalAdr

		LDR		r1, [r1]

		MOV		r0, #0

		STR		r0, [r1]				; clear restart reason to 0

skip_init_step

		LDR		r0, =KHwSYSCTRLPhys + 0x014 ; Peripheral reset control

		LDR		r1, [r0]

		CMP		r1, #0

		BNE		skip_init_step			; wait for AsspInitialiseHardware to complete

		MOV		pc, r5					; Jump into loaded code, NO RETURN!

	ENDIF

check_cpu_id

		; Is this the boot processor ?

		MRC		p15, 0, r0, c0, c0, 5

		ANDS	r0, r0, #0x0f			; r0 = CPU number 0-3

		BEQ		IsBootProcessor			; Branch out if CPU 0 (= boot processor)

		; No - this is an AP

	IF	SMP

		LDR		r11, =KHwBaseMPcorePrivatePhys	; r11 points to SCU

		ADD		r8, r11, #0x1000		; Physical address of GIC Distributor

		ADD		r9, r11, #0x100			; Physical address of GIC CPU Interface

		B		APResetEntry			; NO RETURN!

	ELSE

1

		mov		r0, #0

		mcr		p15, 0, r0, c7, c0, 4

		B		%BA1					; NO RETURN!

	ENDIF

		; This is the boot processor

IsBootProcessor

		; Initialise RAM controller etc. Only if NOT running from RAM

		CMP		PC, #KHwDDR2RamBasePhys

		BLLS	AsspInitialiseHardware		

	IF :DEF: CFG_AlternateEntryPoint; NOTE: Bootloader is defined by this macro		

		; Check for Alternate boot reasons (other than KtRestartReasonBootRestart)

		ADR		r1, SysCtrlUnitPhysicalAdr

		LDR		r1,	[r1]

		LDR		r0,	[r1]

		TST		r0, #KtRestartReasonNANDImage	; Check for specific nand boot restart reason

		BNE		GetCoreldr						; try booting from NAND flash, NO RETURN!

	ENDIF	

		; Turn on LED for CPU 0 and turn off LEDs for CPU 1, 2, 3

		GET_ADDRESS	r0, KHwFpgaLedsPhyicalBase, KHwFpgaLedsLinBase

											; r0 is the address of the 16bit LED register in FPGA, aka FLED

		MOV		r1, #KHtFpgaLed0			; Turn on LED for CPU0 and turn off the other LEDs

		STRH	r1, [r0]					; write r1 back to the FLED register

	IF :DEF: CFG_USE_SHARED_MEMORY

		; Switch on Snoop Control Unit.

		; The whole procedure for switching to SMP is:

		;	- Set SCU on. 			: Done here

		;	- Disable INTs			: Alreday disabled

		;	- Flush DCache			: See InitCpu

		;	- Set SMP bit in AUX reg		: See InitCpu

		;	- Enable INTs			: Later on

		MOV		r0, #KHwBaseMPcorePrivatePhys

		MVN		r1, #0

		STR		r1, [r0, #0x0C]			; invalidate all SCU ways

		LDR		r1, [r0]

		ORR		r1, r1, #1				; SCU Enable

		ORR		r1, r1, #0xFE			; Enable all aliases of everything

		ORR		r1, r1, #0x1F

		STR		r1, [r0]

	ENDIF

		ADRL	r1, ParameterTable		; pass address of parameter table

		BL		InitCpu					; initialise CPU/MMU registers, r0..r7 modified

	IF	CFG_InitDebugPort

		BL		InitDebugPort			; r0..r2 modified  

	ENDIF

;;;;;;;;;;;;

; Put super page at end of SDRAM for now and set up the required super page values

;;;;;;;;;;;

;        LDR     r10, =(KHwSdramBaseAddr+(KHwRamSizeMb<<20)-0x2000)

		BL		CalculateSuperPageAddress

		LDR		r7, =CFG_HWVD				        ; variant number from config.inc

		STR		r7, [r10, #SSuperPageBase_iActiveVariant]

		MOV		r1, #0

		STR		r1, [r10, #SSuperPageBase_iHwStartupReason]	; reset reason = 0

		ADD		r1, r10, #CpuPageOffset

		STR		r1, [r10, #SSuperPageBase_iMachineData]

		ADRL	r0, BootTable

		STR		r0, [r10, #SSuperPageBase_iBootTable]		; set the boot function table

		STR		r12, [r10, #SSuperPageBase_iCodeBase]		; set the base address of bootstrap code

		MRC		p15, 0, r0, c0, c0, 0						; read CPU ID from CP15

		STR		r0, [r10, #SSuperPageBase_iCpuId]

		; Process SMRIB from pre-OS Loader and copy to CPU Page.

		;

		; r8 = r2 from ResetEntry = Address of block: <SMRIB size><SMRIB entries><...> 

		; r9 = r3 the CPSR from entry of ResetEntry

		;

		; SMRIB address in r2 only valid when cpsr (r3) shows ResetEntry entered

		; with System CPU mode set. Such a scenario can only be supported from 

		; local media ROM boots. i.e. boot from NAND

		;

		AND		r0, r9, #EMaskMode				 	; Check for System CPU mode

		CMP		r0, #ESystemMode

		MVNNE	r0, #0 								; Set iSmrData to KSuperPageAddressFieldUndefined when CPU

		STRNE	r0, [r10, #SSuperPageBase_iSmrData]	; not in system mode before

		BNE		NoSMRIB								; i.e. no SMRIB present/defined

		; Proceed to copy SMRIB to Cpu Page at SP+CpuSmrTableOffset

		ADD		r1, r10, #CpuSmrTableOffset			; Set the iSmrData member to the SMRIB address 

		STR		r1, [r10, #SSuperPageBase_iSmrData] ; in the CpuPage, see bootdefs.h, space 

													; for 8 SSmrBank records, max. Sets r1 for call to WordMove

        ; preparing r0, r2 for call to WordMove                                                    

        LDR     r0, [r8, #SSmrIF_iSmrBanks]         ; Load SMR Banks starting address from SSmrIF::iSmrBanks

                                                    ; see kernboot.h 

        LDR     r2, [r8, #SSmrIF_iSmribSize]        ; Load SMRIB size from SSmrIF::iSmribSize and validate, while

		DWORD	r0, "Variant Bootstrap found SMRIB at"

		DWORD	r2, "With the size of the SMRIB being"

		DWORD	r1, "Will copy to                    "

		CMP		r2, #SSmrBank_sz

		FAULT	LT									; Fault if SMRIB size < 16

		CMP		r2, #CpuSmrTableTop-CpuSmrTableOffset-16	; -16 to allow space for null entry, 7 entries allowed

		FAULT	GT									; Fault if SMRIB size > 112 	

		BL		WordMove							; r0=src addr, r1=dest addr, r2=bytes, modifies r0..r3

													; No need to copy or add zero entry, Cpu page zerod already		  

NoSMRIB

		MOV		pc, r13

		; END of InitialiseHardware()                

;*******************************************************************************

; Initialise Assp H/W (memory controllers)

;

; Enter with :

;		R12 points to ROM header

;		There is no valid stack

;

; Leave with :

;		R0-R2 modified

;		Other registers unmodified

;*******************************************************************************

	EXPORT	AsspInitialiseHardware

AsspInitialiseHardware	ROUT

		ADR		r0,Init_data

1

		LDR		r1,[r0],#4

		LDR		r2,[r0],#4

		CMP		r1, #0

		BEQ		%FT2

		STR		r2,[r1]

		B		%BT1

2

		MOV		pc, r14	; return

Init_data

;*DDR2 Init

	DCD	0x18021044,0x30022123

	DCD 0x18021058,0x00000001

	DCD 0x18021008,0x00000020

;*delay(Reset Status Register dummy write)

    DCD 0x18037C0C,0x00000000

    DCD 0x18021008,0x10000004

    DCD 0x18021008,0x00010002

    DCD 0x18021008,0x00018002

    DCD 0x18021008,0x00008002

    DCD 0x18021008,0X1D480002

    DCD 0x18021008,0x10000004

    DCD 0x18021008,0x00000001

    DCD 0x18021008,0x00000001

;*delay(Reset Status Register dummy write)

    DCD 0x18037C0C,0x00000000

    DCD 0x18037C0C,0x00000000

    DCD 0x18037C0C,0x00000000

    DCD 0x18021008,0x19480002

    DCD 0x18021008,0x01308002

    DCD 0x18021008,0x00000100

    DCD 0x18021040,0x1485A912

    DCD 0x18021034,0x00000121

;*SysCon Init

;*  .word 0x18037C80,0x007F0103

    DCD 0x18037C80,0x00000000

;*ExBus Init

    DCD 0x1801A000,0x0000004A

    DCD 0x1801A004,0x08000049

    DCD 0x1801A008,0x0600004E

    DCD 0x1801A00C,0x0400004B

    DCD 0x1801A010,0x1000004A

    DCD 0x1801A014,0x1400000A

    DCD 0x1801A020,0x10388E7F

    DCD 0x1801A024,0x10388E7E

    DCD 0x1801A028,0x10388E7E

    DCD 0x1801A02C,0x10388E7F

    DCD 0x1801A030,0x10388E7E

    DCD 0x1801A034,0x10388E7E

;*ExBus PCS5 UART-EX Init

	DCD 0x14020003,0x00

	DCD 0x14020001,0x00

	DCD 0x14020002,0x07

	DCD 0x14020003,0x80

	DCD 0x14020000,0x1E

	DCD 0x14020001,0x00

	DCD 0x14020003,0x03

	DCD 0x14020004,0x03

;*ExBus PCS5 CharLED

	DCD 0x14000000,0x59

	DCD 0x14000001,0x45

	DCD 0x14000002,0x53

	DCD 0x14000003,0x21

	DCD 0x14000004,0x21

	DCD 0x14000005,0x20

	DCD 0x14000006,0x20

	DCD 0x14000007,0x20

;*ExBus PCS4 LED

	DCD 0x10000030,0x00AA

    DCD 0x18037C14,0x00000000; reset release for all peripheral units

							 ; other cores are waiting for this, must be last

;*End

    DCD 0x0,		  0x0

;*******************************************************************************

; Notify an unrecoverable error during the boot process

;

; Enter with:

;	R14 = address at which fault detected

;

; Don't return

;*******************************************************************************

	EXPORT	Fault

Fault	ROUT

		B		BasicFaultHandler	; generic handler dumps registers via debug

									; serial port

;*******************************************************************************

; Reboot the system

; This function assumes that CPU#0 is running !!!

;

; Enter with:

;		R0 = reboot reason code

;

; Don't return (of course)

;*******************************************************************************

	ALIGN	32, 0

	EXPORT	RestartEntry

RestartEntry	ROUT

		; Save R0 parameter in HW dependent register which is preserved over reset

		GET_ADDRESS	r1, KHwSYSCTRLPhys, SysCtrlUnitLinBase

		STR		r0, [r1]

		; Set SFTRSTP to reset all peripherals and all cores

		MOV		r0, #1

		STR		r0, [r1, #0xC]