equal
deleted
inserted
replaced
3287 } |
3287 } |
3288 } |
3288 } |
3289 break; |
3289 break; |
3290 case 0xc: |
3290 case 0xc: |
3291 case 0xd: |
3291 case 0xd: |
3292 if (dp && (insn & 0x03e00000) == 0x00400000) { |
3292 // SF Bug 1284 - QEMU has faulty instruction emulation for VMOV (between two ARM core registers and two single-precision registers) - start |
|
3293 // if (dp && (insn & 0x03e00000) == 0x00400000) { |
|
3294 if ((insn & 0x03e00e00) == 0x00400a00) { |
|
3295 // SF Bug 1284 - QEMU has faulty instruction emulation for VMOV (between two ARM core registers and two single-precision registers) - end |
3293 /* two-register transfer */ |
3296 /* two-register transfer */ |
3294 rn = (insn >> 16) & 0xf; |
3297 rn = (insn >> 16) & 0xf; |
3295 rd = (insn >> 12) & 0xf; |
3298 rd = (insn >> 12) & 0xf; |
3296 if (dp) { |
3299 if (dp) { |
3297 VFP_DREG_M(rm, insn); |
3300 VFP_DREG_M(rm, insn); |