/*

 * HwInit.c

 *

 * Copyright(c) 1998 - 2010 Texas Instruments. All rights reserved.      

 * All rights reserved.      

 * 

 * This program and the accompanying materials are made available under the 

 * terms of the Eclipse Public License v1.0 or BSD License which accompanies

 * this distribution. The Eclipse Public License is available at

 * http://www.eclipse.org/legal/epl-v10.html and the BSD License is as below.                                   

 *                                                                       

 * Redistribution and use in source and binary forms, with or without    

 * modification, are permitted provided that the following conditions    

 * are met:                                                              

 *                                                                       

 *  * Redistributions of source code must retain the above copyright     

 *    notice, this list of conditions and the following disclaimer.      

 *  * Redistributions in binary form must reproduce the above copyright  

 *    notice, this list of conditions and the following disclaimer in    

 *    the documentation and/or other materials provided with the         

 *    distribution.                                                      

 *  * Neither the name Texas Instruments nor the names of its            

 *    contributors may be used to endorse or promote products derived    

 *    from this software without specific prior written permission.      

 *                                                                       

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS   

 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT     

 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 

 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT  

 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 

 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT      

 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 

 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 

 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT   

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

/*******************************************************************************/

/*                                                                             */

/*  MODULE:  HwInit.c                                                          */

/*  PURPOSE: HwInit module manages the init process of the TNETW, included     */

/*           firmware download process. It shall perform Hard Reset the chip   */

/*           if possible (this will require a Reset line to be connected to    */

/*           the host); Start InterfaceCtrl; Download NVS and FW               */

/*                                                                             */

/*                                                                             */

/*******************************************************************************/

#define __FILE_ID__  FILE_ID_105

#include "tidef.h"

#include "osApi.h"

#include "report.h"

#include "HwInit_api.h"

#include "FwEvent_api.h"

#include "TwIf.h"

#include "TWDriver.h"

#include "TWDriverInternal.h"

#include "eventMbox_api.h"

#include "CmdBld.h"

#include "CmdMBox_api.h"

extern void TWD_FinalizeOnFailure   (TI_HANDLE hTWD);

extern void cmdBld_FinalizeDownload (TI_HANDLE hCmdBld, TBootAttr *pBootAttr, FwStaticData_t *pFwInfo);

/************************************************************************

 * Defines

 ************************************************************************/

/* Download phase partition */

#define PARTITION_DOWN_MEM_ADDR       0                 

#define PARTITION_DOWN_MEM_SIZE       0x177C0           

#define PARTITION_DOWN_REG_ADDR       REGISTERS_BASE	

#define PARTITION_DOWN_REG_SIZE       0x8800            

/* Working phase partition */

#define PARTITION_WORK_MEM_ADDR1       0x40000

#define PARTITION_WORK_MEM_SIZE1       0x14FC0

#define PARTITION_WORK_MEM_ADDR2       REGISTERS_BASE    

#define PARTITION_WORK_MEM_SIZE2       0xA000   

#define PARTITION_WORK_MEM_ADDR3       0x3004F8     

#define PARTITION_WORK_MEM_SIZE3       0x4   

#define PARTITION_WORK_MEM_ADDR4       0x40404   

/* DRPW setting partition */

#define PARTITION_DRPW_MEM_ADDR       0x40000

#define PARTITION_DRPW_MEM_SIZE       0x14FC0

#define PARTITION_DRPW_REG_ADDR       DRPW_BASE         

#define PARTITION_DRPW_REG_SIZE       0x6000	        

/* Total range of bus addresses range */

#define PARTITION_TOTAL_ADDR_RANGE    0x1FFC0

/* Maximal block size in a single SDIO transfer --> Firmware image load chunk size */

#ifdef _VLCT_

#define MAX_SDIO_BLOCK					(4000)	

#else

#define MAX_SDIO_BLOCK					(500)	

#endif

#define ACX_EEPROMLESS_IND_REG        (SCR_PAD4)

#define USE_EEPROM                    (0)

#define SOFT_RESET_MAX_TIME           (1000000)

#define SOFT_RESET_STALL_TIME         (1000)

#define NVS_DATA_BUNDARY_ALIGNMENT    (4)

#define MAX_HW_INIT_CONSECUTIVE_TXN     15

#define WORD_SIZE                       4

#define WORD_ALIGNMENT_MASK             0x3

#define DEF_NVS_SIZE                    (NVS_TOTAL_LENGTH)

#define RADIO_SM_WAIT_LOOP  32

#define FREF_CLK_FREQ_MASK      0x7

#define FREF_CLK_TYPE_MASK      BIT_3

#define FREF_CLK_POLARITY_MASK  BIT_4

#define FREF_CLK_TYPE_BITS      0xfffffe7f

#define CLK_REQ_PRCM            0x100

#define FREF_CLK_POLARITY_BITS  0xfffff8ff

#define CLK_REQ_OUTN_SEL        0x700

/* time to wait till we check if fw is running */

#define STALL_TIMEOUT   10

#define FIN_LOOP 10

/************************************************************************

 * Macros

 ************************************************************************/

#define SET_DEF_NVS(aNVS)     aNVS[0]=0x01; aNVS[1]=0x6d; aNVS[2]=0x54; aNVS[3]=0x56; aNVS[4]=0x34; \

                              aNVS[5]=0x12; aNVS[6]=0x28; aNVS[7]=0x01; aNVS[8]=0x71; aNVS[9]=0x54; \

                              aNVS[10]=0x00; aNVS[11]=0x08; aNVS[12]=0x00; aNVS[13]=0x00; aNVS[14]=0x00; \

                              aNVS[15]=0x00; aNVS[16]=0x00; aNVS[17]=0x00; aNVS[18]=0x00; aNVS[19]=0x00; \

                              aNVS[20]=0x00; aNVS[21]=0x00; aNVS[22]=0x00; aNVS[23]=0x00; aNVS[24]=eNVS_NON_FILE;\

							  aNVS[25]=0x00; aNVS[26]=0x00; aNVS[27]=0x00;

#define SET_PARTITION(pPartition,uAddr1,uMemSize1,uAddr2,uMemSize2,uAddr3,uMemSize3,uAddr4) \

                    ((TPartition*)pPartition)[0].uMemAdrr = uAddr1; \

                    ((TPartition*)pPartition)[0].uMemSize = uMemSize1; \

                    ((TPartition*)pPartition)[1].uMemAdrr = uAddr2; \

                    ((TPartition*)pPartition)[1].uMemSize = uMemSize2; \

                    ((TPartition*)pPartition)[2].uMemAdrr = uAddr3; \

                    ((TPartition*)pPartition)[2].uMemSize = uMemSize3; \

                    ((TPartition*)pPartition)[3].uMemAdrr = uAddr4; 

#define HW_INIT_PTXN_SET(pHwInit, pTxn)  pTxn = (TTxnStruct*)&(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].tTxnStruct);

#define BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB)     \

                              HW_INIT_PTXN_SET(pHwInit, pTxn) \

                              TXN_PARAM_SET_DIRECTION(pTxn, direction); \

                              *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData)) = (TI_UINT32)uVal; \

                              BUILD_TTxnStruct(pTxn, uAddr, pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData, uSize, fCB, hCB)

#define BUILD_HW_INIT_FW_STATIC_TXN(pHwInit, pTxn, uAddr, fCB, hCB)     \

                              HW_INIT_PTXN_SET(pHwInit, pTxn) \

                              TXN_PARAM_SET_DIRECTION(pTxn, TXN_DIRECTION_READ); \

                              BUILD_TTxnStruct(pTxn, uAddr, pHwInit->tFwStaticTxn.pFwStaticInfo, sizeof(FwStaticData_t), fCB, hCB)

#define BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB)     \

                              HW_INIT_PTXN_SET(pHwInit, pTxn) \

                              TXN_PARAM_SET_DIRECTION(pTxn, direction); \

                              BUILD_TTxnStruct(pTxn, uAddr, uVal, uSize, fCB, hCB)

#define SET_DRP_PARTITION(pPartition)\

                        SET_PARTITION(pPartition, PARTITION_DRPW_MEM_ADDR, PARTITION_DRPW_MEM_SIZE, PARTITION_DRPW_REG_ADDR, PARTITION_DRPW_REG_SIZE, 0, 0, 0)

#define SET_FW_LOAD_PARTITION(pPartition,uFwAddress)\

                            SET_PARTITION(pPartition,uFwAddress,PARTITION_DOWN_MEM_SIZE, PARTITION_DOWN_REG_ADDR, PARTITION_DOWN_REG_SIZE,0,0,0)

#define SET_WORK_PARTITION(pPartition)\

                        SET_PARTITION(pPartition,PARTITION_WORK_MEM_ADDR1, PARTITION_WORK_MEM_SIZE1, PARTITION_WORK_MEM_ADDR2, PARTITION_WORK_MEM_SIZE2, PARTITION_WORK_MEM_ADDR3, PARTITION_WORK_MEM_SIZE3, PARTITION_WORK_MEM_ADDR4)

/* Handle return status inside a state machine */

#define EXCEPT(phwinit,status)                                   \

    switch (status) {                                           \

        case TI_OK:                                             \

        case TXN_STATUS_OK:                                     \

        case TXN_STATUS_COMPLETE:                               \

             break;                                             \

        case TXN_STATUS_PENDING:                                \

             return TXN_STATUS_PENDING;                         \

        default:                                                \

             phwinit->DownloadStatus = TXN_STATUS_ERROR;        \

             TWD_FinalizeOnFailure (phwinit->hTWD);             \

             return TXN_STATUS_ERROR;                           \

    }

/* Handle return status inside an init sequence state machine  */

#define EXCEPT_I(phwinit,status)                                \

    switch (status) {                                           \

        case TI_OK:                                             \

        case TXN_STATUS_COMPLETE:                               \

             break;                                             \

        case TXN_STATUS_PENDING:                                \

             phwinit->uInitSeqStatus = status;                  \

             return TXN_STATUS_PENDING;                         \

        default:                                                \

             TWD_FinalizeOnFailure (phwinit->hTWD);             \

             return TXN_STATUS_ERROR;                           \

    }

/* Handle return status inside a load image state machine */

#define EXCEPT_L(phwinit,status)                                \

    switch (status) {                                           \

        case TXN_STATUS_OK:                                     \

        case TXN_STATUS_COMPLETE:                               \

             break;                                             \

        case TXN_STATUS_PENDING:                                \

             phwinit->DownloadStatus = status;                  \

             return TXN_STATUS_PENDING;                         \

        default:                                                \

             phwinit->DownloadStatus = status;                  \

             TWD_FinalizeOnFailure (phwinit->hTWD);             \

             return TXN_STATUS_ERROR;                           \

    }

/************************************************************************

 * Types

 ************************************************************************/

enum

{

    REF_FREQ_19_2                   = 0,

    REF_FREQ_26_0                   = 1,

    REF_FREQ_38_4                   = 2,

    REF_FREQ_40_0                   = 3,

    REF_FREQ_33_6                   = 4,

    REF_FREQ_NUM                    = 5

};

enum

{

    LUT_PARAM_INTEGER_DIVIDER       = 0,

    LUT_PARAM_FRACTIONAL_DIVIDER    = 1,

    LUT_PARAM_ATTN_BB               = 2,

    LUT_PARAM_ALPHA_BB              = 3,

    LUT_PARAM_STOP_TIME_BB          = 4,

    LUT_PARAM_BB_PLL_LOOP_FILTER    = 5,

    LUT_PARAM_NUM                   = 6

};

typedef struct 

{

    TTxnStruct              tTxnStruct;

    TI_UINT8                *pData; 

} THwInitTxn;

typedef struct 

{

    TTxnStruct              tTxnStruct;

    TI_UINT8                *pFwStaticInfo; 

} TFwStaticTxn;

/* The HW Init module object */

typedef struct 

{

    /* Handles */

    TI_HANDLE               hOs;

    TI_HANDLE               hReport;

    TI_HANDLE               hTWD;

    TI_HANDLE               hBusTxn;

    TI_HANDLE               hTwIf;

    TI_HANDLE 		    hFileInfo;	/* holds parameters of FW Image Portion - for DW Download */

    TEndOfHwInitCb          fInitHwCb;

    /* Firmware image ptr */

    TI_UINT8               *pFwBuf;       

    /* Firmware image length */

    TI_UINT32               uFwLength;

    TI_UINT32               uFwAddress;

    TI_UINT32               bFwBufLast;  

    TI_UINT32               uFwLastAddr;  

    /* EEPROM image ptr */

    TI_UINT8               *pEEPROMBuf;   

    /* EEPROM image length */

    TI_UINT32               uEEPROMLen;   

    TI_UINT8               *pEEPROMCurPtr;

    TI_UINT32               uEEPROMCurLen;

    TBootAttr               tBootAttr;

    TI_HANDLE               hHwCtrl;

    ETxnStatus              DownloadStatus;

    /* Upper module callback for the init stage */

    fnotify_t               fCb;          

    /* Upper module handle for the init stage */

    TI_HANDLE               hCb;          

    /* Init stage */

    TI_UINT32               uInitStage;   

    /* Reset statge */ 

    TI_UINT32               uResetStage;  

    /* EEPROM burst stage */

    TI_UINT32               uEEPROMStage; 

    /* Init state machine temporary data */

    TI_UINT32               uInitData;    

    /* ELP command image */

    TI_UINT32               uElpCmd;      

    /* Chip ID */

    TI_UINT32               uChipId;      

    /* Boot state machine temporary data */

    TI_UINT32               uBootData;    

    TI_UINT32               uSelfClearTime;

    TI_UINT8                uEEPROMBurstLen;

    TI_UINT8                uEEPROMBurstLoop;

    TI_UINT32               uEEPROMRegAddr;

    TI_STATUS               uEEPROMStatus;

    TI_UINT32               uNVSStartAddr;

    TI_UINT32               uNVSNumChar;

    TI_UINT32               uNVSNumByte;

    TI_STATUS               uNVSStatus;

    TI_UINT32               uScrPad6;

    TI_UINT32               uRefFreq; 

    TI_UINT32               uInitSeqStage;

    TI_STATUS               uInitSeqStatus;

    TI_UINT32               uLoadStage;

    TI_UINT32               uBlockReadNum;

    TI_UINT32               uBlockWriteNum;

    TI_UINT32               uPartitionLimit;

    TI_UINT32               uFinStage;

    TI_UINT32               uFinData;

    TI_UINT32               uFinLoop; 

    TI_UINT32               uRegStage;

    TI_UINT32               uRegLoop;

    TI_UINT32               uRegSeqStage;

    TI_UINT32               uRegData;  

    #ifndef _VLCT_   

        TI_HANDLE               hStallTimer;

    #endif

    /* Top register Read/Write SM temporary data*/

    TI_UINT32               uTopRegAddr;

    TI_UINT32               uTopRegValue;

    TI_UINT32               uTopRegMask;

    TI_UINT32               uTopRegUpdateValue;

    TI_UINT32               uTopStage;

    TI_STATUS               uTopStatus;

    TI_UINT8                *puFwTmpBuf;

    TFinalizeCb             fFinalizeDownload;

    TI_HANDLE               hFinalizeDownload;

    /* Size of the Fw image, retrieved from the image itself */         

    TI_UINT32               uFwDataLen; 

    TI_UINT8                aDefaultNVS[DEF_NVS_SIZE];

    TI_UINT8                uTxnIndex;

    THwInitTxn              aHwInitTxn[MAX_HW_INIT_CONSECUTIVE_TXN];

    TFwStaticTxn            tFwStaticTxn;

    TI_UINT32               uSavedDataForWspiHdr;  /* For saving the 4 bytes before the NVS data for WSPI case 

                                                        where they are overrun by the WSPI BusDrv */

    TPartition              aPartition[NUM_OF_PARTITION];

} THwInit;

/************************************************************************

 * Local Functions Prototypes

 ************************************************************************/

static void      hwInit_SetPartition                (THwInit   *pHwInit, 

                                                     TPartition *pPartition);

static TI_STATUS hwInit_BootSm                      (TI_HANDLE hHwInit);

static TI_STATUS hwInit_ResetSm                     (TI_HANDLE hHwInit);

static TI_STATUS hwInit_EepromlessStartBurstSm      (TI_HANDLE hHwInit);                                                   

static TI_STATUS hwInit_LoadFwImageSm               (TI_HANDLE hHwInit);

static TI_STATUS hwInit_FinalizeDownloadSm          (TI_HANDLE hHwInit);                                             

static TI_STATUS hwInit_TopRegisterRead(TI_HANDLE hHwInit);

static TI_STATUS hwInit_InitTopRegisterRead(TI_HANDLE hHwInit, TI_UINT32 uAddress);

static TI_STATUS hwInit_TopRegisterWrite(TI_HANDLE hHwInit);

static TI_STATUS hwInit_InitTopRegisterWrite(TI_HANDLE hHwInit, TI_UINT32 uAddress, TI_UINT32 uValue);

#ifndef _VLCT_  

    static void      hwInit_StallTimerCb                (TI_HANDLE hHwInit);

#endif

/*******************************************************************************

*                       PUBLIC  FUNCTIONS  IMPLEMENTATION                      *

********************************************************************************/

/*************************************************************************

*                        hwInit_Create                                   *

**************************************************************************

* DESCRIPTION:  This function initializes the HwInit module.

*

* INPUT:        hOs - handle to Os Abstraction Layer

*               

* RETURN:       Handle to the allocated HwInit module

*************************************************************************/

TI_HANDLE hwInit_Create (TI_HANDLE hOs)

{

    THwInit *pHwInit;

    int i;

    /* Allocate HwInit module */

    pHwInit = os_memoryAlloc (hOs, sizeof(THwInit),MemoryNormal);

    if (pHwInit == NULL)

    {

        WLAN_OS_REPORT(("Error allocating the HwInit Module\n"));

        return NULL;

    }

    /* Reset HwInit module */

    os_memoryZero (hOs, pHwInit, sizeof(THwInit));

    /* Allocate Register buffer */

    for (i = 0; i < MAX_HW_INIT_CONSECUTIVE_TXN; i++) 

    {

        pHwInit->aHwInitTxn[i].pData = os_memoryAlloc (hOs, sizeof(TI_UINT32) + WSPI_PAD_LEN_READ,MemoryDMA);

        if (pHwInit->aHwInitTxn[i].pData == NULL) 

        {

            return NULL;

        }

        os_memoryZero (hOs, pHwInit->aHwInitTxn[i].pData, sizeof(TI_UINT32) + WSPI_PAD_LEN_READ);

        pHwInit->aHwInitTxn[i].pData += WSPI_PAD_LEN_READ;

    }

    pHwInit->tFwStaticTxn.pFwStaticInfo = os_memoryAlloc (hOs, sizeof (FwStaticData_t) + WSPI_PAD_LEN_READ,MemoryDMA);

    if (pHwInit->tFwStaticTxn.pFwStaticInfo == NULL) 

    {

        return NULL;

    }

    os_memoryZero (hOs, pHwInit->tFwStaticTxn.pFwStaticInfo, sizeof (FwStaticData_t) + WSPI_PAD_LEN_READ);

    pHwInit->tFwStaticTxn.pFwStaticInfo += WSPI_PAD_LEN_READ;

    pHwInit->puFwTmpBuf = os_memoryAlloc (hOs, WSPI_PAD_LEN_READ + MAX_SDIO_BLOCK,MemoryDMA);

    if (pHwInit->puFwTmpBuf == NULL) 

    {

     return NULL;

    }

    os_memoryZero (hOs, pHwInit->puFwTmpBuf, WSPI_PAD_LEN_READ + MAX_SDIO_BLOCK);

    pHwInit->puFwTmpBuf += WSPI_PAD_LEN_READ;

    pHwInit->hOs = hOs;

    return (TI_HANDLE)pHwInit;

}

/***************************************************************************

*                           hwInit_Destroy                                 *

****************************************************************************

* DESCRIPTION:  This function unload the HwInit module. 

*

* INPUTS:       hHwInit - the object

*

* OUTPUT:

*

* RETURNS:      TI_OK - Unload succesfull

*               TI_NOK - Unload unsuccesfull

***************************************************************************/

TI_STATUS hwInit_Destroy (TI_HANDLE hHwInit)

{

    THwInit *pHwInit = (THwInit *)hHwInit;

    int i;

    for (i = 0; i < MAX_HW_INIT_CONSECUTIVE_TXN; i++) 

    {

        if (pHwInit->aHwInitTxn[i].pData) 

        {

            os_memoryFree (pHwInit->hOs, pHwInit->aHwInitTxn[i].pData - WSPI_PAD_LEN_READ, sizeof(TI_UINT32) + WSPI_PAD_LEN_READ);

        }

    }

    if (pHwInit->puFwTmpBuf) 

     {

         os_memoryFree (pHwInit->hOs, pHwInit->puFwTmpBuf - WSPI_PAD_LEN_READ, WSPI_PAD_LEN_READ + MAX_SDIO_BLOCK);

     }

    if (pHwInit->pEEPROMBuf) 

     {

         os_memoryFree (pHwInit->hOs, pHwInit->pEEPROMBuf, pHwInit->uEEPROMLen);

     }

    if (pHwInit->tFwStaticTxn.pFwStaticInfo)

    {

        os_memoryFree (pHwInit->hOs, pHwInit->tFwStaticTxn.pFwStaticInfo - WSPI_PAD_LEN_READ, sizeof (FwStaticData_t) + WSPI_PAD_LEN_READ);

    }

    #ifndef _VLCT_   

        if (pHwInit->hStallTimer)

        {

            os_timerDestroy(pHwInit->hOs, pHwInit->hStallTimer);

        }        

    #endif

    /* Free HwInit Module */

    os_memoryFree (pHwInit->hOs, pHwInit, sizeof(THwInit));

    return TI_OK;

}

/***************************************************************************

*                           hwInit_Init                                    *

****************************************************************************

* DESCRIPTION:  This function configures the hwInit module

*

* RETURNS:      TI_OK - Configuration successful

*               TI_NOK - Configuration unsuccessful

***************************************************************************/

TI_STATUS hwInit_Init (TI_HANDLE      hHwInit,

                         TI_HANDLE      hReport,

                         TI_HANDLE      hTWD,

                         TI_HANDLE 	hFinalizeDownload, 

			 TFinalizeCb    fFinalizeDownload, 

                         TEndOfHwInitCb fInitHwCb)

{

    THwInit   *pHwInit = (THwInit *)hHwInit;

    TTxnStruct* pTxn;