/*

 * Device1273.h

 *

 * Copyright(c) 1998 - 2010 Texas Instruments. All rights reserved.      

 * All rights reserved.      

 * 

 * This program and the accompanying materials are made available under the 

 * terms of the Eclipse Public License v1.0 or BSD License which accompanies

 * this distribution. The Eclipse Public License is available at

 * http://www.eclipse.org/legal/epl-v10.html and the BSD License is as below.                                   

 *                                                                       

 * Redistribution and use in source and binary forms, with or without    

 * modification, are permitted provided that the following conditions    

 * are met:                                                              

 *                                                                       

 *  * Redistributions of source code must retain the above copyright     

 *    notice, this list of conditions and the following disclaimer.      

 *  * Redistributions in binary form must reproduce the above copyright  

 *    notice, this list of conditions and the following disclaimer in    

 *    the documentation and/or other materials provided with the         

 *    distribution.                                                      

 *  * Neither the name Texas Instruments nor the names of its            

 *    contributors may be used to endorse or promote products derived    

 *    from this software without specific prior written permission.      

 *                                                                       

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS   

 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT     

 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 

 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT  

 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 

 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT      

 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 

 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 

 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT   

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

/**********************************************************************************************************************

  FILENAME:       Device1273.h

  DESCRIPTION:    TNETW1273 Registes addresses/defintion

***********************************************************************************************************************/

#ifndef DEVICE1273_H

#define DEVICE1273_H

/* Base addresses*/

/* They are not used inside registers definition in purpose to allow this header file*/

/* to be used as an easy reference to register -> address date base. Keep this as it*/

/* is very powerful for debugging purpose.*/

#define REGISTERS_BASE	0x00300000

#define INT_BASE		0x00300400

#define REG_CONFIG_BASE	0x00300800

#define CLK_BASE		0x00300C00

#define SDMA_BASE		0x00301000

#define AES_BASE		0x00301400

#define WEP_BASE		0x00301800

#define TKIP_BASE		0x00301C00

#define SEEPROM_BASE	0x00302000

#define PAR_HOST_BASE	0x00302400

#define SDIO_BASE		0x00302800

#define UART_BASE		0x00302C00

#define USB11_BASE		0x00304000

#define LDMA_BASE		0x00304400

#define RX_BASE			0x00304800

#define ACCESS_BASE		0x00304c00

#define TX_BASE			0x00305000

#define RMAC_CSR_BASE	0x00305400

#define AFE_PM			0x00305800

#define VLYNQ_BASE		0x00308000

#define PCI_BASE		0x00308400

#define USB20_BASE		0x0030A000

#define DRPW_BASE		0x00310000

#define PHY_BASE		0x003C0000

/* DRPw init scratch register */

#define DRPW_SCRATCH_START             (DRPW_BASE + 0x002C)

/* System DMA registers*/

/* Order of registers was changed*/

#define DMA_GLB_CFG                    (REGISTERS_BASE + 0x1000)

#define DMA_HDESC_OFFSET               (REGISTERS_BASE + 0x1004)

#define DMA_HDATA_OFFSET               (REGISTERS_BASE + 0x1008)

#define DMA_CFG0                       (REGISTERS_BASE + 0x100C) /* SDMA_HOST_CFG0 changed*/

#define DMA_CTL0                       (REGISTERS_BASE + 0x1010) /* SDMA_CTRL0 changed*/

#define DMA_LENGTH0                    (REGISTERS_BASE + 0x1014)

#define DMA_L_ADDR0                    (REGISTERS_BASE + 0x1018) /* SDMA_RD_ADDR ?*/

#define DMA_L_PTR0                     (REGISTERS_BASE + 0x101C) /* SDMA_RD_OFFSET ?*/

#define DMA_H_ADDR0                    (REGISTERS_BASE + 0x1020) /* SDMA_WR_ADDR ?*/

#define DMA_H_PTR0                     (REGISTERS_BASE + 0x1024) /* SDMA_WR_OFFSET ?*/

#define DMA_STS0                       (REGISTERS_BASE + 0x1028) /* Changed*/

#define DMA_CFG1                       (REGISTERS_BASE + 0x1030) /* SDMA_HOST_CFG1 changed*/

#define DMA_CTL1                       (REGISTERS_BASE + 0x1034) /* SDMA_CTRL1 changed*/

#define DMA_LENGTH1                    (REGISTERS_BASE + 0x1038)

#define DMA_L_ADDR1                    (REGISTERS_BASE + 0x103C)

#define DMA_L_PTR1                     (REGISTERS_BASE + 0x1040)

#define DMA_H_ADDR1                    (REGISTERS_BASE + 0x1044)

#define DMA_H_PTR1                     (REGISTERS_BASE + 0x1048)

#define DMA_STS1                       (REGISTERS_BASE + 0x104C)

#define DMA_HFRM_PTR                   (REGISTERS_BASE + 0x1050) /* New ?*/

#define DMA_DEBUG                      (REGISTERS_BASE + 0x1054) /* Changed*/

/* Local DMA registers*/

/* number changed from 4 to 2*/

#define LDMA_DEBUG                     (REGISTERS_BASE + 0x4400)

#define LDMA_CTL0                      (REGISTERS_BASE + 0x4404) /* Add 2 bits to support fix address (FIFO)*/

#define LDMA_STATUS0                   (REGISTERS_BASE + 0x4408)

#define LDMA_LENGTH0                   (REGISTERS_BASE + 0x440c)

#define LDMA_RD_ADDR0                  (REGISTERS_BASE + 0x4410)

#define LDMA_RD_OFFSET0                (REGISTERS_BASE + 0x4414)

#define LDMA_WR_ADDR0                  (REGISTERS_BASE + 0x4418)

#define LDMA_WR_OFFSET0                (REGISTERS_BASE + 0x441c)

#define LDMA_CTL1                      (REGISTERS_BASE + 0x4428) /* Add 2 bits to support fix address (FIFO)*/

#define LDMA_STATUS1                   (REGISTERS_BASE + 0x442c)

#define LDMA_LENGTH1                   (REGISTERS_BASE + 0x4430)

#define LDMA_RD_ADDR1                  (REGISTERS_BASE + 0x4434)

#define LDMA_RD_OFFSET1                (REGISTERS_BASE + 0x4438)

#define LDMA_WR_ADDR1                  (REGISTERS_BASE + 0x443c)

#define LDMA_WR_OFFSET1                (REGISTERS_BASE + 0x4440)

/* For TNETW compatability (if willbe )*/

#define LDMA_CUR_RD_PTR0               LDMA_RD_ADDR0

#define LDMA_CUR_WR_PTR0               LDMA_WR_ADDR0

#define LDMA_CUR_RD_PTR1               LDMA_RD_ADDR1

#define LDMA_CUR_WR_PTR1               LDMA_WR_ADDR1

/* Host Slave registers*/

#define SLV_SOFT_RESET                 (REGISTERS_BASE + 0x0000) /* self clearing*/

#define SLV_REG_ADDR                   (REGISTERS_BASE + 0x0004)

#define SLV_REG_DATA                   (REGISTERS_BASE + 0x0008)

#define SLV_REG_ADATA                  (REGISTERS_BASE + 0x000c)

#define SLV_MEM_CP                     (REGISTERS_BASE + 0x0010)

#define SLV_MEM_ADDR                   (REGISTERS_BASE + 0x0014)

#define SLV_MEM_DATA                   (REGISTERS_BASE + 0x0018)

#define SLV_MEM_QOS_DATA               (REGISTERS_BASE + 0x001A)

#define SLV_MEM_CTL                    (REGISTERS_BASE + 0x001c) /* bit 19 moved to PCMCIA_CTL*/

#define SLV_END_CTL                    (REGISTERS_BASE + 0x0020) /* 2 bits moved to ENDIAN_CTL*/

/* Timer registers*/

/* Timer1/2 count MAC clocks*/

/* Timer3/4/5 count usec*/

#define TIM1_CTRL                      (REGISTERS_BASE + 0x0918)

#define TIM1_LOAD                      (REGISTERS_BASE + 0x091C)

#define TIM1_CNT                       (REGISTERS_BASE + 0x0920)

#define TIM2_CTRL                      (REGISTERS_BASE + 0x0924)

#define TIM2_LOAD                      (REGISTERS_BASE + 0x0928)

#define TIM2_CNT                       (REGISTERS_BASE + 0x092C)

#define TIM3_CTRL                      (REGISTERS_BASE + 0x0930)

#define TIM3_LOAD                      (REGISTERS_BASE + 0x0934)

#define TIM3_CNT                       (REGISTERS_BASE + 0x0938)

#define TIM4_CTRL                      (REGISTERS_BASE + 0x093C)

#define TIM4_LOAD                      (REGISTERS_BASE + 0x0940)

#define TIM4_CNT                       (REGISTERS_BASE + 0x0944)

#define TIM5_CTRL                      (REGISTERS_BASE + 0x0948)

#define TIM5_LOAD                      (REGISTERS_BASE + 0x094C)

#define TIM5_CNT                       (REGISTERS_BASE + 0x0950)

/* Watchdog registers*/

#define WDOG_CTRL                      (REGISTERS_BASE + 0x0954)

#define WDOG_LOAD                      (REGISTERS_BASE + 0x0958)

#define WDOG_CNT                       (REGISTERS_BASE + 0x095C)

#define WDOG_STS                       (REGISTERS_BASE + 0x0960)

#define WDOG_FEED                      (REGISTERS_BASE + 0x0964)

/* Interrupt registers*/

/* 64 bit interrupt sources registers ws ced. sme interupts were removed and new ones were added*/

/* Order was changed*/

#define FIQ_MASK                       (REGISTERS_BASE + 0x0400)

#define FIQ_MASK_L                     (REGISTERS_BASE + 0x0400)

#define FIQ_MASK_H                     (REGISTERS_BASE + 0x0404)

#define FIQ_MASK_SET                   (REGISTERS_BASE + 0x0408)

#define FIQ_MASK_SET_L                 (REGISTERS_BASE + 0x0408)

#define FIQ_MASK_SET_H                 (REGISTERS_BASE + 0x040C)

#define FIQ_MASK_CLR                   (REGISTERS_BASE + 0x0410)

#define FIQ_MASK_CLR_L                 (REGISTERS_BASE + 0x0410)

#define FIQ_MASK_CLR_H                 (REGISTERS_BASE + 0x0414)

#define IRQ_MASK                       (REGISTERS_BASE + 0x0418)

#define IRQ_MASK_L                     (REGISTERS_BASE + 0x0418)

#define IRQ_MASK_H                     (REGISTERS_BASE + 0x041C)

#define IRQ_MASK_SET                   (REGISTERS_BASE + 0x0420)

#define IRQ_MASK_SET_L                 (REGISTERS_BASE + 0x0420)

#define IRQ_MASK_SET_H                 (REGISTERS_BASE + 0x0424)

#define IRQ_MASK_CLR                   (REGISTERS_BASE + 0x0428)

#define IRQ_MASK_CLR_L                 (REGISTERS_BASE + 0x0428)

#define IRQ_MASK_CLR_H                 (REGISTERS_BASE + 0x042C)

#define ECPU_MASK                      (REGISTERS_BASE + 0x0448)

#define FIQ_STS_L                      (REGISTERS_BASE + 0x044C)

#define FIQ_STS_H                      (REGISTERS_BASE + 0x0450)

#define IRQ_STS_L                      (REGISTERS_BASE + 0x0454)

#define IRQ_STS_H                      (REGISTERS_BASE + 0x0458)

#define INT_STS_ND                     (REGISTERS_BASE + 0x0464)

#define INT_STS_RAW_L                  (REGISTERS_BASE + 0x0464)

#define INT_STS_RAW_H                  (REGISTERS_BASE + 0x0468)

#define INT_STS_CLR                    (REGISTERS_BASE + 0x04B4)

#define INT_STS_CLR_L                  (REGISTERS_BASE + 0x04B4)

#define INT_STS_CLR_H                  (REGISTERS_BASE + 0x04B8)

#define INT_ACK                        (REGISTERS_BASE + 0x046C)

#define INT_ACK_L                      (REGISTERS_BASE + 0x046C)

#define INT_ACK_H                      (REGISTERS_BASE + 0x0470)

#define INT_TRIG                       (REGISTERS_BASE + 0x0474)

#define INT_TRIG_L                     (REGISTERS_BASE + 0x0474)

#define INT_TRIG_H                     (REGISTERS_BASE + 0x0478)

#define HOST_STS_L                     (REGISTERS_BASE + 0x045C)

#define HOST_STS_H                     (REGISTERS_BASE + 0x0460)

#define HOST_MASK                      (REGISTERS_BASE + 0x0430)

#define HOST_MASK_L                    (REGISTERS_BASE + 0x0430)

#define HOST_MASK_H                    (REGISTERS_BASE + 0x0434)

#define HOST_MASK_SET                  (REGISTERS_BASE + 0x0438)

#define HOST_MASK_SET_L                (REGISTERS_BASE + 0x0438)

#define HOST_MASK_SET_H                (REGISTERS_BASE + 0x043C)

#define HOST_MASK_CLR                  (REGISTERS_BASE + 0x0440)

#define HOST_MASK_CLR_L                (REGISTERS_BASE + 0x0440)

#define HOST_MASK_CLR_H                (REGISTERS_BASE + 0x0444)

/* GPIO Interrupts*/

#define GPIO_INT_STS                   (REGISTERS_BASE + 0x0484) /* 22 GPIOs*/

#define GPIO_INT_ACK                   (REGISTERS_BASE + 0x047C)

#define GPIO_INT_MASK                  (REGISTERS_BASE + 0x0480)

#define GPIO_POS_MASK                  (REGISTERS_BASE + 0x04BC) /* New*/

#define GPIO_NEG_MASK                  (REGISTERS_BASE + 0x04C0) /* New*/

/* Protocol Interrupts*/

#define PROTO_INT_STS                  (REGISTERS_BASE + 0x0490) /* Add 2 PHY->MAC source interrupts*/

#define PROTO_INT_ACK                  (REGISTERS_BASE + 0x0488)

#define PROTO_INT_MASK                 (REGISTERS_BASE + 0x048C)

/* Host Interrupts - The following Addresses are for 1273 */

#define HINT_MASK                      (REGISTERS_BASE + 0x04DC)

#define HINT_MASK_SET                  (REGISTERS_BASE + 0x04E0)

#define HINT_MASK_CLR                  (REGISTERS_BASE + 0x04E4)

#define HINT_STS_ND_MASKED             (REGISTERS_BASE + 0x04EC)

#define HINT_STS_ND  		           (REGISTERS_BASE + 0x04E8)	/* 1150 spec calls this HINT_STS_RAW*/

#define HINT_STS_CLR                   (REGISTERS_BASE + 0x04F8)

#define HINT_ACK                       (REGISTERS_BASE + 0x04F0)

#define HINT_TRIG                      (REGISTERS_BASE + 0x04F4)

/* Clock registers*/

#define CLK_CFG                        (REGISTERS_BASE + 0x0C00) /* new ARM clock bit */

#define CLK_CTRL                       (REGISTERS_BASE + 0x0C04) /* changed*/

#define BLK_RST                        (REGISTERS_BASE + 0x0C08) /* changed*/

#define CFG_USEC_STB                   (REGISTERS_BASE + 0x0C0C)

#define ARM_GATE_CLK_REG               (REGISTERS_BASE + 0x0C10) /* new*/

#define BUSY_STAT_REG                  (REGISTERS_BASE + 0x0C14) /* new*/

#define CFG_PHY_CLK88                  (REGISTERS_BASE + 0x0C18)

#define DYNAMIC_CLKGATE                (REGISTERS_BASE + 0x0C1C) /* new*/

/* AES registers*/

/* Major changes to this module*/

#define AES_START                      (REGISTERS_BASE + 0x1400)

#define AES_CFG                        (REGISTERS_BASE + 0x1404)

#define AES_CTL                        (REGISTERS_BASE + 0x1408)

#define AES_STATUS                     (REGISTERS_BASE + 0x140C)

#define AES_LENGTH                     (REGISTERS_BASE + 0x1410)

#define AES_RD_ADDR                    (REGISTERS_BASE + 0x1414)

#define AES_RD_OFFSET                  (REGISTERS_BASE + 0x1418)

#define AES_WR_ADDR                    (REGISTERS_BASE + 0x141C)

#define AES_WR_OFFSET                  (REGISTERS_BASE + 0x1420)

#define AES_CUR_RD_PTR                 (REGISTERS_BASE + 0x1424)

#define AES_CUR_WR_PTR                 (REGISTERS_BASE + 0x1428)

#define AES_KEY_0                      (REGISTERS_BASE + 0x142C)

#define AES_KEY_1                      (REGISTERS_BASE + 0x1430)

#define AES_KEY_2                      (REGISTERS_BASE + 0x1434)

#define AES_KEY_3                      (REGISTERS_BASE + 0x1438)

#define AES_NONCE_0                    (REGISTERS_BASE + 0x143C)

#define AES_NONCE_1                    (REGISTERS_BASE + 0x1440)

#define AES_NONCE_2                    (REGISTERS_BASE + 0x1444)

#define AES_NONCE_3                    (REGISTERS_BASE + 0x1448)

#define AES_MIC_0                      (REGISTERS_BASE + 0x144C)

#define AES_MIC_1                      (REGISTERS_BASE + 0x1450)

#define AES_MIC_2                      (REGISTERS_BASE + 0x1454)

#define AES_MIC_3                      (REGISTERS_BASE + 0x1458)

#define AES_ASSO_DATA_0                (REGISTERS_BASE + 0x145C)

#define AES_ASSO_DATA_1                (REGISTERS_BASE + 0x1460)

#define AES_ASSO_DATA_2                (REGISTERS_BASE + 0x1464)

#define AES_ASSO_DATA_3                (REGISTERS_BASE + 0x1468)

#define AES_NUM_OF_ROUNDS              (REGISTERS_BASE + 0x146C)

#define AES_TX_QUEUE_PTR               (REGISTERS_BASE + 0x1470)

#define AES_RX_QUEUE_PTR               (REGISTERS_BASE + 0x1474)

#define AES_STACK                      (REGISTERS_BASE + 0x1478)

#define AES_INT_RAW                    (REGISTERS_BASE + 0x147C)

#define AES_INT_MASK                   (REGISTERS_BASE + 0x1480)

#define AES_INT_STS                    (REGISTERS_BASE + 0x1484)

/* WEP registers*/

/* Order was changed*/

#define DEC_CTL                        (REGISTERS_BASE + 0x1800)

#define DEC_STATUS                     (REGISTERS_BASE + 0x1804)

#define DEC_MBLK                       (REGISTERS_BASE + 0x1808)

#define DEC_KEY_ADDR                   (REGISTERS_BASE + 0x180C)

#define DEC_KEY_LEN                    (REGISTERS_BASE + 0x1810)

#define DEC_ADDR_UPPER_BYTE            (REGISTERS_BASE + 0x1814) /* new*/

#define DEC_LEN                        (REGISTERS_BASE + 0x1818)

#define DEC_OFFSET                     (REGISTERS_BASE + 0x181C)

#define DEC_WR_MBLK                    (REGISTERS_BASE + 0x1820)

#define DEC_WR_OFFSET                  (REGISTERS_BASE + 0x1824)

/* TKIP MICHAEL reisters*/

/* order changed*/

#define MCHL_START0                    (REGISTERS_BASE + 0x1C00)

#define MCHL_DMV_START_MBLK0           (REGISTERS_BASE + 0x1C04) /* Changed to 23:5 format*/

#define MCHL_DMV_CUR_MBLK0             (REGISTERS_BASE + 0x1C10)

#define MCHL_DMV_OFFSET0               (REGISTERS_BASE + 0x1C08)

#define MCHL_DMV_LENGTH0               (REGISTERS_BASE + 0x1C0C)

#define MCHL_DMV_CFG0                  (REGISTERS_BASE + 0x1C14)

#define MCHL_KEY_L0                    (REGISTERS_BASE + 0x1C18)

#define MCHL_KEY_H0                    (REGISTERS_BASE + 0x1C1C)

#define MCHL_MIC_L0                    (REGISTERS_BASE + 0x1C20)

#define MCHL_MIC_H0                    (REGISTERS_BASE + 0x1C24)

#define MCHL_START1                    (REGISTERS_BASE + 0x1C28)

#define MCHL_DMV_START_MBLK1           (REGISTERS_BASE + 0x1C2C) /* Changed to 23:5 format*/

#define MCHL_DMV_CUR_MBLK1             (REGISTERS_BASE + 0x1C38)

#define MCHL_DMV_OFFSET1               (REGISTERS_BASE + 0x1C30)

#define MCHL_DMV_LENGTH1               (REGISTERS_BASE + 0x1C34)

#define MCHL_DMV_CFG1                  (REGISTERS_BASE + 0x1C3C)

#define MCHL_KEY_L1                    (REGISTERS_BASE + 0x1C40)

#define MCHL_KEY_H1                    (REGISTERS_BASE + 0x1C44)

#define MCHL_MIC_L1                    (REGISTERS_BASE + 0x1C48)

#define MCHL_MIC_H1                    (REGISTERS_BASE + 0x1C4C)

#define MCHL_CTL0                      (REGISTERS_BASE + 0x1C50) /* new name MCHL_CTRL0*/

#define MCHL_CTL1                      (REGISTERS_BASE + 0x1C54) /* new name MCHL_CTRL1*/

#define MCHL_UPPER_BYTE_ADDR0          (REGISTERS_BASE + 0x1C58) /* new*/

#define MCHL_UPPER_BYTE_ADDR1          (REGISTERS_BASE + 0x1C5C) /* new*/

/* SEEPROM registers*/

#define EE_CFG                         (REGISTERS_BASE + 0x0820)

#define EE_CTL                         (REGISTERS_BASE + 0x2000)

#define EE_DATA                        (REGISTERS_BASE + 0x2004)

#define EE_ADDR                        (REGISTERS_BASE + 0x2008)

/* Parallel Host (PCI/CARDBUS/PCMCIA/GS*/

#define CIS_LADDR                      (REGISTERS_BASE + 0x2400)

#define HI_CTL                         (REGISTERS_BASE + 0x2404)

#define LPWR_MGT                       (REGISTERS_BASE + 0x2408)

/*#define PDR0                         (REGISTERS_BASE + 0x04ec)*/

/*#define PDR1                         (REGISTERS_BASE + 0x04f0)*/

/*#define PDR2                         (REGISTERS_BASE + 0x04f4)*/

/*#define PDR3                         (REGISTERS_BASE + 0x04f8)*/

/*#define BAR2_ENABLE                  (REGISTERS_BASE + 0x04fc)*/

/*#define BAR2_TRANS                   (REGISTERS_BASE + 0x0500)*/

/*#define BAR2_MASK                    (REGISTERS_BASE + 0x0504)*/

#define PCI_MEM_SIZE1                  (REGISTERS_BASE + 0x2428)

#define PCI_MEM_OFFSET1                (REGISTERS_BASE + 0x242C)

#define PCI_MEM_OFFSET2                (REGISTERS_BASE + 0x2430)

/*#define PCI_IO_SIZE1                 (REGISTERS_BASE + 0x0514)*/

/*#define PCI_IO_OFFSET1               (REGISTERS_BASE + 0x0518)*/

/*#define PCI_IO_OFFSET2               (REGISTERS_BASE + 0x051c)*/

/*#define PCI_CFG_OFFSET               (REGISTERS_BASE + 0x0520)*/

#define PCMCIA_CFG                     (REGISTERS_BASE + 0x2444)

#define PCMCIA_CTL                     (REGISTERS_BASE + 0x2448)

#define PCMCIA_CFG2                    (REGISTERS_BASE + 0x244C) /* new*/

#define SRAM_PAGE                      (REGISTERS_BASE + 0x2450)

#define CFG_PULLUPDN                   (REGISTERS_BASE + 0x2454)

#define CIS_MAP                        (REGISTERS_BASE + 0x2458) /* new*/

#define ENDIAN_CTRL                    (REGISTERS_BASE + 0x245C) /* new*/

#define GS_SLEEP_ACCESS                (REGISTERS_BASE + 0x2480) /* new*/

#define PCMCIA_PWR_DN                  (REGISTERS_BASE + 0x04C4) 

#define PCI_OUTPUT_DLY_CFG             (REGISTERS_BASE + 0x2464) /* new*/

/* VLYNQ registers*/

/* VLYNQ2 was removed from hardware*/

#define VL1_REV_ID                     (REGISTERS_BASE + 0x8000) /* VLYNQ_REVISION*/

#define VL1_CTL                        (REGISTERS_BASE + 0x8004) /* VLYNQ_ CONTROL*/

#define VL1_STS                        (REGISTERS_BASE + 0x8008) /* VLYNQ_STATUS*/

#define VLYNQ_INTVEC                   (REGISTERS_BASE + 0x800C)

#define VL1_INT_STS                    (REGISTERS_BASE + 0x8010) /* VLYNQ_INTCR*/

#define VL1_INT_PEND                   (REGISTERS_BASE + 0x8014) /* VLYNQ_INTSR*/

#define VL1_INT_PTR                    (REGISTERS_BASE + 0x8018) /* VLYNQ_INTPTR*/

#define VL1_TX_ADDR                    (REGISTERS_BASE + 0x801C) /* VLYNQ_TX_MAP_ADDR*/

#define VL1_RX_SIZE1                   (REGISTERS_BASE + 0x8020) /* VLYNQ_RX_MAP_SIZE1*/

#define VL1_RX_OFF1                    (REGISTERS_BASE + 0x8024) /* VLYNQ_RX_MAP_OFFSET1*/

#define VL1_RX_SIZE2                   (REGISTERS_BASE + 0x8028) /* VLYNQ_RX_MAP_SIZE2*/

#define VL1_RX_OFF2                    (REGISTERS_BASE + 0x802C) /* VLYNQ_RX_MAP_OFFSET2*/

#define VL1_RX_SIZE3                   (REGISTERS_BASE + 0x8030) /* VLYNQ_RX_MAP_SIZE3*/

#define VL1_RX_OFF3                    (REGISTERS_BASE + 0x8034) /* VLYNQ_RX_MAP_OFFSET3*/

#define VL1_RX_SIZE4                   (REGISTERS_BASE + 0x8038) /* VLYNQ_RX_MAP_SIZE4*/

#define VL1_RX_OFF4                    (REGISTERS_BASE + 0x803C) /* VLYNQ_RX_MAP_OFFSET4*/

#define VL1_CHIP_VER                   (REGISTERS_BASE + 0x8040) /* VLYNQ_CHIP_VER*/

#define VLYNQ_AUTONEG                  (REGISTERS_BASE + 0x8044)

#define VLYNQ_MANNEG                   (REGISTERS_BASE + 0x8048)

#define VLYNQ_NEGSTAT                  (REGISTERS_BASE + 0x804C)

#define VLYNQ_ENDIAN                   (REGISTERS_BASE + 0x805C)

#define VL1_INT_VEC3_0                 (REGISTERS_BASE + 0x8060) /* VLYNQ_HW_INT3TO0_CFG*/

#define VL1_INT_VEC7_4                 (REGISTERS_BASE + 0x8064) /* VLYNQ_HW_INT7TO4_CFG*/

/* VLYNQ Remote configuration registers*/

#define VL1_REM_REV_ID                 (REGISTERS_BASE + 0x8080) /* VLYNQ_REM_REVISION*/

#define VL1_REM_CTL                    (REGISTERS_BASE + 0x8084) /* VLYNQ_REM_ CONTROL*/

#define VL1_REM_STS                    (REGISTERS_BASE + 0x8088) /* VLYNQ_REM_STATUS*/

#define VLYNQ_REM_INTVEC               (REGISTERS_BASE + 0x808C)

#define VL1_REM_INT_STS                (REGISTERS_BASE + 0x8090) /* VLYNQ_REM_INTCR*/

#define VL1_REM_INT_PEND               (REGISTERS_BASE + 0x8094) /* VLYNQ_REM_INTSR*/

#define VL1_REM_INT_PTR                (REGISTERS_BASE + 0x8098) /* VLYNQ_REM_INTPTR*/

#define VL1_REM_TX_ADDR                (REGISTERS_BASE + 0x809C) /* VLYNQ_REM_TX_MAP_ADDR*/

#define VL1_REM_RX_SIZE1               (REGISTERS_BASE + 0x80A0) /* VLYNQ_REM_RX_MAP_SIZE1*/

#define VL1_REM_RX_OFF1                (REGISTERS_BASE + 0x80A4) /* VLYNQ_REM_RX_MAP_OFFSET1*/

#define VL1_REM_RX_SIZE2               (REGISTERS_BASE + 0x80A8) /* VLYNQ_REM_RX_MAP_SIZE2*/

#define VL1_REM_RX_OFF2                (REGISTERS_BASE + 0x80AC) /* VLYNQ_REM_RX_MAP_OFFSET2*/

#define VL1_REM_RX_SIZE3               (REGISTERS_BASE + 0x80B0) /* VLYNQ_REM_RX_MAP_SIZE3*/

#define VL1_REM_RX_OFF3                (REGISTERS_BASE + 0x80B4) /* VLYNQ_REM_RX_MAP_OFFSET3*/

#define VL1_REM_RX_SIZE4               (REGISTERS_BASE + 0x80B8) /* VLYNQ_REM_RX_MAP_SIZE4*/

#define VL1_REM_RX_OFF4                (REGISTERS_BASE + 0x80BC) /* VLYNQ_REM_RX_MAP_OFFSET4*/

#define VL1_REM_CHIP_VER               (REGISTERS_BASE + 0x80C0) /* VLYNQ_REM_CHIP_VER*/

#define VLYNQ_REM_AUTONEG              (REGISTERS_BASE + 0x80C4)

#define VLYNQ_REM_MANNEG               (REGISTERS_BASE + 0x80C8)

#define VLYNQ_REM_NEGSTAT              (REGISTERS_BASE + 0x80CC)

#define VLYNQ_REM_ENDIAN               (REGISTERS_BASE + 0x80DC)

#define VL1_REM_INT_VEC3_0             (REGISTERS_BASE + 0x80E0) /* VLYNQ_REM_HW_INT3TO0_CFG*/

#define VL1_REM_INT_VEC7_4             (REGISTERS_BASE + 0x80E4) /* VLYNQ_REM_HW_INT7TO4_CFG*/

/* PCIIF*/

/**/

#define PCI_ID_REG                     (REGISTERS_BASE + 0x8400)

#define PCI_STATUS_SET_REG             (REGISTERS_BASE + 0x8410)

#define PCI_STATUS_CLR_REG             (REGISTERS_BASE + 0x8414)

#define PCI_HIMASK_SET_REG             (REGISTERS_BASE + 0x8420)

#define PCI_HIMASK_CLR_REG             (REGISTERS_BASE + 0x8424)

#define PCI_AMASK_SET_REG              (REGISTERS_BASE + 0x8430)

#define PCI_AMASK_CLR_REG              (REGISTERS_BASE + 0x8434)

#define PCI_CLKRUN_REG                 (REGISTERS_BASE + 0x8438)

#define PCI_BE_VENDOR_ID_REG           (REGISTERS_BASE + 0x8500)

#define PCI_BE_COMMAND_REG             (REGISTERS_BASE + 0x8504)

#define PCI_BE_REVISION_REG            (REGISTERS_BASE + 0x8508)

#define PCI_BE_CL_SIZE_REG             (REGISTERS_BASE + 0x850C)

#define PCI_BE_BAR0_MASK_REG           (REGISTERS_BASE + 0x8510)

#define PCI_BE_BAR1_MASK_REG           (REGISTERS_BASE + 0x8514)

#define PCI_BE_BAR2_MASK_REG           (REGISTERS_BASE + 0x8518)

#define PCI_BE_BAR3_MASK_REG           (REGISTERS_BASE + 0x851C)

#define PCI_BE_CIS_PTR_REG             (REGISTERS_BASE + 0x8528)

#define PCI_BE_SUBSYS_ID_REG           (REGISTERS_BASE + 0x852C)

#define PCI_BE_CAP_PTR_REG             (REGISTERS_BASE + 0x8534)

#define PCI_BE_INTR_LINE_REG           (REGISTERS_BASE + 0x853C)

#define PCI_BE_PM_CAP_REG              (REGISTERS_BASE + 0x8540)

#define PCI_BE_PM_CTRL_REG             (REGISTERS_BASE + 0x8544)

#define PCI_BE_PM_D0_CTRL_REG          (REGISTERS_BASE + 0x8560)

#define PCI_BE_PM_D1_CTRL_REG          (REGISTERS_BASE + 0x8564)

#define PCI_BE_PM_D2_CTRL_REG          (REGISTERS_BASE + 0x8568)

#define PCI_BE_PM_D3_CTRL_REG          (REGISTERS_BASE + 0x856C)

#define PCI_BE_SLV_CFG_REG             (REGISTERS_BASE + 0x8580)

#define PCI_BE_ARB_CTRL_REG            (REGISTERS_BASE + 0x8584)

#define FER                            (REGISTERS_BASE + 0x85A0) /* PCI_BE_STSCHG_FE_REG*/

#define FEMR                           (REGISTERS_BASE + 0x85A4) /* PCI_BE_STSCHG_FEM_REG*/

#define FPSR                           (REGISTERS_BASE + 0x85A8) /* PCI_BE_STSCHG_FPS_REG*/

#define FFER                           (REGISTERS_BASE + 0x85AC) /* PCI_BE_STSCHG_FFE_REG*/

#define PCI_BE_BAR0_TRANS_REG          (REGISTERS_BASE + 0x85C0)

#define PCI_BE_BAR1_TRANS_REG          (REGISTERS_BASE + 0x85C4)

#define PCI_BE_BAR2_TRANS_REG          (REGISTERS_BASE + 0x85C8)

#define PCI_BE_BAR3_TRANS_REG          (REGISTERS_BASE + 0x85CC)

#define PCI_BE_BAR4_TRANS_REG          (REGISTERS_BASE + 0x85D0)

#define PCI_BE_BAR5_TRANS_REG          (REGISTERS_BASE + 0x85D4)

#define PCI_BE_BAR0_REG                (REGISTERS_BASE + 0x85E0)

#define PCI_BE_BAR1_REG                (REGISTERS_BASE + 0x85E4)

#define PCI_BE_BAR2_REG                (REGISTERS_BASE + 0x85E8)

#define PCI_BE_BAR3_REG                (REGISTERS_BASE + 0x85EC)

#define PCI_PROXY_DATA                 (REGISTERS_BASE + 0x8700)

#define PCI_PROXY_ADDR                 (REGISTERS_BASE + 0x8704)

#define PCI_PROXY_CMD                  (REGISTERS_BASE + 0x8708)

#define PCI_CONTROL                    (REGISTERS_BASE + 0x8710)

/* USB1.1 registers*/

/**/

#define USB_STS_CLR                    (REGISTERS_BASE + 0x4000)

#define USB_STS_ND                     (REGISTERS_BASE + 0x4004)

#define USB_INT_ACK                    (REGISTERS_BASE + 0x4008)

#define USB_MASK                       (REGISTERS_BASE + 0x400c)

#define USB_MASK_SET                   (REGISTERS_BASE + 0x4010)

#define USB_MASK_CLR                   (REGISTERS_BASE + 0x4014)

#define USB_WU                         (REGISTERS_BASE + 0x4018)

#define USB_EP0_OUT_PTR                (REGISTERS_BASE + 0x401c)

#define USB_EP0_OUT_VLD                (REGISTERS_BASE + 0x4020)

#define USB_EP0_OUT_LEN                (REGISTERS_BASE + 0x4024)

#define USB_EP0_IN_PTR                 (REGISTERS_BASE + 0x4028)

#define USB_EP0_IN_VLD                 (REGISTERS_BASE + 0x402c)

#define USB_EP0_IN_LEN                 (REGISTERS_BASE + 0x4030)

#define USB_EP1_CFG                    (REGISTERS_BASE + 0x4034)

#define USB_EP1_OUT_INT_CFG            (REGISTERS_BASE + 0x4038)

#define USB_EP1_OUT_PTR                (REGISTERS_BASE + 0x403c)

#define USB_EP1_OUT_VLD                (REGISTERS_BASE + 0x4040)

#define USB_EP1_OUT_CUR_MBLK           (REGISTERS_BASE + 0x4044)

#define USB_EP1_OUT_LEN                (REGISTERS_BASE + 0x4048)

#define USB_EP1_IN_START_MBLK          (REGISTERS_BASE + 0x404c)

#define USB_EP1_IN_LAST_MBLK           (REGISTERS_BASE + 0x4050)

#define USB_EP1_IN_VLD                 (REGISTERS_BASE + 0x4054)

#define USB_EP2_PTR                    (REGISTERS_BASE + 0x405c)

#define USB_EP2_VLD                    (REGISTERS_BASE + 0x4060)

#define USB_EP2_LEN                    (REGISTERS_BASE + 0x4064)

#define USB_EP3_OUT_PTR0               (REGISTERS_BASE + 0x4068)

#define USB_EP3_OUT_VLD0               (REGISTERS_BASE + 0x406c)

#define USB_EP3_OUT_LEN0               (REGISTERS_BASE + 0x4070)

#define USB_EP3_OUT_PTR1               (REGISTERS_BASE + 0x4074)

#define USB_EP3_OUT_VLD1               (REGISTERS_BASE + 0x4078)

#define USB_EP3_OUT_LEN1               (REGISTERS_BASE + 0x407c)

#define USB_EP3_IN_PTR0                (REGISTERS_BASE + 0x4080)

#define USB_EP3_IN_VLD0                (REGISTERS_BASE + 0x4084)

#define USB_EP3_IN_LEN0                (REGISTERS_BASE + 0x4088)

#define USB_EP3_IN_PTR1                (REGISTERS_BASE + 0x408c)

#define USB_EP3_IN_VLD1                (REGISTERS_BASE + 0x4090)

#define USB_EP3_IN_LEN1                (REGISTERS_BASE + 0x4094)

#define USB_EP1_OUT_END_MBLK           (REGISTERS_BASE + 0x4098)

#define USB_EP0_OUT_SETUP              (REGISTERS_BASE + 0x409c)

#define USB_EP0_STALL                  (REGISTERS_BASE + 0x40a0)

#define USB_EP1_IN_OFFSET              (REGISTERS_BASE + 0x40a4)

/* Device Configuration registers*/

#define SOR_CFG                        (REGISTERS_BASE + 0x0800)

#define ECPU_CTRL                      (REGISTERS_BASE + 0x0804)

#define HI_CFG                         (REGISTERS_BASE + 0x0808)

#define EE_START                       (REGISTERS_BASE + 0x080C)

/* IO Control registers*/

#define SERIAL_HOST_IOCFG0             (REGISTERS_BASE + 0x0894) /* new*/

#define SERIAL_HOST_IOCFG1             (REGISTERS_BASE + 0x0898) /* new*/

#define SERIAL_HOST_IOCFG2             (REGISTERS_BASE + 0x089C) /* new*/

#define SERIAL_HOST_IOCFG3             (REGISTERS_BASE + 0x08A0) /* new*/

#define GPIO_IOCFG0                    (REGISTERS_BASE + 0x08F4) /* new*/

#define GPIO_IOCFG1                    (REGISTERS_BASE + 0x08F8) /* new*/

#define GPIO_IOCFG2                    (REGISTERS_BASE + 0x08FC) /* new*/

#define GPIO_IOCFG3                    (REGISTERS_BASE + 0x0900) /* new*/

#define CHIP_ID_B                      (REGISTERS_BASE + 0x5674) /* new*/

#define CHIP_ID                        CHIP_ID_B/* Leave for TNETW compatability*/

#define CHIP_ID_1273_PG10              (0x04030101)