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/*
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* Device1273.h
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*
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* Copyright(c) 1998 - 2010 Texas Instruments. All rights reserved.
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* All rights reserved.
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*
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* This program and the accompanying materials are made available under the
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* terms of the Eclipse Public License v1.0 or BSD License which accompanies
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* this distribution. The Eclipse Public License is available at
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* http://www.eclipse.org/legal/epl-v10.html and the BSD License is as below.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Texas Instruments nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**********************************************************************************************************************
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FILENAME: Device1273.h
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DESCRIPTION: TNETW1273 Registes addresses/defintion
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***********************************************************************************************************************/
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#ifndef DEVICE1273_H
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#define DEVICE1273_H
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/* Base addresses*/
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/* They are not used inside registers definition in purpose to allow this header file*/
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/* to be used as an easy reference to register -> address date base. Keep this as it*/
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/* is very powerful for debugging purpose.*/
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#define REGISTERS_BASE 0x00300000
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#define INT_BASE 0x00300400
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#define REG_CONFIG_BASE 0x00300800
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#define CLK_BASE 0x00300C00
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#define SDMA_BASE 0x00301000
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#define AES_BASE 0x00301400
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#define WEP_BASE 0x00301800
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#define TKIP_BASE 0x00301C00
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#define SEEPROM_BASE 0x00302000
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#define PAR_HOST_BASE 0x00302400
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#define SDIO_BASE 0x00302800
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#define UART_BASE 0x00302C00
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#define USB11_BASE 0x00304000
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#define LDMA_BASE 0x00304400
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#define RX_BASE 0x00304800
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#define ACCESS_BASE 0x00304c00
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#define TX_BASE 0x00305000
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#define RMAC_CSR_BASE 0x00305400
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#define AFE_PM 0x00305800
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#define VLYNQ_BASE 0x00308000
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#define PCI_BASE 0x00308400
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#define USB20_BASE 0x0030A000
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#define DRPW_BASE 0x00310000
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#define PHY_BASE 0x003C0000
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/* DRPw init scratch register */
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#define DRPW_SCRATCH_START (DRPW_BASE + 0x002C)
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/* System DMA registers*/
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/* Order of registers was changed*/
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#define DMA_GLB_CFG (REGISTERS_BASE + 0x1000)
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#define DMA_HDESC_OFFSET (REGISTERS_BASE + 0x1004)
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#define DMA_HDATA_OFFSET (REGISTERS_BASE + 0x1008)
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#define DMA_CFG0 (REGISTERS_BASE + 0x100C) /* SDMA_HOST_CFG0 changed*/
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#define DMA_CTL0 (REGISTERS_BASE + 0x1010) /* SDMA_CTRL0 changed*/
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#define DMA_LENGTH0 (REGISTERS_BASE + 0x1014)
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#define DMA_L_ADDR0 (REGISTERS_BASE + 0x1018) /* SDMA_RD_ADDR ?*/
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#define DMA_L_PTR0 (REGISTERS_BASE + 0x101C) /* SDMA_RD_OFFSET ?*/
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#define DMA_H_ADDR0 (REGISTERS_BASE + 0x1020) /* SDMA_WR_ADDR ?*/
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#define DMA_H_PTR0 (REGISTERS_BASE + 0x1024) /* SDMA_WR_OFFSET ?*/
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#define DMA_STS0 (REGISTERS_BASE + 0x1028) /* Changed*/
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#define DMA_CFG1 (REGISTERS_BASE + 0x1030) /* SDMA_HOST_CFG1 changed*/
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#define DMA_CTL1 (REGISTERS_BASE + 0x1034) /* SDMA_CTRL1 changed*/
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#define DMA_LENGTH1 (REGISTERS_BASE + 0x1038)
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#define DMA_L_ADDR1 (REGISTERS_BASE + 0x103C)
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#define DMA_L_PTR1 (REGISTERS_BASE + 0x1040)
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#define DMA_H_ADDR1 (REGISTERS_BASE + 0x1044)
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#define DMA_H_PTR1 (REGISTERS_BASE + 0x1048)
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#define DMA_STS1 (REGISTERS_BASE + 0x104C)
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#define DMA_HFRM_PTR (REGISTERS_BASE + 0x1050) /* New ?*/
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#define DMA_DEBUG (REGISTERS_BASE + 0x1054) /* Changed*/
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/* Local DMA registers*/
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/* number changed from 4 to 2*/
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#define LDMA_DEBUG (REGISTERS_BASE + 0x4400)
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#define LDMA_CTL0 (REGISTERS_BASE + 0x4404) /* Add 2 bits to support fix address (FIFO)*/
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#define LDMA_STATUS0 (REGISTERS_BASE + 0x4408)
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#define LDMA_LENGTH0 (REGISTERS_BASE + 0x440c)
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#define LDMA_RD_ADDR0 (REGISTERS_BASE + 0x4410)
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#define LDMA_RD_OFFSET0 (REGISTERS_BASE + 0x4414)
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#define LDMA_WR_ADDR0 (REGISTERS_BASE + 0x4418)
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#define LDMA_WR_OFFSET0 (REGISTERS_BASE + 0x441c)
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#define LDMA_CTL1 (REGISTERS_BASE + 0x4428) /* Add 2 bits to support fix address (FIFO)*/
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#define LDMA_STATUS1 (REGISTERS_BASE + 0x442c)
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#define LDMA_LENGTH1 (REGISTERS_BASE + 0x4430)
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#define LDMA_RD_ADDR1 (REGISTERS_BASE + 0x4434)
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#define LDMA_RD_OFFSET1 (REGISTERS_BASE + 0x4438)
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#define LDMA_WR_ADDR1 (REGISTERS_BASE + 0x443c)
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#define LDMA_WR_OFFSET1 (REGISTERS_BASE + 0x4440)
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/* For TNETW compatability (if willbe )*/
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#define LDMA_CUR_RD_PTR0 LDMA_RD_ADDR0
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#define LDMA_CUR_WR_PTR0 LDMA_WR_ADDR0
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#define LDMA_CUR_RD_PTR1 LDMA_RD_ADDR1
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#define LDMA_CUR_WR_PTR1 LDMA_WR_ADDR1
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/* Host Slave registers*/
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#define SLV_SOFT_RESET (REGISTERS_BASE + 0x0000) /* self clearing*/
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#define SLV_REG_ADDR (REGISTERS_BASE + 0x0004)
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#define SLV_REG_DATA (REGISTERS_BASE + 0x0008)
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#define SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
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#define SLV_MEM_CP (REGISTERS_BASE + 0x0010)
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#define SLV_MEM_ADDR (REGISTERS_BASE + 0x0014)
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#define SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
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#define SLV_MEM_QOS_DATA (REGISTERS_BASE + 0x001A)
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#define SLV_MEM_CTL (REGISTERS_BASE + 0x001c) /* bit 19 moved to PCMCIA_CTL*/
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#define SLV_END_CTL (REGISTERS_BASE + 0x0020) /* 2 bits moved to ENDIAN_CTL*/
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/* Timer registers*/
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/* Timer1/2 count MAC clocks*/
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/* Timer3/4/5 count usec*/
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#define TIM1_CTRL (REGISTERS_BASE + 0x0918)
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#define TIM1_LOAD (REGISTERS_BASE + 0x091C)
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#define TIM1_CNT (REGISTERS_BASE + 0x0920)
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#define TIM2_CTRL (REGISTERS_BASE + 0x0924)
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#define TIM2_LOAD (REGISTERS_BASE + 0x0928)
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#define TIM2_CNT (REGISTERS_BASE + 0x092C)
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#define TIM3_CTRL (REGISTERS_BASE + 0x0930)
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#define TIM3_LOAD (REGISTERS_BASE + 0x0934)
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#define TIM3_CNT (REGISTERS_BASE + 0x0938)
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#define TIM4_CTRL (REGISTERS_BASE + 0x093C)
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#define TIM4_LOAD (REGISTERS_BASE + 0x0940)
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#define TIM4_CNT (REGISTERS_BASE + 0x0944)
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#define TIM5_CTRL (REGISTERS_BASE + 0x0948)
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#define TIM5_LOAD (REGISTERS_BASE + 0x094C)
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#define TIM5_CNT (REGISTERS_BASE + 0x0950)
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/* Watchdog registers*/
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#define WDOG_CTRL (REGISTERS_BASE + 0x0954)
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#define WDOG_LOAD (REGISTERS_BASE + 0x0958)
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#define WDOG_CNT (REGISTERS_BASE + 0x095C)
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#define WDOG_STS (REGISTERS_BASE + 0x0960)
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#define WDOG_FEED (REGISTERS_BASE + 0x0964)
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/* Interrupt registers*/
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/* 64 bit interrupt sources registers ws ced. sme interupts were removed and new ones were added*/
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/* Order was changed*/
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#define FIQ_MASK (REGISTERS_BASE + 0x0400)
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#define FIQ_MASK_L (REGISTERS_BASE + 0x0400)
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#define FIQ_MASK_H (REGISTERS_BASE + 0x0404)
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#define FIQ_MASK_SET (REGISTERS_BASE + 0x0408)
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#define FIQ_MASK_SET_L (REGISTERS_BASE + 0x0408)
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#define FIQ_MASK_SET_H (REGISTERS_BASE + 0x040C)
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#define FIQ_MASK_CLR (REGISTERS_BASE + 0x0410)
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#define FIQ_MASK_CLR_L (REGISTERS_BASE + 0x0410)
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#define FIQ_MASK_CLR_H (REGISTERS_BASE + 0x0414)
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#define IRQ_MASK (REGISTERS_BASE + 0x0418)
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#define IRQ_MASK_L (REGISTERS_BASE + 0x0418)
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#define IRQ_MASK_H (REGISTERS_BASE + 0x041C)
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#define IRQ_MASK_SET (REGISTERS_BASE + 0x0420)
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#define IRQ_MASK_SET_L (REGISTERS_BASE + 0x0420)
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#define IRQ_MASK_SET_H (REGISTERS_BASE + 0x0424)
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#define IRQ_MASK_CLR (REGISTERS_BASE + 0x0428)
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#define IRQ_MASK_CLR_L (REGISTERS_BASE + 0x0428)
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#define IRQ_MASK_CLR_H (REGISTERS_BASE + 0x042C)
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#define ECPU_MASK (REGISTERS_BASE + 0x0448)
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#define FIQ_STS_L (REGISTERS_BASE + 0x044C)
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#define FIQ_STS_H (REGISTERS_BASE + 0x0450)
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#define IRQ_STS_L (REGISTERS_BASE + 0x0454)
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#define IRQ_STS_H (REGISTERS_BASE + 0x0458)
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#define INT_STS_ND (REGISTERS_BASE + 0x0464)
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#define INT_STS_RAW_L (REGISTERS_BASE + 0x0464)
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#define INT_STS_RAW_H (REGISTERS_BASE + 0x0468)
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#define INT_STS_CLR (REGISTERS_BASE + 0x04B4)
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#define INT_STS_CLR_L (REGISTERS_BASE + 0x04B4)
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#define INT_STS_CLR_H (REGISTERS_BASE + 0x04B8)
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#define INT_ACK (REGISTERS_BASE + 0x046C)
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#define INT_ACK_L (REGISTERS_BASE + 0x046C)
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#define INT_ACK_H (REGISTERS_BASE + 0x0470)
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#define INT_TRIG (REGISTERS_BASE + 0x0474)
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#define INT_TRIG_L (REGISTERS_BASE + 0x0474)
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#define INT_TRIG_H (REGISTERS_BASE + 0x0478)
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#define HOST_STS_L (REGISTERS_BASE + 0x045C)
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#define HOST_STS_H (REGISTERS_BASE + 0x0460)
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#define HOST_MASK (REGISTERS_BASE + 0x0430)
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#define HOST_MASK_L (REGISTERS_BASE + 0x0430)
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#define HOST_MASK_H (REGISTERS_BASE + 0x0434)
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#define HOST_MASK_SET (REGISTERS_BASE + 0x0438)
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#define HOST_MASK_SET_L (REGISTERS_BASE + 0x0438)
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#define HOST_MASK_SET_H (REGISTERS_BASE + 0x043C)
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#define HOST_MASK_CLR (REGISTERS_BASE + 0x0440)
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#define HOST_MASK_CLR_L (REGISTERS_BASE + 0x0440)
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#define HOST_MASK_CLR_H (REGISTERS_BASE + 0x0444)
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/* GPIO Interrupts*/
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#define GPIO_INT_STS (REGISTERS_BASE + 0x0484) /* 22 GPIOs*/
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#define GPIO_INT_ACK (REGISTERS_BASE + 0x047C)
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#define GPIO_INT_MASK (REGISTERS_BASE + 0x0480)
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#define GPIO_POS_MASK (REGISTERS_BASE + 0x04BC) /* New*/
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#define GPIO_NEG_MASK (REGISTERS_BASE + 0x04C0) /* New*/
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/* Protocol Interrupts*/
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#define PROTO_INT_STS (REGISTERS_BASE + 0x0490) /* Add 2 PHY->MAC source interrupts*/
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#define PROTO_INT_ACK (REGISTERS_BASE + 0x0488)
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#define PROTO_INT_MASK (REGISTERS_BASE + 0x048C)
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/* Host Interrupts - The following Addresses are for 1273 */
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#define HINT_MASK (REGISTERS_BASE + 0x04DC)
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#define HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
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#define HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)
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#define HINT_STS_ND_MASKED (REGISTERS_BASE + 0x04EC)
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#define HINT_STS_ND (REGISTERS_BASE + 0x04E8) /* 1150 spec calls this HINT_STS_RAW*/
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#define HINT_STS_CLR (REGISTERS_BASE + 0x04F8)
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#define HINT_ACK (REGISTERS_BASE + 0x04F0)
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#define HINT_TRIG (REGISTERS_BASE + 0x04F4)
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/* Clock registers*/
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#define CLK_CFG (REGISTERS_BASE + 0x0C00) /* new ARM clock bit */
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#define CLK_CTRL (REGISTERS_BASE + 0x0C04) /* changed*/
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#define BLK_RST (REGISTERS_BASE + 0x0C08) /* changed*/
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#define CFG_USEC_STB (REGISTERS_BASE + 0x0C0C)
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#define ARM_GATE_CLK_REG (REGISTERS_BASE + 0x0C10) /* new*/
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#define BUSY_STAT_REG (REGISTERS_BASE + 0x0C14) /* new*/
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#define CFG_PHY_CLK88 (REGISTERS_BASE + 0x0C18)
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#define DYNAMIC_CLKGATE (REGISTERS_BASE + 0x0C1C) /* new*/
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/* AES registers*/
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/* Major changes to this module*/
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#define AES_START (REGISTERS_BASE + 0x1400)
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#define AES_CFG (REGISTERS_BASE + 0x1404)
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#define AES_CTL (REGISTERS_BASE + 0x1408)
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#define AES_STATUS (REGISTERS_BASE + 0x140C)
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#define AES_LENGTH (REGISTERS_BASE + 0x1410)
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#define AES_RD_ADDR (REGISTERS_BASE + 0x1414)
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#define AES_RD_OFFSET (REGISTERS_BASE + 0x1418)
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#define AES_WR_ADDR (REGISTERS_BASE + 0x141C)
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#define AES_WR_OFFSET (REGISTERS_BASE + 0x1420)
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#define AES_CUR_RD_PTR (REGISTERS_BASE + 0x1424)
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#define AES_CUR_WR_PTR (REGISTERS_BASE + 0x1428)
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#define AES_KEY_0 (REGISTERS_BASE + 0x142C)
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#define AES_KEY_1 (REGISTERS_BASE + 0x1430)
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#define AES_KEY_2 (REGISTERS_BASE + 0x1434)
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#define AES_KEY_3 (REGISTERS_BASE + 0x1438)
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#define AES_NONCE_0 (REGISTERS_BASE + 0x143C)
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#define AES_NONCE_1 (REGISTERS_BASE + 0x1440)
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#define AES_NONCE_2 (REGISTERS_BASE + 0x1444)
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#define AES_NONCE_3 (REGISTERS_BASE + 0x1448)
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#define AES_MIC_0 (REGISTERS_BASE + 0x144C)
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#define AES_MIC_1 (REGISTERS_BASE + 0x1450)
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#define AES_MIC_2 (REGISTERS_BASE + 0x1454)
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#define AES_MIC_3 (REGISTERS_BASE + 0x1458)
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#define AES_ASSO_DATA_0 (REGISTERS_BASE + 0x145C)
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#define AES_ASSO_DATA_1 (REGISTERS_BASE + 0x1460)
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#define AES_ASSO_DATA_2 (REGISTERS_BASE + 0x1464)
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#define AES_ASSO_DATA_3 (REGISTERS_BASE + 0x1468)
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#define AES_NUM_OF_ROUNDS (REGISTERS_BASE + 0x146C)
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#define AES_TX_QUEUE_PTR (REGISTERS_BASE + 0x1470)
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#define AES_RX_QUEUE_PTR (REGISTERS_BASE + 0x1474)
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#define AES_STACK (REGISTERS_BASE + 0x1478)
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#define AES_INT_RAW (REGISTERS_BASE + 0x147C)
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#define AES_INT_MASK (REGISTERS_BASE + 0x1480)
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#define AES_INT_STS (REGISTERS_BASE + 0x1484)
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/* WEP registers*/
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/* Order was changed*/
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#define DEC_CTL (REGISTERS_BASE + 0x1800)
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#define DEC_STATUS (REGISTERS_BASE + 0x1804)
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#define DEC_MBLK (REGISTERS_BASE + 0x1808)
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#define DEC_KEY_ADDR (REGISTERS_BASE + 0x180C)
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#define DEC_KEY_LEN (REGISTERS_BASE + 0x1810)
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297 |
#define DEC_ADDR_UPPER_BYTE (REGISTERS_BASE + 0x1814) /* new*/
|
|
298 |
#define DEC_LEN (REGISTERS_BASE + 0x1818)
|
|
299 |
#define DEC_OFFSET (REGISTERS_BASE + 0x181C)
|
|
300 |
#define DEC_WR_MBLK (REGISTERS_BASE + 0x1820)
|
|
301 |
#define DEC_WR_OFFSET (REGISTERS_BASE + 0x1824)
|
|
302 |
|
|
303 |
/* TKIP MICHAEL reisters*/
|
|
304 |
/* order changed*/
|
|
305 |
#define MCHL_START0 (REGISTERS_BASE + 0x1C00)
|
|
306 |
#define MCHL_DMV_START_MBLK0 (REGISTERS_BASE + 0x1C04) /* Changed to 23:5 format*/
|
|
307 |
#define MCHL_DMV_CUR_MBLK0 (REGISTERS_BASE + 0x1C10)
|
|
308 |
#define MCHL_DMV_OFFSET0 (REGISTERS_BASE + 0x1C08)
|
|
309 |
#define MCHL_DMV_LENGTH0 (REGISTERS_BASE + 0x1C0C)
|
|
310 |
#define MCHL_DMV_CFG0 (REGISTERS_BASE + 0x1C14)
|
|
311 |
#define MCHL_KEY_L0 (REGISTERS_BASE + 0x1C18)
|
|
312 |
#define MCHL_KEY_H0 (REGISTERS_BASE + 0x1C1C)
|
|
313 |
#define MCHL_MIC_L0 (REGISTERS_BASE + 0x1C20)
|
|
314 |
#define MCHL_MIC_H0 (REGISTERS_BASE + 0x1C24)
|
|
315 |
#define MCHL_START1 (REGISTERS_BASE + 0x1C28)
|
|
316 |
#define MCHL_DMV_START_MBLK1 (REGISTERS_BASE + 0x1C2C) /* Changed to 23:5 format*/
|
|
317 |
#define MCHL_DMV_CUR_MBLK1 (REGISTERS_BASE + 0x1C38)
|
|
318 |
#define MCHL_DMV_OFFSET1 (REGISTERS_BASE + 0x1C30)
|
|
319 |
#define MCHL_DMV_LENGTH1 (REGISTERS_BASE + 0x1C34)
|
|
320 |
#define MCHL_DMV_CFG1 (REGISTERS_BASE + 0x1C3C)
|
|
321 |
#define MCHL_KEY_L1 (REGISTERS_BASE + 0x1C40)
|
|
322 |
#define MCHL_KEY_H1 (REGISTERS_BASE + 0x1C44)
|
|
323 |
#define MCHL_MIC_L1 (REGISTERS_BASE + 0x1C48)
|
|
324 |
#define MCHL_MIC_H1 (REGISTERS_BASE + 0x1C4C)
|
|
325 |
#define MCHL_CTL0 (REGISTERS_BASE + 0x1C50) /* new name MCHL_CTRL0*/
|
|
326 |
#define MCHL_CTL1 (REGISTERS_BASE + 0x1C54) /* new name MCHL_CTRL1*/
|
|
327 |
#define MCHL_UPPER_BYTE_ADDR0 (REGISTERS_BASE + 0x1C58) /* new*/
|
|
328 |
#define MCHL_UPPER_BYTE_ADDR1 (REGISTERS_BASE + 0x1C5C) /* new*/
|
|
329 |
|
|
330 |
/* SEEPROM registers*/
|
|
331 |
#define EE_CFG (REGISTERS_BASE + 0x0820)
|
|
332 |
#define EE_CTL (REGISTERS_BASE + 0x2000)
|
|
333 |
#define EE_DATA (REGISTERS_BASE + 0x2004)
|
|
334 |
#define EE_ADDR (REGISTERS_BASE + 0x2008)
|
|
335 |
|
|
336 |
/* Parallel Host (PCI/CARDBUS/PCMCIA/GS*/
|
|
337 |
#define CIS_LADDR (REGISTERS_BASE + 0x2400)
|
|
338 |
#define HI_CTL (REGISTERS_BASE + 0x2404)
|
|
339 |
#define LPWR_MGT (REGISTERS_BASE + 0x2408)
|
|
340 |
/*#define PDR0 (REGISTERS_BASE + 0x04ec)*/
|
|
341 |
/*#define PDR1 (REGISTERS_BASE + 0x04f0)*/
|
|
342 |
/*#define PDR2 (REGISTERS_BASE + 0x04f4)*/
|
|
343 |
/*#define PDR3 (REGISTERS_BASE + 0x04f8)*/
|
|
344 |
/*#define BAR2_ENABLE (REGISTERS_BASE + 0x04fc)*/
|
|
345 |
/*#define BAR2_TRANS (REGISTERS_BASE + 0x0500)*/
|
|
346 |
/*#define BAR2_MASK (REGISTERS_BASE + 0x0504)*/
|
|
347 |
#define PCI_MEM_SIZE1 (REGISTERS_BASE + 0x2428)
|
|
348 |
#define PCI_MEM_OFFSET1 (REGISTERS_BASE + 0x242C)
|
|
349 |
#define PCI_MEM_OFFSET2 (REGISTERS_BASE + 0x2430)
|
|
350 |
/*#define PCI_IO_SIZE1 (REGISTERS_BASE + 0x0514)*/
|
|
351 |
/*#define PCI_IO_OFFSET1 (REGISTERS_BASE + 0x0518)*/
|
|
352 |
/*#define PCI_IO_OFFSET2 (REGISTERS_BASE + 0x051c)*/
|
|
353 |
/*#define PCI_CFG_OFFSET (REGISTERS_BASE + 0x0520)*/
|
|
354 |
#define PCMCIA_CFG (REGISTERS_BASE + 0x2444)
|
|
355 |
#define PCMCIA_CTL (REGISTERS_BASE + 0x2448)
|
|
356 |
#define PCMCIA_CFG2 (REGISTERS_BASE + 0x244C) /* new*/
|
|
357 |
#define SRAM_PAGE (REGISTERS_BASE + 0x2450)
|
|
358 |
#define CFG_PULLUPDN (REGISTERS_BASE + 0x2454)
|
|
359 |
#define CIS_MAP (REGISTERS_BASE + 0x2458) /* new*/
|
|
360 |
#define ENDIAN_CTRL (REGISTERS_BASE + 0x245C) /* new*/
|
|
361 |
#define GS_SLEEP_ACCESS (REGISTERS_BASE + 0x2480) /* new*/
|
|
362 |
#define PCMCIA_PWR_DN (REGISTERS_BASE + 0x04C4)
|
|
363 |
#define PCI_OUTPUT_DLY_CFG (REGISTERS_BASE + 0x2464) /* new*/
|
|
364 |
|
|
365 |
/* VLYNQ registers*/
|
|
366 |
/* VLYNQ2 was removed from hardware*/
|
|
367 |
#define VL1_REV_ID (REGISTERS_BASE + 0x8000) /* VLYNQ_REVISION*/
|
|
368 |
#define VL1_CTL (REGISTERS_BASE + 0x8004) /* VLYNQ_ CONTROL*/
|
|
369 |
#define VL1_STS (REGISTERS_BASE + 0x8008) /* VLYNQ_STATUS*/
|
|
370 |
#define VLYNQ_INTVEC (REGISTERS_BASE + 0x800C)
|
|
371 |
#define VL1_INT_STS (REGISTERS_BASE + 0x8010) /* VLYNQ_INTCR*/
|
|
372 |
#define VL1_INT_PEND (REGISTERS_BASE + 0x8014) /* VLYNQ_INTSR*/
|
|
373 |
#define VL1_INT_PTR (REGISTERS_BASE + 0x8018) /* VLYNQ_INTPTR*/
|
|
374 |
#define VL1_TX_ADDR (REGISTERS_BASE + 0x801C) /* VLYNQ_TX_MAP_ADDR*/
|
|
375 |
#define VL1_RX_SIZE1 (REGISTERS_BASE + 0x8020) /* VLYNQ_RX_MAP_SIZE1*/
|
|
376 |
#define VL1_RX_OFF1 (REGISTERS_BASE + 0x8024) /* VLYNQ_RX_MAP_OFFSET1*/
|
|
377 |
#define VL1_RX_SIZE2 (REGISTERS_BASE + 0x8028) /* VLYNQ_RX_MAP_SIZE2*/
|
|
378 |
#define VL1_RX_OFF2 (REGISTERS_BASE + 0x802C) /* VLYNQ_RX_MAP_OFFSET2*/
|
|
379 |
#define VL1_RX_SIZE3 (REGISTERS_BASE + 0x8030) /* VLYNQ_RX_MAP_SIZE3*/
|
|
380 |
#define VL1_RX_OFF3 (REGISTERS_BASE + 0x8034) /* VLYNQ_RX_MAP_OFFSET3*/
|
|
381 |
#define VL1_RX_SIZE4 (REGISTERS_BASE + 0x8038) /* VLYNQ_RX_MAP_SIZE4*/
|
|
382 |
#define VL1_RX_OFF4 (REGISTERS_BASE + 0x803C) /* VLYNQ_RX_MAP_OFFSET4*/
|
|
383 |
#define VL1_CHIP_VER (REGISTERS_BASE + 0x8040) /* VLYNQ_CHIP_VER*/
|
|
384 |
#define VLYNQ_AUTONEG (REGISTERS_BASE + 0x8044)
|
|
385 |
#define VLYNQ_MANNEG (REGISTERS_BASE + 0x8048)
|
|
386 |
#define VLYNQ_NEGSTAT (REGISTERS_BASE + 0x804C)
|
|
387 |
#define VLYNQ_ENDIAN (REGISTERS_BASE + 0x805C)
|
|
388 |
#define VL1_INT_VEC3_0 (REGISTERS_BASE + 0x8060) /* VLYNQ_HW_INT3TO0_CFG*/
|
|
389 |
#define VL1_INT_VEC7_4 (REGISTERS_BASE + 0x8064) /* VLYNQ_HW_INT7TO4_CFG*/
|
|
390 |
/* VLYNQ Remote configuration registers*/
|
|
391 |
#define VL1_REM_REV_ID (REGISTERS_BASE + 0x8080) /* VLYNQ_REM_REVISION*/
|
|
392 |
#define VL1_REM_CTL (REGISTERS_BASE + 0x8084) /* VLYNQ_REM_ CONTROL*/
|
|
393 |
#define VL1_REM_STS (REGISTERS_BASE + 0x8088) /* VLYNQ_REM_STATUS*/
|
|
394 |
#define VLYNQ_REM_INTVEC (REGISTERS_BASE + 0x808C)
|
|
395 |
#define VL1_REM_INT_STS (REGISTERS_BASE + 0x8090) /* VLYNQ_REM_INTCR*/
|
|
396 |
#define VL1_REM_INT_PEND (REGISTERS_BASE + 0x8094) /* VLYNQ_REM_INTSR*/
|
|
397 |
#define VL1_REM_INT_PTR (REGISTERS_BASE + 0x8098) /* VLYNQ_REM_INTPTR*/
|
|
398 |
#define VL1_REM_TX_ADDR (REGISTERS_BASE + 0x809C) /* VLYNQ_REM_TX_MAP_ADDR*/
|
|
399 |
#define VL1_REM_RX_SIZE1 (REGISTERS_BASE + 0x80A0) /* VLYNQ_REM_RX_MAP_SIZE1*/
|
|
400 |
#define VL1_REM_RX_OFF1 (REGISTERS_BASE + 0x80A4) /* VLYNQ_REM_RX_MAP_OFFSET1*/
|
|
401 |
#define VL1_REM_RX_SIZE2 (REGISTERS_BASE + 0x80A8) /* VLYNQ_REM_RX_MAP_SIZE2*/
|
|
402 |
#define VL1_REM_RX_OFF2 (REGISTERS_BASE + 0x80AC) /* VLYNQ_REM_RX_MAP_OFFSET2*/
|
|
403 |
#define VL1_REM_RX_SIZE3 (REGISTERS_BASE + 0x80B0) /* VLYNQ_REM_RX_MAP_SIZE3*/
|
|
404 |
#define VL1_REM_RX_OFF3 (REGISTERS_BASE + 0x80B4) /* VLYNQ_REM_RX_MAP_OFFSET3*/
|
|
405 |
#define VL1_REM_RX_SIZE4 (REGISTERS_BASE + 0x80B8) /* VLYNQ_REM_RX_MAP_SIZE4*/
|
|
406 |
#define VL1_REM_RX_OFF4 (REGISTERS_BASE + 0x80BC) /* VLYNQ_REM_RX_MAP_OFFSET4*/
|
|
407 |
#define VL1_REM_CHIP_VER (REGISTERS_BASE + 0x80C0) /* VLYNQ_REM_CHIP_VER*/
|
|
408 |
#define VLYNQ_REM_AUTONEG (REGISTERS_BASE + 0x80C4)
|
|
409 |
#define VLYNQ_REM_MANNEG (REGISTERS_BASE + 0x80C8)
|
|
410 |
#define VLYNQ_REM_NEGSTAT (REGISTERS_BASE + 0x80CC)
|
|
411 |
#define VLYNQ_REM_ENDIAN (REGISTERS_BASE + 0x80DC)
|
|
412 |
#define VL1_REM_INT_VEC3_0 (REGISTERS_BASE + 0x80E0) /* VLYNQ_REM_HW_INT3TO0_CFG*/
|
|
413 |
#define VL1_REM_INT_VEC7_4 (REGISTERS_BASE + 0x80E4) /* VLYNQ_REM_HW_INT7TO4_CFG*/
|
|
414 |
|
|
415 |
/* PCIIF*/
|
|
416 |
/**/
|
|
417 |
#define PCI_ID_REG (REGISTERS_BASE + 0x8400)
|
|
418 |
#define PCI_STATUS_SET_REG (REGISTERS_BASE + 0x8410)
|
|
419 |
#define PCI_STATUS_CLR_REG (REGISTERS_BASE + 0x8414)
|
|
420 |
#define PCI_HIMASK_SET_REG (REGISTERS_BASE + 0x8420)
|
|
421 |
#define PCI_HIMASK_CLR_REG (REGISTERS_BASE + 0x8424)
|
|
422 |
#define PCI_AMASK_SET_REG (REGISTERS_BASE + 0x8430)
|
|
423 |
#define PCI_AMASK_CLR_REG (REGISTERS_BASE + 0x8434)
|
|
424 |
#define PCI_CLKRUN_REG (REGISTERS_BASE + 0x8438)
|
|
425 |
#define PCI_BE_VENDOR_ID_REG (REGISTERS_BASE + 0x8500)
|
|
426 |
#define PCI_BE_COMMAND_REG (REGISTERS_BASE + 0x8504)
|
|
427 |
#define PCI_BE_REVISION_REG (REGISTERS_BASE + 0x8508)
|
|
428 |
#define PCI_BE_CL_SIZE_REG (REGISTERS_BASE + 0x850C)
|
|
429 |
#define PCI_BE_BAR0_MASK_REG (REGISTERS_BASE + 0x8510)
|
|
430 |
#define PCI_BE_BAR1_MASK_REG (REGISTERS_BASE + 0x8514)
|
|
431 |
#define PCI_BE_BAR2_MASK_REG (REGISTERS_BASE + 0x8518)
|
|
432 |
#define PCI_BE_BAR3_MASK_REG (REGISTERS_BASE + 0x851C)
|
|
433 |
#define PCI_BE_CIS_PTR_REG (REGISTERS_BASE + 0x8528)
|
|
434 |
#define PCI_BE_SUBSYS_ID_REG (REGISTERS_BASE + 0x852C)
|
|
435 |
#define PCI_BE_CAP_PTR_REG (REGISTERS_BASE + 0x8534)
|
|
436 |
#define PCI_BE_INTR_LINE_REG (REGISTERS_BASE + 0x853C)
|
|
437 |
#define PCI_BE_PM_CAP_REG (REGISTERS_BASE + 0x8540)
|
|
438 |
#define PCI_BE_PM_CTRL_REG (REGISTERS_BASE + 0x8544)
|
|
439 |
#define PCI_BE_PM_D0_CTRL_REG (REGISTERS_BASE + 0x8560)
|
|
440 |
#define PCI_BE_PM_D1_CTRL_REG (REGISTERS_BASE + 0x8564)
|
|
441 |
#define PCI_BE_PM_D2_CTRL_REG (REGISTERS_BASE + 0x8568)
|
|
442 |
#define PCI_BE_PM_D3_CTRL_REG (REGISTERS_BASE + 0x856C)
|
|
443 |
#define PCI_BE_SLV_CFG_REG (REGISTERS_BASE + 0x8580)
|
|
444 |
#define PCI_BE_ARB_CTRL_REG (REGISTERS_BASE + 0x8584)
|
|
445 |
|
|
446 |
#define FER (REGISTERS_BASE + 0x85A0) /* PCI_BE_STSCHG_FE_REG*/
|
|
447 |
#define FEMR (REGISTERS_BASE + 0x85A4) /* PCI_BE_STSCHG_FEM_REG*/
|
|
448 |
#define FPSR (REGISTERS_BASE + 0x85A8) /* PCI_BE_STSCHG_FPS_REG*/
|
|
449 |
#define FFER (REGISTERS_BASE + 0x85AC) /* PCI_BE_STSCHG_FFE_REG*/
|
|
450 |
|
|
451 |
#define PCI_BE_BAR0_TRANS_REG (REGISTERS_BASE + 0x85C0)
|
|
452 |
#define PCI_BE_BAR1_TRANS_REG (REGISTERS_BASE + 0x85C4)
|
|
453 |
#define PCI_BE_BAR2_TRANS_REG (REGISTERS_BASE + 0x85C8)
|
|
454 |
#define PCI_BE_BAR3_TRANS_REG (REGISTERS_BASE + 0x85CC)
|
|
455 |
#define PCI_BE_BAR4_TRANS_REG (REGISTERS_BASE + 0x85D0)
|
|
456 |
#define PCI_BE_BAR5_TRANS_REG (REGISTERS_BASE + 0x85D4)
|
|
457 |
#define PCI_BE_BAR0_REG (REGISTERS_BASE + 0x85E0)
|
|
458 |
#define PCI_BE_BAR1_REG (REGISTERS_BASE + 0x85E4)
|
|
459 |
#define PCI_BE_BAR2_REG (REGISTERS_BASE + 0x85E8)
|
|
460 |
#define PCI_BE_BAR3_REG (REGISTERS_BASE + 0x85EC)
|
|
461 |
|
|
462 |
#define PCI_PROXY_DATA (REGISTERS_BASE + 0x8700)
|
|
463 |
#define PCI_PROXY_ADDR (REGISTERS_BASE + 0x8704)
|
|
464 |
#define PCI_PROXY_CMD (REGISTERS_BASE + 0x8708)
|
|
465 |
#define PCI_CONTROL (REGISTERS_BASE + 0x8710)
|
|
466 |
|
|
467 |
/* USB1.1 registers*/
|
|
468 |
/**/
|
|
469 |
#define USB_STS_CLR (REGISTERS_BASE + 0x4000)
|
|
470 |
#define USB_STS_ND (REGISTERS_BASE + 0x4004)
|
|
471 |
#define USB_INT_ACK (REGISTERS_BASE + 0x4008)
|
|
472 |
#define USB_MASK (REGISTERS_BASE + 0x400c)
|
|
473 |
#define USB_MASK_SET (REGISTERS_BASE + 0x4010)
|
|
474 |
#define USB_MASK_CLR (REGISTERS_BASE + 0x4014)
|
|
475 |
#define USB_WU (REGISTERS_BASE + 0x4018)
|
|
476 |
#define USB_EP0_OUT_PTR (REGISTERS_BASE + 0x401c)
|
|
477 |
#define USB_EP0_OUT_VLD (REGISTERS_BASE + 0x4020)
|
|
478 |
#define USB_EP0_OUT_LEN (REGISTERS_BASE + 0x4024)
|
|
479 |
#define USB_EP0_IN_PTR (REGISTERS_BASE + 0x4028)
|
|
480 |
#define USB_EP0_IN_VLD (REGISTERS_BASE + 0x402c)
|
|
481 |
#define USB_EP0_IN_LEN (REGISTERS_BASE + 0x4030)
|
|
482 |
#define USB_EP1_CFG (REGISTERS_BASE + 0x4034)
|
|
483 |
#define USB_EP1_OUT_INT_CFG (REGISTERS_BASE + 0x4038)
|
|
484 |
#define USB_EP1_OUT_PTR (REGISTERS_BASE + 0x403c)
|
|
485 |
#define USB_EP1_OUT_VLD (REGISTERS_BASE + 0x4040)
|
|
486 |
#define USB_EP1_OUT_CUR_MBLK (REGISTERS_BASE + 0x4044)
|
|
487 |
#define USB_EP1_OUT_LEN (REGISTERS_BASE + 0x4048)
|
|
488 |
#define USB_EP1_IN_START_MBLK (REGISTERS_BASE + 0x404c)
|
|
489 |
#define USB_EP1_IN_LAST_MBLK (REGISTERS_BASE + 0x4050)
|
|
490 |
#define USB_EP1_IN_VLD (REGISTERS_BASE + 0x4054)
|
|
491 |
|
|
492 |
#define USB_EP2_PTR (REGISTERS_BASE + 0x405c)
|
|
493 |
#define USB_EP2_VLD (REGISTERS_BASE + 0x4060)
|
|
494 |
#define USB_EP2_LEN (REGISTERS_BASE + 0x4064)
|
|
495 |
#define USB_EP3_OUT_PTR0 (REGISTERS_BASE + 0x4068)
|
|
496 |
#define USB_EP3_OUT_VLD0 (REGISTERS_BASE + 0x406c)
|
|
497 |
#define USB_EP3_OUT_LEN0 (REGISTERS_BASE + 0x4070)
|
|
498 |
#define USB_EP3_OUT_PTR1 (REGISTERS_BASE + 0x4074)
|
|
499 |
#define USB_EP3_OUT_VLD1 (REGISTERS_BASE + 0x4078)
|
|
500 |
#define USB_EP3_OUT_LEN1 (REGISTERS_BASE + 0x407c)
|
|
501 |
#define USB_EP3_IN_PTR0 (REGISTERS_BASE + 0x4080)
|
|
502 |
#define USB_EP3_IN_VLD0 (REGISTERS_BASE + 0x4084)
|
|
503 |
#define USB_EP3_IN_LEN0 (REGISTERS_BASE + 0x4088)
|
|
504 |
#define USB_EP3_IN_PTR1 (REGISTERS_BASE + 0x408c)
|
|
505 |
#define USB_EP3_IN_VLD1 (REGISTERS_BASE + 0x4090)
|
|
506 |
#define USB_EP3_IN_LEN1 (REGISTERS_BASE + 0x4094)
|
|
507 |
#define USB_EP1_OUT_END_MBLK (REGISTERS_BASE + 0x4098)
|
|
508 |
#define USB_EP0_OUT_SETUP (REGISTERS_BASE + 0x409c)
|
|
509 |
#define USB_EP0_STALL (REGISTERS_BASE + 0x40a0)
|
|
510 |
#define USB_EP1_IN_OFFSET (REGISTERS_BASE + 0x40a4)
|
|
511 |
|
|
512 |
/* Device Configuration registers*/
|
|
513 |
#define SOR_CFG (REGISTERS_BASE + 0x0800)
|
|
514 |
#define ECPU_CTRL (REGISTERS_BASE + 0x0804)
|
|
515 |
#define HI_CFG (REGISTERS_BASE + 0x0808)
|
|
516 |
#define EE_START (REGISTERS_BASE + 0x080C)
|
|
517 |
|
|
518 |
/* IO Control registers*/
|
|
519 |
#define SERIAL_HOST_IOCFG0 (REGISTERS_BASE + 0x0894) /* new*/
|
|
520 |
#define SERIAL_HOST_IOCFG1 (REGISTERS_BASE + 0x0898) /* new*/
|
|
521 |
#define SERIAL_HOST_IOCFG2 (REGISTERS_BASE + 0x089C) /* new*/
|
|
522 |
#define SERIAL_HOST_IOCFG3 (REGISTERS_BASE + 0x08A0) /* new*/
|
|
523 |
#define GPIO_IOCFG0 (REGISTERS_BASE + 0x08F4) /* new*/
|
|
524 |
#define GPIO_IOCFG1 (REGISTERS_BASE + 0x08F8) /* new*/
|
|
525 |
#define GPIO_IOCFG2 (REGISTERS_BASE + 0x08FC) /* new*/
|
|
526 |
#define GPIO_IOCFG3 (REGISTERS_BASE + 0x0900) /* new*/
|
|
527 |
#define CHIP_ID_B (REGISTERS_BASE + 0x5674) /* new*/
|
|
528 |
#define CHIP_ID CHIP_ID_B/* Leave for TNETW compatability*/
|
|
529 |
#define CHIP_ID_1273_PG10 (0x04030101)
|
|
530 |
#define CHIP_ID_1273_PG20 (0x04030111)
|
|
531 |
|
|
532 |
#define SYSTEM (REGISTERS_BASE + 0x0810)
|
|
533 |
#define PCI_ARB_CFG (REGISTERS_BASE + 0x0814)
|
|
534 |
#define BOOT_IRAM_CFG (REGISTERS_BASE + 0x0818)
|
|
535 |
#define IO_CONTROL_ENABLE (REGISTERS_BASE + 0x5450)
|
|
536 |
#define MBLK_CFG (REGISTERS_BASE + 0x5460)
|
|
537 |
#define RS232_BITINTERVAL (REGISTERS_BASE + 0x0824)
|
|
538 |
#define TEST_PORT (REGISTERS_BASE + 0x096C)
|
|
539 |
#define DEBUG_PORT (REGISTERS_BASE + 0x0970)
|
|
540 |
#define HOST_WR_ACCESS_REG (REGISTERS_BASE + 0x09F8)
|
|
541 |
|
|
542 |
/* GPIO registers*/
|
|
543 |
#define GPIO_OE (REGISTERS_BASE + 0x082C) /* 22 GPIOs*/
|
|
544 |
#define GPIO_OUT (REGISTERS_BASE + 0x0834)
|
|
545 |
#define GPIO_IN (REGISTERS_BASE + 0x0830)
|
|
546 |
#define GPO_CFG (REGISTERS_BASE + 0x083C)
|
|
547 |
#define GPIO_SELECT (REGISTERS_BASE + 0x614C)
|
|
548 |
#define GPIO_OE_RADIO (REGISTERS_BASE + 0x6140)
|
|
549 |
#define PWRDN_BUS_L (REGISTERS_BASE + 0x0844)
|
|
550 |
#define PWRDN_BUS_H (REGISTERS_BASE + 0x0848)
|
|
551 |
#define DIE_ID_L (REGISTERS_BASE + 0x088C)
|
|
552 |
#define DIE_ID_H (REGISTERS_BASE + 0x0890)
|
|
553 |
|
|
554 |
/* Power Management registers*/
|
|
555 |
/* */
|
|
556 |
#define ELP_START (REGISTERS_BASE + 0x5800)
|
|
557 |
#define ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
|
|
558 |
#define ELP_CMD (REGISTERS_BASE + 0x5808)
|
|
559 |
#define PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
|
|
560 |
#define CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
|
|
561 |
#define CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
|
|
562 |
|
|
563 |
#define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820) /* Points to the CFG_PLL_SYNC_CNT_xx registers set*/
|
|
564 |
#define CFG_PLL_SYNC_CNT_I (REGISTERS_BASE + 0x5820)
|
|
565 |
#define CFG_PLL_SYNC_CNT_II (REGISTERS_BASE + 0x5824)
|
|
566 |
#define CFG_PLL_SYNC_CNT_III (REGISTERS_BASE + 0x5828)
|
|
567 |
|
|
568 |
#define CFG_ELP_SLEEP_CNT (REGISTERS_BASE + 0x5830) /* Points to the CFG_ELP_SLEEP_CNT_xx registers set*/
|
|
569 |
#define CFG_ELP_SLEEP_CNT_I (REGISTERS_BASE + 0x5830)
|
|
570 |
#define CFG_ELP_SLEEP_CNT_II (REGISTERS_BASE + 0x5834)
|
|
571 |
#define CFG_ELP_SLEEP_CNT_III (REGISTERS_BASE + 0x5838)
|
|
572 |
#define CFG_ELP_SLEEP_CNT_IV (REGISTERS_BASE + 0x583c)
|
|
573 |
|
|
574 |
#define ELP_SLEEP_CNT (REGISTERS_BASE + 0x5840) /* Points to the ELP_SLEEP_CNT_xx registers set*/
|
|
575 |
#define ELP_SLEEP_CNT_I (REGISTERS_BASE + 0x5840)
|
|
576 |
#define ELP_SLEEP_CNT_II (REGISTERS_BASE + 0x5844)
|
|
577 |
#define ELP_SLEEP_CNT_III (REGISTERS_BASE + 0x5848)
|
|
578 |
#define ELP_SLEEP_CNT_IV (REGISTERS_BASE + 0x584c)
|
|
579 |
|
|
580 |
#define ELP_WAKE_UP_STS (REGISTERS_BASE + 0x5850)
|
|
581 |
#define CFG_SLP_CLK_SEL (REGISTERS_BASE + 0x5860)
|
|
582 |
#define CFG_SLP_CLK_EN (REGISTERS_BASE + 0x5870)
|
|
583 |
|
|
584 |
#define CFG_WAKE_UP_EN_I (REGISTERS_BASE + 0x5880)
|
|
585 |
#define CFG_WAKE_UP_EN_II (REGISTERS_BASE + 0x5884)
|
|
586 |
#define CFG_WAKE_UP_EN_III (REGISTERS_BASE + 0x5888)
|
|
587 |
|
|
588 |
#define CFG_ELP_PWRDN_I (REGISTERS_BASE + 0x5890)
|
|
589 |
#define CFG_ELP_PWRDN_II (REGISTERS_BASE + 0x5894)
|
|
590 |
#define CFG_ELP_PWRDN_III (REGISTERS_BASE + 0x5898)
|
|
591 |
|
|
592 |
#define CFG_POWER_DOWN_I (REGISTERS_BASE + 0x58a0)
|
|
593 |
#define CFG_POWER_DOWN_II (REGISTERS_BASE + 0x58a4)
|
|
594 |
#define CFG_POWER_DOWN_III (REGISTERS_BASE + 0x58a8)
|
|
595 |
|
|
596 |
#define CFG_BUCK_TESTMODE_I (REGISTERS_BASE + 0x58b0)
|
|
597 |
#define CFG_BUCK_TESTMODE_II (REGISTERS_BASE + 0x58b4)
|
|
598 |
|
|
599 |
#define POWER_STATUS_I (REGISTERS_BASE + 0x58C0)
|
|
600 |
#define POWER_STATUS_II (REGISTERS_BASE + 0x58C4)
|
|
601 |
|
|
602 |
#define DIGLDO_BIAS_PROG_I (REGISTERS_BASE + 0x58d0)
|
|
603 |
#define DIGLDO_BIAS_PROG_II (REGISTERS_BASE + 0x58d4)
|
|
604 |
|
|
605 |
#define LDO2P8_BIAS_PROG_I (REGISTERS_BASE + 0x58e0)
|
|
606 |
#define LDO2P8_BIAS_PROG_II (REGISTERS_BASE + 0x58e4)
|
|
607 |
|
|
608 |
#define ADCLDO_BIAS_PROG (REGISTERS_BASE + 0x58f0)
|
|
609 |
|
|
610 |
#define REFSYS_PROG_I (REGISTERS_BASE + 0x5910)
|
|
611 |
#define REFSYS_PROG_II (REGISTERS_BASE + 0x5914)
|
|
612 |
|
|
613 |
#define PM_TEST_I (REGISTERS_BASE + 0x5920)
|
|
614 |
#define PM_TEST_II (REGISTERS_BASE + 0x5924)
|
|
615 |
|
|
616 |
#define POR_PROG (REGISTERS_BASE + 0x5930)
|
|
617 |
|
|
618 |
#define TEST_PIN_DIR_I (REGISTERS_BASE + 0x5940)
|
|
619 |
#define TEST_PIN_DIR_II (REGISTERS_BASE + 0x5944)
|
|
620 |
|
|
621 |
#define PROC_CTL (REGISTERS_BASE + 0x5950)
|
|
622 |
|
|
623 |
#define ADC_REF_WAKEUP_I (REGISTERS_BASE + 0x5960)
|
|
624 |
#define ADC_REF_WAKEUP_II (REGISTERS_BASE + 0x5964)
|
|
625 |
#define ADC_REF_WAKEUP_III (REGISTERS_BASE + 0x5968)
|
|
626 |
#define ADC_REF_WAKEUP_IV (REGISTERS_BASE + 0x596C)
|
|
627 |
|
|
628 |
#define VREG_WAKEUP_I (REGISTERS_BASE + 0x5970)
|
|
629 |
#define VREG_WAKEUP_II (REGISTERS_BASE + 0x5974)
|
|
630 |
#define VREG_WAKEUP_III (REGISTERS_BASE + 0x5978)
|
|
631 |
#define VREG_WAKEUP_IV (REGISTERS_BASE + 0x597C)
|
|
632 |
|
|
633 |
#define PLL_WAKEUP_I (REGISTERS_BASE + 0x5980)
|
|
634 |
#define PLL_WAKEUP_II (REGISTERS_BASE + 0x5984)
|
|
635 |
#define PLL_WAKEUP_III (REGISTERS_BASE + 0x5988)
|
|
636 |
#define PLL_WAKEUP_IV (REGISTERS_BASE + 0x598C)
|
|
637 |
|
|
638 |
#define XTALOSC_WAKEUP_I (REGISTERS_BASE + 0x5990)
|
|
639 |
#define XTALOSC_WAKEUP_II (REGISTERS_BASE + 0x5994)
|
|
640 |
#define XTALOSC_WAKEUP_III (REGISTERS_BASE + 0x5998)
|
|
641 |
#define XTALOSC_WAKEUP_IV (REGISTERS_BASE + 0x599C)
|
|
642 |
|
|
643 |
/* ----------*/
|
|
644 |
|
|
645 |
#define PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
|
|
646 |
#define WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
|
|
647 |
#define WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)
|
|
648 |
|
|
649 |
/* ----------*/
|
|
650 |
|
|
651 |
#define POWER_MGMT2 (REGISTERS_BASE + 0x0840)
|
|
652 |
#define POWER_MGMT (REGISTERS_BASE + 0x5098)
|
|
653 |
#define MAC_HW_DOZE (REGISTERS_BASE + 0x090c)
|
|
654 |
#define ECPU_SLEEP (REGISTERS_BASE + 0x0840)
|
|
655 |
#define DOZE_CFG (REGISTERS_BASE + 0x54bc)
|
|
656 |
#define DOZE2_CFG (REGISTERS_BASE + 0x081c)
|
|
657 |
#define WAKEUP_CFG (REGISTERS_BASE + 0x54c0)
|
|
658 |
#define WAKEUP_TIME_L (REGISTERS_BASE + 0x54c8)
|
|
659 |
#define WAKEUP_TIME_H (REGISTERS_BASE + 0x54c4)
|
|
660 |
|
|
661 |
/**/
|
|
662 |
|
|
663 |
/*#define CPU_WAIT_CFG (f0020)*/
|
|
664 |
/*#define CFG_QOS_ACM (f0046)*/
|
|
665 |
|
|
666 |
/* Scratch Pad registers*/
|
|
667 |
#define SCR_PAD0 (REGISTERS_BASE + 0x5608)
|
|
668 |
#define SCR_PAD1 (REGISTERS_BASE + 0x560C)
|
|
669 |
#define SCR_PAD2 (REGISTERS_BASE + 0x5610)
|
|
670 |
#define SCR_PAD3 (REGISTERS_BASE + 0x5614)
|
|
671 |
#define SCR_PAD4 (REGISTERS_BASE + 0x5618)
|
|
672 |
#define SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
|
|
673 |
#define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
|
|
674 |
#define SCR_PAD5 (REGISTERS_BASE + 0x5624)
|
|
675 |
#define SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
|
|
676 |
#define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
|
|
677 |
#define SCR_PAD6 (REGISTERS_BASE + 0x5630)
|
|
678 |
#define SCR_PAD7 (REGISTERS_BASE + 0x5634)
|
|
679 |
#define SCR_PAD8 (REGISTERS_BASE + 0x5638)
|
|
680 |
#define SCR_PAD9 (REGISTERS_BASE + 0x563C)
|
|
681 |
|
|
682 |
/* Spare registers*/
|
|
683 |
#define SPARE_A1 (REGISTERS_BASE + 0x0994)
|
|
684 |
#define SPARE_A2 (REGISTERS_BASE + 0x0998)
|
|
685 |
#define SPARE_A3 (REGISTERS_BASE + 0x099C)
|
|
686 |
#define SPARE_A4 (REGISTERS_BASE + 0x09A0)
|
|
687 |
#define SPARE_A5 (REGISTERS_BASE + 0x09A4)
|
|
688 |
#define SPARE_A6 (REGISTERS_BASE + 0x09A8)
|
|
689 |
#define SPARE_A7 (REGISTERS_BASE + 0x09AC)
|
|
690 |
#define SPARE_A8 (REGISTERS_BASE + 0x09B0)
|
|
691 |
#define SPARE_B1 (REGISTERS_BASE + 0x5420)
|
|
692 |
#define SPARE_B2 (REGISTERS_BASE + 0x5424)
|
|
693 |
#define SPARE_B3 (REGISTERS_BASE + 0x5428)
|
|
694 |
#define SPARE_B4 (REGISTERS_BASE + 0x542C)
|
|
695 |
#define SPARE_B5 (REGISTERS_BASE + 0x5430)
|
|
696 |
#define SPARE_B6 (REGISTERS_BASE + 0x5434)
|
|
697 |
#define SPARE_B7 (REGISTERS_BASE + 0x5438)
|
|
698 |
#define SPARE_B8 (REGISTERS_BASE + 0x543C)
|
|
699 |
|
|
700 |
/* RMAC registers (Raleigh MAC)*/
|
|
701 |
|
|
702 |
/* Station registers*/
|
|
703 |
#define DEV_MODE (REGISTERS_BASE + 0x5464)
|
|
704 |
#define STA_ADDR_L (REGISTERS_BASE + 0x546C)
|
|
705 |
#define STA_ADDR_H (REGISTERS_BASE + 0x5470)
|
|
706 |
#define BSSID_L (REGISTERS_BASE + 0x5474)
|
|
707 |
#define BSSID_H (REGISTERS_BASE + 0x5478)
|
|
708 |
#define AID_CFG (REGISTERS_BASE + 0x547C)
|
|
709 |
#define BASIC_RATE_CFG (REGISTERS_BASE + 0x4C6C)
|
|
710 |
#define BASIC_RATE_TX_CFG (REGISTERS_BASE + 0x55F0)
|
|
711 |
|
|
712 |
/* Protocol timers registers*/
|
|
713 |
#define IFS_CFG0 (REGISTERS_BASE + 0x5494)
|
|
714 |
#define IFS_CFG1 (REGISTERS_BASE + 0x5498)
|
|
715 |
#define TIMEOUT_CFG (REGISTERS_BASE + 0x549C)
|
|
716 |
#define CONT_WIND_CFG (REGISTERS_BASE + 0x54A0)
|
|
717 |
#define BCN_INT_CFG (REGISTERS_BASE + 0x54A4)
|
|
718 |
#define RETRY_CFG (REGISTERS_BASE + 0x54A8)
|
|
719 |
#define DELAY_CFG (REGISTERS_BASE + 0x54B0)
|
|
720 |
|
|
721 |
/* Hardware Override registers*/
|
|
722 |
#define CCA_CFG (REGISTERS_BASE + 0x54CC)
|
|
723 |
#define CCA_FILTER_CFG (REGISTERS_BASE + 0x5480)
|
|
724 |
#define RADIO_PLL_CFG (REGISTERS_BASE + 0x555C)
|
|
725 |
#define CCA_MON (REGISTERS_BASE + 0x54D0)
|
|
726 |
#define TX_FRM_CTL (REGISTERS_BASE + 0x54D4)
|
|
727 |
#define CONT_TX_EN (REGISTERS_BASE + 0x50EC)
|
|
728 |
#define PHY_STANDBY_EN (REGISTERS_BASE + 0x5668)
|
|
729 |
|
|
730 |
/* Transmit Setup registers*/
|
|
731 |
#define TX_PING_PONG (REGISTERS_BASE + 0x5090)
|
|
732 |
#define TX_CFG0 (REGISTERS_BASE + 0x5000)
|
|
733 |
#define TX_CFG1 (REGISTERS_BASE + 0x5004)
|
|
734 |
#define TX_CFG2 (REGISTERS_BASE + 0x5008)
|
|
735 |
#define MAX_LIFETIME (REGISTERS_BASE + 0x50FC)
|
|
736 |
#define TX_PANG_SEL (REGISTERS_BASE + 0x50E0)
|
|
737 |
#define TX_PANG0 (REGISTERS_BASE + 0x50A0)
|
|
738 |
#define TX_PING0 (REGISTERS_BASE + 0x5010)
|
|
739 |
#define TX_PONG0 (REGISTERS_BASE + 0x5050)
|
|
740 |
#define TX_PANG1 (REGISTERS_BASE + 0x50A4)
|
|
741 |
#define TX_PING1 (REGISTERS_BASE + 0x5014)
|
|
742 |
#define TX_PONG1 (REGISTERS_BASE + 0x5054)
|
|
743 |
#define TX_PANG2 (REGISTERS_BASE + 0x50A8)
|
|
744 |
#define TX_PING2 (REGISTERS_BASE + 0x5018)
|
|
745 |
#define TX_PONG2 (REGISTERS_BASE + 0x5058)
|
|
746 |
#define TX_PANG3 (REGISTERS_BASE + 0x50AC)
|
|
747 |
#define TX_PING3 (REGISTERS_BASE + 0x501C)
|
|
748 |
#define TX_PONG3 (REGISTERS_BASE + 0x505C)
|
|
749 |
#define TX_PANG4 (REGISTERS_BASE + 0x50B0)
|
|
750 |
#define TX_PING4 (REGISTERS_BASE + 0x5020)
|
|
751 |
#define TX_PONG4 (REGISTERS_BASE + 0x5060)
|
|
752 |
#define TX_PANG5 (REGISTERS_BASE + 0x50B4)
|
|
753 |
#define TX_PING5 (REGISTERS_BASE + 0x5024)
|
|
754 |
#define TX_PONG5 (REGISTERS_BASE + 0x5064)
|
|
755 |
#define TX_PANG6 (REGISTERS_BASE + 0x50B8)
|
|
756 |
#define TX_PING6 (REGISTERS_BASE + 0x5028)
|
|
757 |
#define TX_PONG6 (REGISTERS_BASE + 0x5068)
|
|
758 |
#define TX_PANG7 (REGISTERS_BASE + 0x50BC)
|
|
759 |
#define TX_PING7 (REGISTERS_BASE + 0x502C)
|
|
760 |
#define TX_PONG7 (REGISTERS_BASE + 0x506C)
|
|
761 |
#define TX_PANG8 (REGISTERS_BASE + 0x50C0)
|
|
762 |
#define TX_PING8 (REGISTERS_BASE + 0x5030)
|
|
763 |
#define TX_PONG8 (REGISTERS_BASE + 0x5070)
|
|
764 |
#define TX_PANG9 (REGISTERS_BASE + 0x50C4)
|
|
765 |
#define TX_PING9 (REGISTERS_BASE + 0x5034)
|
|
766 |
#define TX_PONG9 (REGISTERS_BASE + 0x5074)
|
|
767 |
#define TX_PANG10 (REGISTERS_BASE + 0x50C8)
|
|
768 |
#define TX_PING10 (REGISTERS_BASE + 0x5038)
|
|
769 |
#define TX_PONG10 (REGISTERS_BASE + 0x5078)
|
|
770 |
#define TX_PANG11 (REGISTERS_BASE + 0x50CC)
|
|
771 |
#define TX_PING11 (REGISTERS_BASE + 0x503C)
|
|
772 |
#define TX_PONG11 (REGISTERS_BASE + 0x507C)
|
|
773 |
|
|
774 |
/* Transmit Status registers*/
|
|
775 |
#define TX_STATUS (REGISTERS_BASE + 0x509C)
|
|
776 |
#define TX_PANG_EXCH (REGISTERS_BASE + 0x50D0)
|
|
777 |
#define TX_PING_EXCH (REGISTERS_BASE + 0x5040)
|
|
778 |
#define TX_PONG_EXCH (REGISTERS_BASE + 0x5080)
|
|
779 |
#define TX_PANG_ATT (REGISTERS_BASE + 0x50D4)
|
|
780 |
#define TX_PING_ATT (REGISTERS_BASE + 0x5044)
|
|
781 |
#define TX_PONG_ATT (REGISTERS_BASE + 0x5084)
|
|
782 |
#define TX_PANG_TIMESTAMP (REGISTERS_BASE + 0x50DC)
|
|
783 |
#define TX_PING_TIMESTAMP (REGISTERS_BASE + 0x504C)
|
|
784 |
#define TX_PONG_TIMESTAMP (REGISTERS_BASE + 0x508C)
|
|
785 |
|
|
786 |
/* Transmit State registers*/
|
|
787 |
#define TX_STATE (REGISTERS_BASE + 0x5094)
|
|
788 |
#define TX_PANG_OVRD_CFG (REGISTERS_BASE + 0x50D8)
|
|
789 |
#define TX_PING_OVRD_CFG (REGISTERS_BASE + 0x5048)
|
|
790 |
#define TX_PONG_OVRD_CFG (REGISTERS_BASE + 0x5088)
|
|
791 |
#define TX_HOLD_CFG (REGISTERS_BASE + 0x54D8)
|
|
792 |
#define TSF_ADJ_CFG1 (REGISTERS_BASE + 0x54DC)
|
|
793 |
#define TSF_ADJ_CFG2 (REGISTERS_BASE + 0x54E0)
|
|
794 |
#define TSF_ADJ_CFG3 (REGISTERS_BASE + 0x54E4)
|
|
795 |
#define TSF_ADJ_CFG4 (REGISTERS_BASE + 0x54E8)
|
|
796 |
#define CFG_OFDM_TIMES0 (REGISTERS_BASE + 0x5648)
|
|
797 |
#define CFG_OFDM_TIMES1 (REGISTERS_BASE + 0x564C)
|
|
798 |
|
|
799 |
/* Beacon/Probe Response registers*/
|
|
800 |
#define PRB_ADDR (REGISTERS_BASE + 0x54EC)
|
|
801 |
#define PRB_LENGTH (REGISTERS_BASE + 0x54F0)
|
|
802 |
#define BCN_ADDR (REGISTERS_BASE + 0x54F4)
|
|
803 |
#define BCN_LENGTH (REGISTERS_BASE + 0x54F8)
|
|
804 |
#define TIM_VALID0 (REGISTERS_BASE + 0x54FC)
|
|
805 |
#define TIM_ADDR0 (REGISTERS_BASE + 0x5500)
|
|
806 |
#define TIM_LENGTH0 (REGISTERS_BASE + 0x5504)
|
|
807 |
#define TIM_VALID1 (REGISTERS_BASE + 0x5654)
|
|
808 |
#define TIM_ADDR1 (REGISTERS_BASE + 0x5658)
|
|
809 |
#define TIM_LENGTH1 (REGISTERS_BASE + 0x565C)
|
|
810 |
#define TIM_SELECT (REGISTERS_BASE + 0x5660)
|
|
811 |
#define TSF_CFG (REGISTERS_BASE + 0x5508)
|
|
812 |
|
|
813 |
/* Other Hardware Generated Frames regi*/
|
|
814 |
#define CTL_FRM_CFG (REGISTERS_BASE + 0x550C)
|
|
815 |
#define MGMT_FRM_CFG (REGISTERS_BASE + 0x5510)
|
|
816 |
#define CFG_ANT_SEL (REGISTERS_BASE + 0x5664)
|
|
817 |
#define RMAC_ADDR_BASE (REGISTERS_BASE + 0x5680) /* new*/
|
|
818 |
|
|
819 |
/* Protocol Interface Read Write Interf*/
|
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820 |
#define TXSIFS_TIMER (REGISTERS_BASE + 0x4C00)
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821 |
#define TXPIFS_TIMER (REGISTERS_BASE + 0x4C04)
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822 |
#define TXDIFS_TIMER (REGISTERS_BASE + 0x4C08)
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823 |
#define SLOT_TIMER (REGISTERS_BASE + 0x4C0C)
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824 |
#define BACKOFF_TIMER (REGISTERS_BASE + 0x4C10)
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825 |
#define BCN_PSP_TIMER (REGISTERS_BASE + 0x4C14)
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826 |
#define NAV (REGISTERS_BASE + 0x4C18)
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827 |
#define TSF_L (REGISTERS_BASE + 0x4C1C)
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828 |
#define TSF_H (REGISTERS_BASE + 0x4C20)
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829 |
#define TSF_PREV_L (REGISTERS_BASE + 0x4CC4) /* new */
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830 |
#define TSF_PREV_H (REGISTERS_BASE + 0x4CC8) /* new */
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831 |
#define TOUT_TIMER (REGISTERS_BASE + 0x4C2C)
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832 |
#define NEXT_TBTT_L (REGISTERS_BASE + 0x4C30)
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833 |
#define NEXT_TBTT_H (REGISTERS_BASE + 0x4C34)
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834 |
#define DTIM_CNT (REGISTERS_BASE + 0x4C38)
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835 |
#define CONT_WIND (REGISTERS_BASE + 0x4C3C)
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836 |
#define PRSP_REQ (REGISTERS_BASE + 0x4C40)
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837 |
#define PRSP_DA_L (REGISTERS_BASE + 0x4C44)
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838 |
#define PRSP_DA_H (REGISTERS_BASE + 0x4C48)
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839 |
#define PRSP_RETRY (REGISTERS_BASE + 0x4C4C)
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840 |
#define PSPOLL_REQ (REGISTERS_BASE + 0x4C50)
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841 |
#define NEXT_SEQ_NUM (REGISTERS_BASE + 0x4C54)
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842 |
#define PRSP_SEQ_NUM (REGISTERS_BASE + 0x4C58)
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843 |
#define BCN_SEQ_NUM (REGISTERS_BASE + 0x4C5C)
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844 |
#define MED_USAGE (REGISTERS_BASE + 0x4C24)
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845 |
#define MED_USAGE_TM (REGISTERS_BASE + 0x4C28)
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846 |
#define PRB_DLY (REGISTERS_BASE + 0x4C60)
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847 |
#define STA_SRC (REGISTERS_BASE + 0x4C64)
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848 |
#define STA_LRC (REGISTERS_BASE + 0x4C68)
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849 |
#define CFG_ACM (REGISTERS_BASE + 0x4C70)
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850 |
#define RAND_NUMB (REGISTERS_BASE + 0x4C6C)
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851 |
#define CFG_ACK_CTS_DOT11A (REGISTERS_BASE + 0x4C74)
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852 |
#define CFG_ACK_CTS_DOT11B (REGISTERS_BASE + 0x4C78)
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853 |
#define ACM_IFS_CFG0 (REGISTERS_BASE + 0x4C7C)
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854 |
#define ACM_IFS_CFG1 (REGISTERS_BASE + 0x4C80)
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855 |
#define ACM_IFS_CFG2 (REGISTERS_BASE + 0x4C84)
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856 |
#define ACM_IFS_CFG3 (REGISTERS_BASE + 0x4C88)
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857 |
#define ACK_CTS_FRM_CFG (REGISTERS_BASE + 0x4C8C)
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858 |
#define CFG_RX_TSTMP_DLY0 (REGISTERS_BASE + 0x4C90)
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859 |
#define CFG_RX_TSTMP_DLY1 (REGISTERS_BASE + 0x4C94)
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860 |
#define CFG_RX_TSTMP_DLY2 (REGISTERS_BASE + 0x4C98)
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861 |
#define CFG_RX_TSTMP_DLY3 (REGISTERS_BASE + 0x4C9C)
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862 |
#define CCA_BUSY (REGISTERS_BASE + 0x4CA0)
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863 |
#define CCA_BUSY_CLR (REGISTERS_BASE + 0x4CA4)
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864 |
#define CCA_IDLE (REGISTERS_BASE + 0x4CA8)
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865 |
#define CCA_IDLE_CLR (REGISTERS_BASE + 0x4CAC)
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866 |
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867 |
/* Receive Manager registers*/
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868 |
#define RX_HEAD_PTR (REGISTERS_BASE + 0x567C) /* new*/
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869 |
#define RX_TAIL_PTR (REGISTERS_BASE + 0x4898) /* new*/
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870 |
#define RX_CURR_PTR (REGISTERS_BASE + 0x5678) /* new*/
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871 |
#define RX_RESET (REGISTERS_BASE + 0x4800)
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872 |
#define RX_MODMODE (REGISTERS_BASE + 0x4838) /* new*/
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873 |
#define MAC_HEADER_BYTECNT (REGISTERS_BASE + 0x4890)
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874 |
#define RX_MAC_BYTECNT_INT (REGISTERS_BASE + 0x489C)
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875 |
#define MAC_HEADER_WORD0 (REGISTERS_BASE + 0x4868)
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876 |
#define MAC_HEADER_WORD1 (REGISTERS_BASE + 0x486C)
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877 |
#define MAC_HEADER_WORD2 (REGISTERS_BASE + 0x4870)
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878 |
#define MAC_HEADER_WORD3 (REGISTERS_BASE + 0x4874)
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879 |
#define MAC_HEADER_WORD4 (REGISTERS_BASE + 0x4878)
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880 |
#define MAC_HEADER_WORD5 (REGISTERS_BASE + 0x487C)
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881 |
#define MAC_HEADER_WORD6 (REGISTERS_BASE + 0x4880)
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882 |
#define MAC_HEADER_WORD7 (REGISTERS_BASE + 0x4884)
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883 |
#define MAC_HEADER_WORD8 (REGISTERS_BASE + 0x4888)
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884 |
#define MAC_HEADER_WORD9 (REGISTERS_BASE + 0x488C)
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885 |
#define RX_CFG (REGISTERS_BASE + 0x5514)
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886 |
#define RX_FILTER_CFG (REGISTERS_BASE + 0x55B4)
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887 |
#define RX_MC0_L (REGISTERS_BASE + 0x5518)
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888 |
#define RX_MC0_H (REGISTERS_BASE + 0x551C)
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889 |
#define RX_MC1_L (REGISTERS_BASE + 0x5520)
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890 |
#define RX_MC1_H (REGISTERS_BASE + 0x5524)
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891 |
#define STA_SSID0 (REGISTERS_BASE + 0x4804)
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892 |
#define STA_SSID1 (REGISTERS_BASE + 0x4808)
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893 |
#define STA_SSID2 (REGISTERS_BASE + 0x480C)
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894 |
#define STA_SSID3 (REGISTERS_BASE + 0x4810)
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895 |
#define STA_SSID4 (REGISTERS_BASE + 0x4814)
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896 |
#define STA_SSID5 (REGISTERS_BASE + 0x4818)
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897 |
#define STA_SSID6 (REGISTERS_BASE + 0x481C)
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898 |
#define STA_SSID7 (REGISTERS_BASE + 0x4820)
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899 |
#define SSID_LEN (REGISTERS_BASE + 0x4824)
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900 |
#define RX_FREE_MEM (REGISTERS_BASE + 0x5528)
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901 |
#define RX_CURR_MEM (REGISTERS_BASE + 0x552C)
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902 |
#define MAC_TIMESTAMP (REGISTERS_BASE + 0x5560) /* Check place*/
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903 |
#define RX_TIMESTAMP (REGISTERS_BASE + 0x5564)
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904 |
#define RX_FRM_PTR (REGISTERS_BASE + 0x5568)
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905 |
#define RX_FRM_LEN (REGISTERS_BASE + 0x556C)
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906 |
#define RX_PLCP_HDR (REGISTERS_BASE + 0x5570)
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907 |
#define RX_PLCP_SIGNAL (REGISTERS_BASE + 0x5574)
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908 |
#define RX_PLCP_SERVICE (REGISTERS_BASE + 0x5578) /* 16 bits ?*/
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909 |
#define RX_PLCP_LENGTH (REGISTERS_BASE + 0x557C)
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910 |
#define RX_FRM_CTL (REGISTERS_BASE + 0x5580)
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911 |
#define RX_DUR_ID (REGISTERS_BASE + 0x5584)
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912 |
#define RX_ADDR1_L (REGISTERS_BASE + 0x5588)
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913 |
#define RX_ADDR1_H (REGISTERS_BASE + 0x558C)
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914 |
#define RX_ADDR2_L (REGISTERS_BASE + 0x5590)
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915 |
#define RX_ADDR2_H (REGISTERS_BASE + 0x5594)
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916 |
#define RX_ADDR3_L (REGISTERS_BASE + 0x5598)
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917 |
#define RX_ADDR3_H (REGISTERS_BASE + 0x559C)
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918 |
#define RX_SEQ_CTL (REGISTERS_BASE + 0x55A0)
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919 |
#define RX_WEP_IV (REGISTERS_BASE + 0x55A4)
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920 |
#define RX_TIME_L (REGISTERS_BASE + 0x55A8)
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921 |
#define RX_TIME_H (REGISTERS_BASE + 0x55AC)
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922 |
#define RX_STATUS (REGISTERS_BASE + 0x55B0)
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923 |
#define PLCP_ERR_CNT (REGISTERS_BASE + 0x4828)
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924 |
#define FCS_ERR_CNT (REGISTERS_BASE + 0x482C)
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925 |
#define RX_OVERFLOW_CNT (REGISTERS_BASE + 0x4830)
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926 |
#define RX_DEBUG1 (REGISTERS_BASE + 0x4858)
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927 |
#define RX_DEBUG2 (REGISTERS_BASE + 0x485C)
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928 |
#define RX_QOS_CFG (REGISTERS_BASE + 0x4848)
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929 |
#define RX_QOS_CTL (REGISTERS_BASE + 0x4844)
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930 |
#define RX_QOS_STATUS (REGISTERS_BASE + 0x4854) /* new name RX_QOS_STS*/
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931 |
#define RX_TXOP_HOLDER_L (REGISTERS_BASE + 0x484C)
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932 |
#define RX_TXOP_HOLDER_H (REGISTERS_BASE + 0x4850)
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933 |
#define RX_FRM_CNT (REGISTERS_BASE + 0x4834) /* what is RX_FRM_CTR*/
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934 |
#define CONS_FCS_ERR_CNT (REGISTERS_BASE + 0x483C)
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935 |
#define CONS_FCS_ERR_CFG (REGISTERS_BASE + 0x4840)
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936 |
#define RX_QOS_CTL_MASK (REGISTERS_BASE + 0x48A0) /* new*/
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937 |
#define RX_QOS_ACK_EN (REGISTERS_BASE + 0x48A4) /* new*/
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938 |
#define RX_QOS_NOACK_EN (REGISTERS_BASE + 0x48A8) /* new*/
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939 |
#define RX_QOS_ACK_BITMAP (REGISTERS_BASE + 0x48AC) /* new*/
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940 |
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941 |
/* Baseband Processor registers*/
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942 |
#define SBB_CFG (REGISTERS_BASE + 0x55C8)
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943 |
#define SBB_ADDR (REGISTERS_BASE + 0x55D0)
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944 |
#define SBB_DATA (REGISTERS_BASE + 0x55D4)
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945 |
#define SBB_CTL (REGISTERS_BASE + 0x55D8)
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946 |
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947 |
/* Radio Control Interface registers*/
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948 |
#define RCI_CTL (REGISTERS_BASE + 0x55DC)
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949 |
#define RCI_DATA (REGISTERS_BASE + 0x55E0)
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950 |
#define RCI_CFG1 (REGISTERS_BASE + 0x55E4)
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951 |
#define RCI_CFG2 (REGISTERS_BASE + 0x55E8)
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952 |
#define RCI_CFG3 (REGISTERS_BASE + 0x55EC)
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953 |
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954 |
#define TNET1150_LAST_REG_ADDR PCI_CONTROL
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955 |
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956 |
#define ECPU_CONTROL_HALT 0x00000101
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957 |
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958 |
/*0x03bc00 address is 1KB from end of FW RAM in 125x chip*/
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959 |
#define FW_STATIC_NVS_TRAGET_ADDRESS 0x03bc00
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960 |
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961 |
/* Command mail box address */
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962 |
#define CMD_MBOX_ADDRESS 0x407B4
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963 |
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964 |
/* Top Register */
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965 |
#define INDIRECT_REG1 (REGISTERS_BASE + 0x9B0)
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966 |
#define OCP_POR_CTR (REGISTERS_BASE + 0x9B4)
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967 |
#define OCP_POR_WDATA (REGISTERS_BASE + 0x9B8)
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968 |
#define OCP_DATA_RD (REGISTERS_BASE + 0x9BC)
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969 |
#define OCP_CMD (REGISTERS_BASE + 0x9C0)
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970 |
#define FUNC7_SEL 0xC8C
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971 |
#define FUNC7_PULL 0xCB0
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972 |
#define FN0_CCCR_REG_32 0x64
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973 |
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974 |
#define PLL_PARAMETERS_CLK_VAL_19_2M 0x01
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975 |
#define PLL_PARAMETERS_CLK_VAL_26M 0x02
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976 |
#define PLL_PARAMETERS_CLK_VAL_38_4M 0x03
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977 |
#define PLL_PARAMETERS_CLK_VAL_52M 0x04
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978 |
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979 |
#define WU_COUNTER_PAUSE_VAL 0x3FF
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980 |
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981 |
/* Base band clocker register */
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982 |
#define WELP_ARM_COMMAND_VAL 0x4
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983 |
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984 |
/* Command mail box address */
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985 |
#define CMD_MBOX_ADDRESS 0x407B4
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986 |
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987 |
#endif
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