// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// e32\nkernsmp\arm\vectors.cia

// 

//

#include <e32cia.h>

#include <arm.h>

#include <arm_gic.h>

#include <arm_scu.h>

#include <arm_tmr.h>

void FastMutexNestAttempt();

void FastMutexSignalError();

extern "C" void ExcFault(TAny*);

extern "C" void send_accumulated_resched_ipis();

extern "C" TInt HandleSpecialOpcode(TArmExcInfo* aContext, TInt aType);

extern "C" {

extern TUint32 CrashStateOut;

extern SFullArmRegSet DefaultRegSet;

}

#ifdef BTRACE_CPU_USAGE

extern "C" void btrace_irq_exit();

extern "C" void btrace_fiq_exit();

#endif

#ifdef _DEBUG

#define __CHECK_LOCK_STATE__

#endif

//#define __FAULT_ON_FIQ__

#ifdef __CHECK_LOCK_STATE__

/******************************************************************************

 * Check that the kernel is unlocked, no fast mutex is held and the thread

 * is not in a critical section when returning to user mode.

 ******************************************************************************/

extern "C" __NAKED__ void check_lock_state()

	{

	GET_RWNO_TID(,r12);

	asm("ldr	r12, [r12, #%a0]" : : "i" _FOFF(TSubScheduler,iKernLockCount));

	asm("cmp	r12, #0 ");

	asm("beq	1f ");

	__ASM_CRASH();

	asm("1:		");

	GET_RWNO_TID(,r12);

	asm("ldr	r12, [r12, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));

	asm("ldr	r12, [r12, #%a0]" : : "i" _FOFF(NThread,iHeldFastMutex));

	asm("cmp	r12, #0 ");

	asm("beq	2f ");

	__ASM_CRASH();

	asm("2:		");

	GET_RWNO_TID(,r12);

	asm("ldr	r12, [r12, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));

	asm("ldr	r12, [r12, #%a0]" : : "i" _FOFF(NThread,iCsCount));

	asm("cmp	r12, #0 ");

	asm("beq	3f ");

	__ASM_CRASH();

	asm("3:		");

	GET_RWNO_TID(,r12);

	asm("ldr	r12, [r12, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));

	asm("ldrh	r12, [r12, #%a0]" : : "i" _FOFF(NSchedulable,iFreezeCpu));

	asm("cmp	r12, #0 ");

	asm("beq	4f ");

	__ASM_CRASH();

	asm("4:		");

	__JUMP(,lr);

	}

#endif

//#define	__RECORD_STATE__

#ifdef __RECORD_STATE__

#define RECORD_STATE()				\

	asm("ldr r3, [sp, #68] ");		\

	asm("mov r1, sp ");				\

	asm("bic r12, sp, #0xff ");		\

	asm("bic r12, r12, #0xf00 ");	\

	asm("add r12, r12, #24 ");		\

	asm("tst r3, #0x0f ");			\

	asm("addne pc, pc, #12 ");		\

	asm("ldmia r1!, {r2-r11} ");	\

	asm("stmia r12!, {r2-r11} ");	\

	asm("ldmia r1!, {r2-r9} ");		\

	asm("stmia r12!, {r2-r9} ")

#define RECORD_STATE_EXC()			\

	asm("ldr r3, [sp, #92] ");		\

	asm("mov r12, sp ");			\

	asm("bic lr, sp, #0xff ");		\

	asm("bic lr, lr, #0xf00 ");		\

	asm("tst r3, #0x0f ");			\

	asm("addne pc, pc, #12 ");		\

	asm("ldmia r12!, {r0-r11} ");	\

	asm("stmia lr!, {r0-r11} ");	\

	asm("ldmia r12!, {r0-r11} ");	\

	asm("stmia lr!, {r0-r11} ");

#else

#define RECORD_STATE()

#define RECORD_STATE_EXC()

#endif

#ifdef __USER_MEMORY_GUARDS_ENABLED__

// This macro can be invoked just before a return-from-exception instruction

// It will cause an UNDEF exception if we're about to return to user mode with UMG still on

#define	USER_MEMORY_GUARD_CHECK()											\

	asm("stmfd	sp!, {lr}");												\

	asm("ldr	lr, [sp, #8]");						/* lr<-future CPSR	*/	\

	USER_MEMORY_GUARD_ASSERT_OFF_IF_MODE_USR(lr);							\

	asm("ldmfd	sp!, {lr}");

#else

#define	USER_MEMORY_GUARD_CHECK()

#endif

/******************************************************************************

 * SWI Handler

 ******************************************************************************/

extern "C" __NAKED__ void __ArmVectorSwi()

	{

	// IRQs disabled, FIQs enabled here

	__ASM_CLI();							// all interrupts off

	SRSDBW(MODE_SVC);						// save return address and return CPSR to supervisor stack

	asm("sub	sp, sp, #%a0" : : "i" _FOFF(SThreadExcStack,iR15));

	asm("stmia	sp, {r0-r14}^ ");			// save R0-R12, R13_usr, R14_usr

	asm("mov	r4, #%a0" : : "i" ((TInt)SThreadExcStack::ESvc));

	USER_MEMORY_GUARD_ON_IF_MODE_USR(r11);

	asm("ldr	r12, [lr, #-4] ");			// get SWI opcode

	GET_RWNO_TID(,r11);

	asm("str	r4, [sp, #%a0]" : : "i" _FOFF(SThreadExcStack,iExcCode));	// word describing exception type

	asm("movs	r12, r12, lsl #9 ");		// 512*SWI number into r12

	asm("adr	lr, fast_swi_exit ");

	asm("ldr	r9, [r11, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));

	asm("bcc	slow_swi ");				// bit 23=0 for slow/unprot

	asm("mov	r1, r9 ");

	asm("beq	wait_for_any_request ");	// special case for Exec::WaitForAnyRequest

	asm("ldr	r2, [r1, #%a0]" : : "i" _FOFF(NThread,iFastExecTable));

	asm("ldr	r3, [r2], r12, lsr #7 ");	// r3=limit, r2->dispatch table entry

	asm("cmp	r3, r12, lsr #9 ");			// r3-SWI number

	asm("ldrhi	pc, [r2] ");				// if SWI number valid, call kernel function

	asm("mvn	r12, #0 ");					// put invalid SWI number into r12

	asm("b		slow_swi ");				// go through slow SWI routine to call invalid SWI handler

#ifndef __FAST_SEM_MACHINE_CODED__

	asm("wait_for_any_request: ");

	__ASM_STI();							// all interrupts on

#else

	asm(".global exec_wfar_wait ");

	asm("exec_wfar_wait: ");

	asm("mov	r2, #1 ");

	asm("str	r2, [r11, #%a0]" : : "i" _FOFF(TSubScheduler,iKernLockCount));			// else lock the kernel

	__ASM_STI();

	asm("strb	r2, [r11, #%a0]" : : "i" _FOFF(TSubScheduler,iRescheduleNeededFlag));	// and set the reschedule flag

	asm("bl "	CSM_ZN10TScheduler10RescheduleEv );	// reschedule

	asm(".global exec_wfar_resched_return ");

	asm("exec_wfar_resched_return: ");

	asm("ldr	r4, [r3, #%a0]" : : "i" _FOFF(NThreadBase,iUserModeCallbacks));

	asm("mov	r9, r3 ");

	// need to send any outstanding reschedule IPIs

	asm("cmp	r12, #0 ");

	asm("blne " CSM_CFUNC(send_accumulated_resched_ipis));

	asm(".global exec_wfar_finish ");

	asm("exec_wfar_finish: ");

	asm("mrs	r1, spsr ");

	asm("tst	r1, #0x0f ");

	asm("bne	fast_swi_exit2 ");			// not returning to user mode; in this case we don't run callbacks

											// and the UMG was not changed on entry so we don't reset it

#ifdef __CHECK_LOCK_STATE__

	asm("bl "	CSM_CFUNC(check_lock_state));

#endif

	asm("cmp	r4, #3 ");					// callbacks?

	asm("blhs	run_user_mode_callbacks ");	// run them; NB trashes most registers (R0-R12, R14)

	USER_MEMORY_GUARD_OFF(,r12,r12);		// because we're returning to user mode

	asm("b		fast_swi_exit2 ");

#endif

	asm("fast_swi_exit: ");

#if defined(__CHECK_LOCK_STATE__) || defined(__USER_MEMORY_GUARDS_ENABLED__)

	asm("mrs	r12, spsr ");

	asm("tst	r12, #0x0f ");

	asm("bne	fast_swi_exit2 ");			// not returning to user mode; in this case we don't run callbacks

											// and the UMG was not changed on entry so we don't restore it

#ifdef __CHECK_LOCK_STATE__

	asm("bl "	CSM_CFUNC(check_lock_state));

#endif

	USER_MEMORY_GUARD_OFF(,r12,r12);		// because we're returning to user mode

#endif

	asm("fast_swi_exit2: ");

	RECORD_STATE();

	asm("ldmib	sp, {r1-r14}^ ");			// restore R1-R12, R13_usr, R14_usr

	asm("nop ");							// don't access banked register immediately after

	asm("add	sp, sp, #%a0" : : "i" _FOFF(SThreadExcStack,iR15));

	USER_MEMORY_GUARD_CHECK();				// check UMG is off if returning to user mode

	RFEIAW(13);								// restore PC and CPSR - return from Exec function

	asm("slow_swi: ");						// IRQs and FIQs off here

	__ASM_STI();							// all interrupts on

	asm("ldr	r4, [r9, #%a0]" : : "i" _FOFF(NThread,iSlowExecTable));

	asm("mrs	r11, spsr ");				// spsr_svc into r11

	asm("adr	lr, slow_swi_exit ");

	asm("ldr	r5, [r4, #-12] ");			// r5=limit

	asm("add	r6, r4, r12, lsr #6 ");		// r6->dispatch table entry

	asm("cmp	r5, r12, lsr #9 ");			// r5-SWI number

	asm("ldmhiia r6, {r5,r6} ");			// if SWI number OK, flags into r5, function addr into r6

	asm("ldrls	pc, [r4, #-8] ");			// if SWI number invalid, call invalid handler, returning to slow_swi_exit below

	// Acquire system lock if necessary: warning - any scratch registers modified after __ArmVectorSwi()

	// function preamble will be restored after call to NKern::LockSystem() with stale values.

	asm("tst	r5, #%a0" : : "i" ((TInt)KExecFlagClaim));	// claim system lock?

	asm("beq	slow_swi_no_wait ");						// skip if not

	asm("bl "	CSM_ZN5NKern10LockSystemEv );

	asm("ldmia	sp, {r0-r3} ");								// reload original values

	asm("slow_swi_no_wait: ");

	// Check to see if extra arguments are needed.  Needs to be placed after call to NKern::LockSystem()

	// above, as r2 is reloaded with its original value by the ldmia instruction above

	asm("tst	r5, #%a0" : : "i" ((TInt)KExecFlagExtraArgMask));	// extra arguments needed?

	asm("addne	r2, sp, #%a0" : : "i" _FOFF(SThreadExcStack,iR4));	// if so, point r2 at saved registers on stack

	asm("tst	r5, #%a0" : : "i" ((TInt)KExecFlagPreprocess));	// preprocess (handle lookup)? can use r4, r7, r8, r12, r0

	asm("mov	lr, pc ");

	asm("ldrne	pc, [r4, #-4] ");			// call preprocess handler if required

	asm("orr	r5, r9, r5, lsr #30 ");		// r5 = current NThread pointer with bits 0,1 = (flags & (KExecFlagRelease|KExecFlagClaim))>>30

	asm("mov	lr, pc ");

	__JUMP(,	r6);						// call exec function, preserve r5,r11

	asm("str	r0, [sp, #%a0]" : : "i" _FOFF(SThreadExcStack,iR0));	// save return value

	asm("bic	r9, r5, #3 ");				// r9 = current NThread pointer

	asm("tst	r5, #%a0" : : "i" ((TInt)KExecFlagRelease>>30));		// release system lock?

	asm("blne "	CSM_ZN5NKern12UnlockSystemEv );

	asm("slow_swi_exit: ");

	__ASM_CLI();

	asm("ldr	r4, [r9, #%a0]" : : "i" _FOFF(NThreadBase,iUserModeCallbacks));

	asm("tst	r11, #0x0f ");				// returning to user mode?

	asm("bne	slow_swi_exit2 ");			// not returning to user mode; in this case we don't run callbacks

											// and the UMG was not changed on entry so we don't reset it

#ifdef __CHECK_LOCK_STATE__

	asm("bl "	CSM_CFUNC(check_lock_state));

#endif

	asm("cmp	r4, #3 ");					// callbacks?

	asm("blhs	run_user_mode_callbacks ");	// run them; NB trashes most registers (R0-R12, R14)

	USER_MEMORY_GUARD_OFF(,r12,r12);		// because we're returning to user mode

	asm("slow_swi_exit2: ");

	RECORD_STATE();

	asm("ldmia	sp, {r0-r14}^ ");			// R0=return value, restore R1-R12, R13_usr, R14_usr

	asm("nop ");							// don't access banked register immediately after

	asm("add	sp, sp, #%a0" : : "i" _FOFF(SThreadExcStack,iR15));

	USER_MEMORY_GUARD_CHECK();				// check UMG is off if returning to user mode

	RFEIAW(13);								// restore PC and CPSR - return from Exec function

	}

/******************************************************************************

 * IRQ Postamble

 * This routine is called after the IRQ has been dispatched

 * Enter in mode_sys

 * R4->TSubScheduler, R6->GIC CPU interface

 * For nested IRQ, R0-R12, R14_sys, return address, return CPSR are on top

 *	 of the mode_sys (i.e. current) stack

 * For non-nested IRQ, registers are saved on top of mode_svc stack and

 *	 pointed to by R5 in the order:

 *	 R5->R0 ... R12 R13_usr R14_usr <spare> PC CPSR

 *   and if user memory guards are active, R8 = saved DACR

 ******************************************************************************/

extern "C" __NAKED__ void __ArmVectorIrq()

	{

	// Interrupts may be enabled here

#ifdef BTRACE_CPU_USAGE

	asm("ldr	r10, __BTraceCpuUsageFilter ");

#endif

	asm("ldr	r7, [r4, #%a0]" : : "i" _FOFF(TSubScheduler, iSSX.iIrqNestCount));

	asm("ldrb	r0, [r4, #%a0]" : : "i" _FOFF(TSubScheduler, iEventHandlersPending));

	__DATA_MEMORY_BARRIER_Z__(r2);

#ifdef BTRACE_CPU_USAGE

	asm("ldrb	r10, [r10] ");

#endif

	asm("subs	r7, r7, #1 ");

	asm("bpl	nested_irq_exit ");

	asm("cmp	r0, #0 ");

	asm("beq	no_event_handlers ");

	asm("mov	r0, r4 ");

	asm("bl		run_event_handlers ");

	asm("no_event_handlers: ");

#ifdef __USER_MEMORY_GUARDS_ENABLED__

	asm("mov	r11, r8 ");

#endif

	asm("ldr	r8, [r5, #%a0]" : : "i" _FOFF(SThreadExcStack,iCPSR));	// r8 = interrupted cpsr

	asm("ldr	r0, [r4, #%a0]" : : "i" _FOFF(TSubScheduler, iKernLockCount));

	__ASM_CLI();							// all interrupts off

	asm("and	r2, r8, #0x1f ");

	asm("ldr	r1, [r4, #%a0]" : : "i" _FOFF(TSubScheduler, iRescheduleNeededFlag));

	asm("cmp	r2, #0x10 ");				// interrupted mode_usr ?

	asm("cmpne	r2, #0x13 ");				// if not, interrupted mode_svc ?

	asm("cmpeq	r0, #0 ");					// if mode_usr or mode_svc, is kernel locked?

	asm("str	r7, [r4, #%a0]" : : "i" _FOFF(TSubScheduler, iSSX.iIrqNestCount));

	asm("bne	irq_kernel_locked_exit ");	// if neither or if kernel locked, exit immediately

	asm("cmp	r1, #0 ");					// If not, IDFCs/reschedule pending?

	asm("beq	irq_kernel_locked_exit ");	// if not, exit

	asm("mov	r1, #1 ");

	asm("str	r1, [r4, #%a0]" : : "i" _FOFF(TSubScheduler, iKernLockCount));	// lock the kernel

	__ASM_STI_MODE(MODE_SVC);				// mode_svc, interrupts on

	// Saved registers are on top of mode_svc stack

	// reschedule - this also switches context if necessary

	// enter this function in mode_svc, interrupts on, kernel locked

	// exit this function in mode_svc, all interrupts off, kernel unlocked

	asm("irq_do_resched: ");

	asm("stmfd	sp!, {r11,lr} ");			// save user memory guard state, lr_svc

	asm("bl "	CSM_ZN10TScheduler10RescheduleEv);	// return with R3->current thread

	asm(".global irq_resched_return ");

	asm("irq_resched_return: ");

	asm("ldr	r8, [sp, #%a0]" : : "i" (_FOFF(SThreadExcStack,iCPSR)+8));		// have UMG, lr_svc on stack as well

	asm("ldr	r4, [r3, #%a0]" : : "i" _FOFF(NThreadBase,iUserModeCallbacks));

	asm("mov	r9, r3 ");

	// need to send any outstanding reschedule IPIs

	asm("cmp	r12, #0 ");

	asm("blne " CSM_CFUNC(send_accumulated_resched_ipis));

	asm("tst	r8, #0x0f ");				// returning to user mode?

	asm("bne	irq_post_resched_exit ");	// if not, we don't check locks or run callbacks

#ifdef __CHECK_LOCK_STATE__

	asm("bl "	CSM_CFUNC(check_lock_state));

#endif

	asm("cmp	r4, #3 ");					// callbacks?

	asm("blhs	run_user_mode_callbacks ");	// run them; NB trashes most registers (R0-R12, R14)

	asm("irq_post_resched_exit: ");

	asm("ldmfd	sp!, {r11,lr} ");			// restore UMG, lr_svc

	USER_MEMORY_GUARD_RESTORE(r11,r12);

	RECORD_STATE();

	asm("ldmia	sp, {r0-r14}^ ");			// restore R0-R12, R13_usr, R14_usr

	asm("nop ");							// don't access banked register immediately after

	asm("add	sp, sp, #%a0" : : "i" _FOFF(SThreadExcStack,iR15));

	USER_MEMORY_GUARD_CHECK();				// check UMG is off if returning to user mode

	RFEIAW(13);								// restore PC and CPSR - return from Exec function

	asm("irq_kernel_locked_exit: ");

#ifdef __CHECK_LOCK_STATE__

	asm("tst	r8, #0x0f ");

	asm("bleq " CSM_CFUNC(check_lock_state));

#endif

#ifdef BTRACE_CPU_USAGE

	asm("cmp	r10, #0 ");

	asm("blne	btrace_irq_exit ");

#endif

	USER_MEMORY_GUARD_RESTORE(r11,r12);

	__ASM_CLI_MODE(MODE_SVC);				// mode_svc, interrupts off

	RECORD_STATE();

	asm("ldmia	sp, {r0-r14}^ ");			// restore R0-R12, R13_usr, R14_usr

	asm("nop ");							// don't access banked register immediately after

	asm("add	sp, sp, #%a0" : : "i" _FOFF(SThreadExcStack,iR15));

	USER_MEMORY_GUARD_CHECK();				// check UMG is off if returning to user mode

	RFEIAW(13);								// restore PC and CPSR - return from Exec function

	asm("nested_irq_exit: ");

	__ASM_CLI1();

	asm("str	r7, [r4, #%a0]" : : "i" _FOFF(TSubScheduler, iSSX.iIrqNestCount));

#ifdef BTRACE_CPU_USAGE

	asm("cmp	r10, #0 ");

	asm("blne	btrace_irq_exit ");

#endif

	asm("ldmia	sp!, {r0-r12,r14} ");		// restore r0-r12, r14_sys

	USER_MEMORY_GUARD_CHECK();				// check UMG is off if returning to user mode

	RFEIAW(13);								// restore PC and CPSR - return from Exec function

	asm("__BTraceCpuUsageFilter: ");

	asm(".word	%a0" : : "i" ((TInt)&BTraceData.iFilter[BTrace::ECpuUsage]));

	}

/******************************************************************************

 * FIQ Postamble

 * This routine is called after the FIQ has been dispatched

 * spsr_fiq, r0-r3 are unmodified

 * Return address is on the top of the FIQ stack -- except that if user memory

 * guards are in use, the saved DACR was pushed afterwards, so that's on top

 * of the stack and the return address is next

 ******************************************************************************/

extern "C" __NAKED__ void __ArmVectorFiq()

	{

#ifdef __FAULT_ON_FIQ__

	asm(".word 0xe7f10f10 ");

#endif

	// IRQs and FIQs disabled here

	// r0-r7 are unaltered from when FIQ occurred

	GET_RWNO_TID(,r9);

	asm("mrs	r8, spsr ");				// check interrupted mode

	asm("and	r10, r8, #0x1f ");

	asm("cmp	r10, #0x10 ");				// check for mode_usr

	asm("ldr	r11, [r9, #%a0]" : : "i" _FOFF(TSubScheduler, iKernLockCount));

	asm("cmpne	r10, #0x13 ");				// or mode_svc

	asm("ldreq	r10, [r9, #%a0]" : : "i" _FOFF(TSubScheduler, iRescheduleNeededFlag));

	asm("cmpeq	r11, #0 ");					// and check if kernel locked

	asm("bne	FiqExit0 ");				// if wrong mode or kernel locked, return immediately

	asm("cmp	r10, #0 ");					// check if reschedule needed

	asm("beq	FiqExit0 ");				// if not, return from interrupt

	// we interrupted mode_usr or mode_svc, kernel unlocked, reschedule needed

#ifdef __USER_MEMORY_GUARDS_ENABLED__

	asm("ldr	r8, [sp], #4 ");			// r8_fiq = UMG state

#endif

	asm("ldr	r14, [sp], #4 ");			// r14_fiq = return address

	asm("add	r11, r11, #1 ");

	asm("str	r11, [r9, #%a0]" : : "i" _FOFF(TSubScheduler, iKernLockCount));	// lock the kernel

	SRSDBW(MODE_SVC);						// save return address and return CPSR to supervisor stack

	CPSCHM(MODE_SVC);						// switch to mode_svc, all interrupts off

	asm("sub	sp, sp, #%a0" : : "i" _FOFF(SThreadExcStack,iR15));

	asm("stmia	sp, {r0-r14}^ ");			// save R0-R12, R13_usr, R14_usr

	asm("mov	r0, #%a0" : : "i" ((TInt)SThreadExcStack::EFiq));

#ifdef __USER_MEMORY_GUARDS_ENABLED__

	CPSCHM(MODE_FIQ);						// back to mode_fiq, all interrupts off

	asm("mov	r1, r8 ");					// retrieve UMG state

	CPSCHM(MODE_SVC);						// switch to mode_svc, all interrupts off

	asm("mov	r11, r1 ");					// UMG state into R11

#endif

	asm("str	r0, [sp, #%a0]" : : "i" _FOFF(SThreadExcStack,iExcCode));	// word describing exception type

	__ASM_STI();							// interrupts on

	asm("b		irq_do_resched ");			// do reschedule and return from interrupt

	asm("FiqExit0: ");

#ifdef BTRACE_CPU_USAGE

	asm("ldr	r8, __BTraceCpuUsageFilter ");

	asm("ldrb	r8, [r8] ");

	asm("cmp	r8, #0 ");

	asm("beq	1f ");

	asm("stmfd	sp!, {r0-r3} ");

	asm("bl		btrace_fiq_exit ");

	asm("ldmfd	sp!, {r0-r3} ");

	asm("1: ");

#endif

#ifdef __USER_MEMORY_GUARDS_ENABLED__

	asm("ldr	r8, [sp], #4 ");

#endif

	USER_MEMORY_GUARD_RESTORE(r8,r12);

	asm("ldmfd	sp!, {pc}^ ");				// return from interrupt

	asm("__TheScheduler: ");

	asm(".word TheScheduler ");

	}

/******************************************************************************

 * Abort handler

 * This routine is called in response to a data abort, prefetch abort or

 * undefined instruction exception.

 ******************************************************************************/

extern "C" __NAKED__ void __ArmVectorAbortData()

	{

	__ASM_CLI();							// disable all interrupts

	asm("sub	lr, lr, #8 ");				// lr now points to aborted instruction

	SRSDBW(		MODE_ABT);					// save it along with aborted CPSR

	asm("sub	sp, sp, #%a0" : : "i" _FOFF(SThreadExcStack,iR15));

	asm("stmia	sp, {r0-r14}^ ");			// save R0-R12, R13_usr, R14_usr

	GET_RWNO_TID(,r11);

	asm("mov	r1, #%a0 " : : "i" ((TInt)EArmExceptionDataAbort));

	asm("str	r1, [sp, #%a0]" : : "i" _FOFF(SThreadExcStack,iExcCode));	// word describing exception type

	asm("handle_exception: ");

	// We are in exception mode (abt/und) with registers stacked as follows:

	// R13_abt/R13_und -> R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_usr R14_usr ExcCode PC CPSR

#if defined(__CPU_ARM_HAS_WORKING_CLREX)

	CLREX									// reset exclusive monitor 	

#elif defined(__CPU_ARM_HAS_LDREX_STREX)

	STREX(12,0,13);							// dummy STREX to reset exclusivity monitor

#endif

#if 0	// minimum-dependency exception handling

	asm("ldr	r0, [sp, #%a0]" : : "i" _FOFF(SThreadExcStack,iCPSR));

	asm("mrs	r4, cpsr ");

	asm("orr	r1, r0, #0xc0 ");

	asm("msr	cpsr, r1 ");				// back to original mode

	asm("mov	r2, sp ");

	asm("mov	r3, lr ");

	asm("msr	cpsr, r4 ");				// back to mode_abt or mode_und

	asm("stmfd	sp!, {r2,r3} ");			// now have R13 R14 R0-R12 R13_usr R14_usr ExcCode PC CPSR

	asm("mrc	p15, 0, r1, c5, c0, 0 ");	// DFSR

	asm("mrc	p15, 0, r2, c5, c0, 1 ");	// IFSR

	asm("mrc	p15, 0, r0, c6, c0, 0 ");	// DFAR

	asm("stmfd	sp!, {r0-r2} ");			// now have DFAR DFSR IFSR R13 R14 R0-R12 R13_usr R14_usr ExcCode PC CPSR

	asm("mov	r0, sp ");

	asm(".extern hw_init_exc ");

	asm("bl		hw_init_exc ");

	asm("add	sp, sp, #20 ");

	asm("ldmia	sp, {r0-r14}^ ");			// restore R0-R12, R13_usr, R14_usr

	asm("nop ");							// don't access banked register immediately after

	asm("add	sp, sp, #%a0" : : "i" _FOFF(SThreadExcStack,iR15));

	RFEIAW(13);								// restore PC and CPSR - return from Exec function

#endif

	asm("ldr	r0, [sp, #%a0]" : : "i" _FOFF(SThreadExcStack,iCPSR));