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// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// eka\include\kernel\kernboot.h
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// Interface between bootstrap and kernel
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// This header file should contain only POD structures with members having
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// only the following types:
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// TInt8, TUint8, TInt16, TUint16, TInt32, TUint32, TInt64, TUint64
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// TInt, TUint, TLinAddr, T* where T is an alphanumeric string
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// If TInt64/TUint64 are used, manual padding should be used to guarantee
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// that these start on an 8 byte boundary.
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//
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// WARNING: This file contains some APIs which are internal and are subject
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// to change without notice. Such APIs should therefore not be used
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// outside the Kernel and Hardware Services package.
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//
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#ifndef __KERNBOOT_H__
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#define __KERNBOOT_H__
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/**
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The part of SSuperPageBase class.
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Holds the stack base address and the stack size of IRQ, FIQ, Undefined & Abort cpu modes.
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@see SSuperPageBase
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@publishedPartner
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@released
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*/
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struct TStackInfo
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{
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void* iIrqStackBase; /**< Stack base address of IRQ CPU mode*/
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TInt iIrqStackSize; /**< Stack size of IRQ CPU mode*/
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void* iFiqStackBase; /**< Stack base address of FIQ CPU mode*/
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TInt iFiqStackSize; /**< Stack size of FIQ CPU mode*/
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void* iUndStackBase; /**< Stack base address of Undefined CPU mode*/
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TInt iUndStackSize; /**< Stack size of Undefined CPU mode*/
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void* iAbtStackBase; /**< Stack base address of Abort CPU mode*/
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TInt iAbtStackSize; /**< Stack size of Abort CPU mode*/
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};
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/** The part of the super page used by the bootstrap.
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Optional fields in this structure may be set to
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KSuperPageAddressFieldUndefined (-1) if not used during boot time.
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Current optional fields are: iSmrData
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@publishedPartner
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@released
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*/
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struct SSuperPageBase
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{
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TInt iRamDriveSize; /**< @internalComponent */ // current size of RAM drive
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TInt iTotalRomSize; /**< total size of ROM */
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TInt iTotalRamSize; /**< total size of RAM, excluding simulated ROM*/
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TLinAddr iPageDir; /**< @internalComponent */ // address of page directory
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TInt iKernelFault; /**< flag to indicate reboot due to fault - cleared by bootstrap on hardware reset*/
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TLinAddr iRamBootData; /**< @internalComponent */ // pointer to RAM description
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TLinAddr iRomBootData; /**< @internalComponent */ // pointer to ROM description
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TLinAddr iBootTable; /**< @internalComponent */ // used temporarily by bootstrap
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TLinAddr iCodeBase; /**< @internalComponent */ // used temporarily by bootstrap
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TUint32 iBootFlags; /**< @internalComponent */ // used temporarily by bootstrap
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TLinAddr iBootAlloc; /**< @internalComponent */ // used temporarily by bootstrap
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TLinAddr iMachineData; /**< pointer to variant specific information*/
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TUint iActiveVariant; /**< Active Hardware Variant Descriptor*/
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TLinAddr iPrimaryEntry; /**< pointer to TRomEntry for active kernel image*/
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TInt iInitialHeapSize; /**< initial size of kernel stack/heap chunk*/
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TInt iDebugPort; /**< debug port number*/
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TUint iCpuId; /**< CPU identifier*/
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TLinAddr iUncachedAddress; /**< Virtual address mapped to uncached memory if required*/
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TLinAddr iRootDirList; /**< pointer to ROM root directory list (for extension ROMs)*/
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TInt iHwStartupReason; /**< startup reason code (hardware dependent)*/
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TLinAddr iKernelLimit; /**< @internalComponent */ // linear address of top of kernel region (direct model only)
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TLinAddr iRamBase; /**< @internalComponent */ // linear address base of RAM (direct model only)
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TLinAddr iDCacheFlushArea; /**< linear address of DCache flush area (direct model only)*/
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TLinAddr iDCacheFlushWrap; /**< size of DCache flush area (direct model only)*/
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TLinAddr iAltDCacheFlushArea; /**< linear address of alternate DCache flush area (direct model only)*/
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TLinAddr iAltDCacheFlushWrap; /**< size of alternate DCache flush area (direct model only)*/
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TStackInfo iStackInfo; /**< base address & size of Irq & Fiq CPU mode's stacks*/
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TLinAddr iArmL2CacheBase; /**< base address of the external cache controller (e.g. L210, L220,...)*/
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TUint32 iRomHeaderPhys; /**< @internalComponent */
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TUint32 iAPBootPagePhys; /**< @internalComponent */
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TUint32 iAPBootPageLin; /**< @internalComponent */
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TUint32 iAPBootPageDirPhys; /**< @internalComponent */
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TUint32 iSmrData; /**< address of shadow memory region information block (SMRIB), optional field set by bootstrap PSL */
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TInt iReserved[26]; /**< reserved for the future use*/
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};
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/** Descriptor for a single contiguous block of RAM
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@publishedPartner
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@released
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*/
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struct SRamBank
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{
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TUint32 iBase; /**< physical base address of block*/
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TUint32 iSize; /**< size of block in bytes*/
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};
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/** Maximum number of RAM zones.
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@see SRamZone
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@publishedPartner
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@released
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*/
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const TUint KMaxRamZones = 64;
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/** Flag to indicate that no further fixed pages can be allocated into a
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particular RAM zone.
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This flag still allows device drivers to allocate pages into a RAM zone
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using Epoc::ZoneAllocPhysicalRam().
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@publishedPartner
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@released
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*/
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const TUint KRamZoneFlagNoFixed = 0x01;
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/** Flag to indicate that no further movable pages can be allocated into a
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particular RAM zone.
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@publishedPartner
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@released
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*/
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const TUint KRamZoneFlagNoMovable = 0x02;
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/** Flag to indicate that no further discardable pages can be allocated into a
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particular RAM zone.
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@publishedPartner
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@released
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*/
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const TUint KRamZoneFlagNoDiscard = 0x04;
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/** RAM zone flag that ensures no further pages are allocated into
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a RAM zone.
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@publishedPartner
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@released
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*/
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const TUint KRamZoneFlagNoAlloc = 0x80;
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/** RAM zone flag mask that ensures only discardable pages are allocated into
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a RAM zone.
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This flag mask still allows device drivers to allocate pages into a RAM zone
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using Epoc::ZoneAllocPhysicalRam().
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@publishedPartner
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@released
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*/
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const TUint KRamZoneFlagDiscardOnly = KRamZoneFlagNoFixed | KRamZoneFlagNoMovable;
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/** RAM zone flag to indicate that a RAM zone should be temporarily blocked
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from further allocations.
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@internalComponent
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*/
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const TUint KRamZoneFlagTmpBlockAlloc = 0x08000000;
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/** RAM zone flag to indicate that a RAM zone has been inspected by a general defrag.
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@internalComponent
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*/
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const TUint KRamZoneFlagGenDefrag = 0x20000000;
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/** RAM zone flag to indicate that a RAM zone should not be allocated
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into by a general defrag operation.
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@internalComponent
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*/
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const TUint KRamZoneFlagGenDefragBlock = 0x10000000;
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/** RAM zone flag to indicate that a RAM zone is being claimed and therefore shouldn't
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be allocated into.
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@internalComponent
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*/
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const TUint KRamZoneFlagClaiming = 0x40000000;
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/** RAM zone flag that is used to detect RAM zone activity.
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@internalComponent
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*/
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const TUint KRamZoneFlagMark = 0x80000000;
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/**
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A mask of RAM zone flag bits that can not be set by device driver or base port code.
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@internalComponent
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*/
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const TUint KRamZoneFlagInvalid = ~(KRamZoneFlagNoAlloc | KRamZoneFlagNoFixed | KRamZoneFlagNoMovable | KRamZoneFlagNoDiscard);
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/** Value that cannot be used for a RAM zone ID.
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@publishedPartner
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@released
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*/
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const TUint KRamZoneInvalidId = 0xffffffff;
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/** Specifies a single RAM zone and its properties.
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@publishedPartner
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@released
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*/
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struct SRamZone
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{
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TUint32 iBase; /**< Physical base address of the RAM zone*/
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TUint32 iSize; /**< Size of the RAM zone in bytes, the end of the SRamZone array is indicated by a RAM zone size of zero*/
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TUint iId; /**< ID number of the RAM zone*/
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TUint iFlags; /**< Zone flags - specify whether the RAM zone should be reserved for contiguous buffer or h/w use etc*/
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TUint8 iPref; /**< Preference value for this RAM zone, lower preference RAM zones are used first*/
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TUint8 iReserved[3];/**< @internalComponent*/
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};
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/** Defines an SRamZone struct object.
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@see SRamZone
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@publishedPartner
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@released
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*/
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#define __SRAM_ZONE(aBase, aSize, aId, aFlags, aPref) \
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{aBase, aSize, aId, aFlags, aPref, {0,0,0,},}
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/** Ends the RAM zone declarations by defining the iSize of a RAM zone as zero.
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@see SRamZone
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@publishedPartner
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@released
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*/
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#define __SRAM_ZONE_END {0,0,0,0,0,{0,0,0,},}
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/** Descriptor for a single contiguous block of ROM
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@publishedPartner
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@released
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*/
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class SRomBank
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{
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public:
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TUint32 iBase; /**< physical base address of block*/
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TUint32 iSize; /**< size of block*/
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TUint8 iWidth; /**< log2(bus width in bits)*/
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TUint8 iType; /**< device type*/
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TUint8 iSpeedR; /**< random access speed*/
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TUint8 iSpeedS; /**< sequential access speed*/
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TUint32 iLinBase; /**< linear base address of block*/
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};
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/* Enumeration for type of ROM
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@publishedPartner
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@released
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*/
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enum TRomType
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{
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ERomTypeXIPFlash = 0x01,
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ERomTypeXIP = 0x02,
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ERomTypeRamAsRom = 0x04
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};
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/* CPU ID field
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@publishedPartner
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@released
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*/
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const TUint KCpuIdISS = 0x80000000u; // Instruction Set Simulator
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/* Boot flags field
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@publishedPartner
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@released
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*/
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const TUint32 KBootFlagRunFromRAM = 0x80000000u;
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/** This cosnstant is used in optional fields in the SSuperPageBase struct
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(e.g. iSmrData) to indicate the field is not used/set during the boot process.
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This maybe because the baseport does not support this field/feature or that
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the feature is not enabled/available as determined by bootstrap PSL in
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InitialiseHardware() at boot time.
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@publishedPartner
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@prototype
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*/
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const TUint32 KSuperPageAddressFieldUndefined = 0xffffffff;
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/** Descriptor for a single contiguous block of RAM initialised with a SMR
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image. Typically these are initialised by the pre-OS loader.
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The structure represents an entry in the Shadow Memory Region Information
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Block (SMRIB). SMRIB is pointed to by the SuperPage iSmrData member.
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SMRIB ends with zero sized SSmrBank entry. The iSize is in bytes and must be a
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multiple of 4Kb.
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@publishedPartner
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@prototype
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*/
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struct SSmrBank
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{
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TUint32 iBase; /**< physical base address of block */
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TUint32 iSize; /**< size of block in bytes, multiple of 4Kb */
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TUint32 iPayloadUID; /**< SMR Payload UID */
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TUint32 iPayloadFlags; /**< SMR Payload flags */
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};
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/** Structure defining the SMR partition image header format.
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The SMR Rom Header has a fixed size of 256 bytes.
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@publishedPartner
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@prototype
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*/
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struct SSmrRomHeader
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{
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TUint32 iFingerPrint[2]; /**< "SMR_PART" [0]=0x5F524D53[1]=0x54524150 */
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TUint32 iReserved0; /**< Reserved for future use, always 0 */
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TUint32 iImageVersion; /**< Version number of image format */
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TUint32 iImageSize; /**< Size in bytes of the image (hdr+payload)*/
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TUint32 iImageTimestamp; /**< Image creation time in seconds since midnight Jan 1st 1970 */
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TUint32 iReserved1; /**< Reserved for future use, always 0 */
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TUint32 iPayloadChecksum; /**< Calculated checksum at build time */
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TUint32 iPayloadUID; /**< Alloc'd UID identifying payload content */
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TUint32 iPayloadFlags; /**< Payload specific flag word */
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TUint32 iReserved[54]; /**< Reserved for future use, always 0 */
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};
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#endif
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