author | Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com> |
Mon, 18 Jan 2010 21:31:10 +0200 | |
changeset 45 | 329ab0095843 |
parent 43 | 96e5fb8b040d |
child 153 | 1f2940c968a9 |
permissions | -rw-r--r-- |
43
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
1 |
// Copyright (c) 2006-2009 Nokia Corporation and/or its subsidiary(-ies). |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
2 |
// All rights reserved. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
3 |
// This component and the accompanying materials are made available |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
4 |
// under the terms of the License "Eclipse Public License v1.0" |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
5 |
// which accompanies this distribution, and is available |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
6 |
// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
7 |
// |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
8 |
// Initial Contributors: |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
9 |
// Nokia Corporation - initial contribution. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
10 |
// |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
11 |
// Contributors: |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
12 |
// |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
13 |
// Description: |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
14 |
// Cache maintenance primitives on ARMv7 (and later) platforms. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
15 |
// eka\kernel\arm\cachev7.cia |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
16 |
// |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
17 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
18 |
#include <e32cia.h> |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
19 |
#include <arm.h> |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
20 |
#include "cache_maintenance.h" |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
21 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
22 |
#if defined(__CPU_ARMV7) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
23 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
24 |
// These constant defines LoC & LoU position in Cache Level ID Register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
25 |
const TInt KLoCMask = 0x07000000; // LoC field in CLIDR |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
26 |
const TInt KLoCShift = 24; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
27 |
#if defined(__SMP__) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
28 |
// LoUIS seems to be not implemented on cortex_a9. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
29 |
//const TInt KLoUMask = 0x00e00000; // LoUIS field in CLIDR |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
30 |
//const TInt KLoUShift = 21; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
31 |
const TInt KLoUMask = 0x38000000; // LoUU field in CLIDR |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
32 |
const TInt KLoUShift = 27; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
33 |
#else |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
34 |
const TInt KLoUMask = 0x38000000; // LoUU field in CLIDR |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
35 |
const TInt KLoUShift = 27; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
36 |
#endif |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
37 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
38 |
// These constant defines max values in Cache Size Id Register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
39 |
const TInt KAssocMax = 0x3ff; //Max value of associativity (10 bits reserved for this) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
40 |
const TInt KNumSetMax = 0x7fff; //MaxValue for Set Number (15 bits resrved for this) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
41 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
42 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
43 |
__NAKED__ TUint32 InternalCache::TypeRegister() |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
44 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
45 |
asm("mrc p15, 0, r0, c0, c0, 1 "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
46 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
47 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
48 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
49 |
__NAKED__ TUint32 InternalCache::LevelIDRegister() |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
50 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
51 |
asm("mrc p15, 1, r0, c0, c0, 1 "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
52 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
53 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
54 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
55 |
__NAKED__ TUint32 InternalCache::SizeIdRegister(TUint32 /*aType*/, TUint32 /*aLevel*/) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
56 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
57 |
asm("orr r0, r1, lsl #1"); // r0 = entry for Cache Size Selection Reg. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
58 |
asm("mcr p15, 2, r0, c0, c0, 0 "); // set Cache Size Selection Register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
59 |
asm("mov r1, #0"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
60 |
ARM_ISBSY; // prefetchFlush to sync the change to the CacheSizeID reg |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
61 |
asm("mrc p15, 1, r0, c0, c0, 0 "); // read Cache Size Id Register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
62 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
63 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
64 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
65 |
__NAKED__ void InternalCache::DrainBuffers() |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
66 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
67 |
// Drain write buffer is rather archaic vocabulary from ARMv5. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
68 |
// On ARMv7, data & instruction sync barriers apply. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
69 |
asm("mov r0, #0 "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
70 |
ARM_DSBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
71 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
72 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
73 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
74 |
asm("__DCacheInfoPoU: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
75 |
asm(".word %a0" : : "i" ((TInt)&InternalCache::Info[KCacheInfoD_PoU])); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
76 |
asm("__DCacheInfoPoC: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
77 |
asm(".word %a0" : : "i" ((TInt)&InternalCache::Info[KCacheInfoD])); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
78 |
asm("__ICacheInfo: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
79 |
asm(".word %a0" : : "i" ((TInt)&InternalCache::Info[KCacheInfoI])); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
80 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
81 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
82 |
__NAKED__ void InternalCache::IMB_CacheLine(TLinAddr /*aAddr*/) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
83 |
{ |
45
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
84 |
//--Determine base address of cache line--// |
43
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
85 |
asm("ldr r2, __DCacheInfoPoU "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
86 |
asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength)); |
45
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
87 |
asm("sub ip, r3, #1"); // ip=mask for offset within line |
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
88 |
asm("bic r2, r0, ip"); // r2 = cache line base |
43
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
89 |
|
45
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
90 |
DCCMVAU(r2); // Clean DCache line to Point-of-Unification |
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
91 |
ARM_DSBSY; // Data Sync Barrier (system) |
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
92 |
ICIMVAU(r2); // Invalidate Instruction cache line to Point-of-Unification |
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
93 |
BPIMVA(r0); // Invalidate aAddr from Branch Predictor Array |
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
94 |
asm("add r0, r0, #2"); |
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
95 |
BPIMVA(r0); // Invalidate possible THUMB instuction at aAddr+2 from Branch Predictor Array |
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
96 |
ARM_DSBSH; // Data Sync Barrier (system) |
329ab0095843
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
43
diff
changeset
|
97 |
ARM_ISBSY; // Instruction Sync Barrier |
43
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
98 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
99 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
100 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
101 |
__NAKED__ void InternalCache::Invalidate_ICache_Region(TLinAddr /*aBase*/, TUint /*aSize*/) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
102 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
103 |
asm("ldr r2, __ICacheInfo "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
104 |
asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
105 |
asm("sub ip, r3, #1 "); // ip=mask for offset within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
106 |
asm("and ip, ip, r0 "); // ip=offset of start address within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
107 |
asm("add r1, r1, ip "); // add this to the size |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
108 |
asm("sub ip, r3, #1 "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
109 |
asm("bic r0, r0, ip "); // round base address down to start of line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
110 |
asm("add r1, r1, ip "); // round size up |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
111 |
asm("1: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
112 |
asm("subs r1, r1, r3 "); // decrement size by line length |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
113 |
asm("bcc 2f "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
114 |
ICIMVAU(r0); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
115 |
asm("2: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
116 |
asm("add r0, r0, r3 "); // step address on |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
117 |
asm("bhi 1b "); // loop if more lines |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
118 |
#ifdef __SMP__ // } |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
119 |
BPIALLIS; // } flush branch predictor |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
120 |
#else // } |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
121 |
BPIALL; // } |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
122 |
#endif |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
123 |
ARM_DSBSH; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
124 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
125 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
126 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
127 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
128 |
__NAKED__ void InternalCache::Invalidate_ICache_All() |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
129 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
130 |
#ifdef __SMP__ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
131 |
ICIALLUIS; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
132 |
// BPIALLIS; NOT NEEDED SINCE IT IS INCORPORATED IN ICIALLUIS |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
133 |
ARM_DSBSH; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
134 |
#else |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
135 |
ICIALLU; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
136 |
// BPIALL; NOT NEEDED SINCE IT IS INCORPORATED IN ICIALLU |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
137 |
ARM_DSBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
138 |
#endif |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
139 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
140 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
141 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
142 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
143 |
__NAKED__ void InternalCache::Invalidate_DCache_Region(TLinAddr /*aBase*/, TUint /*aSize*/) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
144 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
145 |
asm("ldr r2, __DCacheInfoPoC "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
146 |
asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
147 |
asm("sub ip, r3, #1 "); // ip=mask for offset within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
148 |
asm("and ip, ip, r0 "); // ip=offset of start address within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
149 |
asm("add r1, r1, ip "); // add this to the size |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
150 |
asm("sub ip, r3, #1 "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
151 |
asm("bic r0, r0, ip "); // round base address down to start of line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
152 |
asm("add r1, r1, ip "); // round size up |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
153 |
asm("1: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
154 |
asm("subs r1, r1, r3 "); // decrement size by line length |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
155 |
asm("bcc 2f "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
156 |
DCIMVAC(r0); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
157 |
asm("2: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
158 |
asm("add r0, r0, r3 "); // step address on |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
159 |
asm("bhi 1b "); // loop if more lines |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
160 |
ARM_DSBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
161 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
162 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
163 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
164 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
165 |
__NAKED__ void InternalCache::Clean_DCache_Region(TLinAddr /*aBase*/, TUint /*aSize*/) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
166 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
167 |
asm("ldr r2, __DCacheInfoPoC "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
168 |
asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
169 |
asm("sub ip, r3, #1 "); // ip=mask for offset within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
170 |
asm("and ip, ip, r0 "); // ip=offset of start address within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
171 |
asm("add r1, r1, ip "); // add this to the size |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
172 |
asm("sub ip, r3, #1 "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
173 |
asm("bic r0, r0, ip "); // round base address down to start of line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
174 |
asm("add r1, r1, ip "); // round size up |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
175 |
asm("1: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
176 |
asm("subs r1, r1, r3 "); // decrement size by line length |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
177 |
asm("bcc 2f "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
178 |
DCCMVAC(r0); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
179 |
#if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571771_FIXED) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
180 |
DCCMVAC(r13); // ARM Cortex-A9 MPCore erratum 571771 workaround |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
181 |
// Execute additional cache clean to enforce barrier on other CPUs |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
182 |
#endif |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
183 |
asm("2: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
184 |
asm("add r0, r0, r3 "); // step address on |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
185 |
asm("bhi 1b "); // loop if more lines |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
186 |
ARM_DSBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
187 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
188 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
189 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
190 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
191 |
__NAKED__ void InternalCache::Clean_PoU_DCache_Region(TLinAddr /*aBase*/, TUint /*aSize*/) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
192 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
193 |
asm("ldr r2, __DCacheInfoPoU "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
194 |
asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
195 |
asm("sub ip, r3, #1 "); // ip=mask for offset within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
196 |
asm("and ip, ip, r0 "); // ip=offset of start address within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
197 |
asm("add r1, r1, ip "); // add this to the size |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
198 |
asm("sub ip, r3, #1 "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
199 |
asm("bic r0, r0, ip "); // round base address down to start of line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
200 |
asm("add r1, r1, ip "); // round size up |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
201 |
asm("1: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
202 |
asm("subs r1, r1, r3 "); // decrement size by line length |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
203 |
asm("bcc 2f "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
204 |
DCCMVAU(r0); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
205 |
asm("2: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
206 |
asm("add r0, r0, r3 "); // step address on |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
207 |
asm("bhi 1b "); // loop if more lines |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
208 |
ARM_DSBSH; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
209 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
210 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
211 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
212 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
213 |
__NAKED__ void InternalCache::CleanAndInvalidate_DCache_Region(TLinAddr, TUint) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
214 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
215 |
asm("ldr r2, __DCacheInfoPoC "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
216 |
asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
217 |
asm("sub ip, r3, #1 "); // ip=mask for offset within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
218 |
asm("and ip, ip, r0 "); // ip=offset of start address within line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
219 |
asm("add r1, r1, ip "); // add this to the size |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
220 |
asm("sub ip, r3, #1 "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
221 |
asm("bic r0, r0, ip "); // round base address down to start of line |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
222 |
asm("add r1, r1, ip "); // round size up |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
223 |
asm("1: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
224 |
asm("subs r1, r1, r3 "); // decrement size by line length |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
225 |
asm("bcc 2f "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
226 |
DCCIMVAC(r0); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
227 |
#if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571771_FIXED) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
228 |
DCCIMVAC(r13); // ARM Cortex-A9 MPCore erratum 571771 workaround |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
229 |
// Execute additional cache clean to enforce barrier on other CPUs |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
230 |
#endif |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
231 |
asm("2: "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
232 |
asm("add r0, r0, r3 "); // step address on |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
233 |
asm("bhi 1b "); // loop if more lines |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
234 |
ARM_DSBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
235 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
236 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
237 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
238 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
239 |
__NAKED__ void InternalCache::Clean_DCache_All() |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
240 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
241 |
//NOTE: ON SMP THIS ONLY CLEANS THE CURRENT CPU CACHE, NOT OTHER CPU CACHES |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
242 |
asm("stmfd sp!, {r4-r5,r7,r9-r11} "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
243 |
asm("mrc p15, 1, r0, c0, c0, 1"); // Read CLIDR |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
244 |
asm("ands r3, r0, #%a0" : : "i" ((TInt)KLoCMask)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
245 |
asm("mov r3, r3, lsr #%a0" : : "i" ((TInt)(KLoCShift-1))); // r3 = LoC << 1 |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
246 |
asm("beq 5f"); // ... and finish if LoC is zero |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
247 |
asm("mov r10, #0"); // r10 = 0 (the current cache level) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
248 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
249 |
asm("1:"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
250 |
asm("add r2, r10, r10, lsr #1"); // Work out 3xcachelevel |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
251 |
asm("mov r1, r0, LSR r2"); // bottom 3 bits are the Ctype for this level |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
252 |
asm("and r1, r1, #7"); // get those 3 bits alone |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
253 |
asm("cmp r1, #2"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
254 |
asm("blt 4f"); // no cache or only instruction cache at this level |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
255 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
256 |
asm("mrs r4, cpsr"); // Disable interrupts while accessing CS Selection Reg & |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
257 |
CPSIDAIF; // CS ID Reg. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
258 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
259 |
asm("mcr p15, 2, r10, c0, c0, 0"); // write the Cache Size selection register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
260 |
asm("mov r1, #0"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
261 |
ARM_ISBSY; // ISB to sync the change to the CacheSizeID reg |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
262 |
asm("mrc p15, 1, r1, c0, c0, 0"); // reads current Cache Size ID register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
263 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
264 |
asm("msr cpsr_c, r4"); // Restore interrupts |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
265 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
266 |
asm("and r2, r1, #7"); // extract the line length field |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
267 |
asm("add r2, r2, #4"); // add 4 for the line length offset (log2 16 bytes) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
268 |
asm("ldr r4, =%a0" : : "i" ((TInt)KAssocMax)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
269 |
asm("ands r4, r4, r1, lsr #3"); // R4 is the max number on the way size (right aligned) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
270 |
CLZ(5,4); // R5 is the bit position of the way size increment |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
271 |
asm("ldr r7, =%a0" : : "i" ((TInt)KNumSetMax)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
272 |
asm("ands r7, r7, r1, lsr #13"); // R7 is the max number of the index size (right aligned) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
273 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
274 |
asm("2:"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
275 |
asm("mov r9, r4"); // R9 working copy of the max way size (right aligned) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
276 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
277 |
asm("3:"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
278 |
asm("orr r11, r10, r9, lsl r5"); // factor in the way number and cache number into R11 |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
279 |
asm("orr r11, r11, r7, lsl r2"); // factor in the index number |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
280 |
DCCSW(r11); // clean by set/way |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
281 |
asm("subs r9, r9, #1"); // decrement the way number |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
282 |
asm("bge 3b"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
283 |
asm("subs r7, r7, #1"); // decrement the index |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
284 |
asm("bge 2b"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
285 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
286 |
asm("4:"); // SKIP |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
287 |
asm("add r10, r10, #2"); // increment the cache number |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
288 |
asm("cmp r3, r10"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
289 |
asm("bgt 1b"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
290 |
ARM_DSBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
291 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
292 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
293 |
asm("5:"); // FINISHED |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
294 |
asm("ldmfd sp!, {r4-r5,r7,r9-r11} "); // restore registers |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
295 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
296 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
297 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
298 |
__NAKED__ void InternalCache::CleanAndInvalidate_DCache_All() |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
299 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
300 |
//NOTE: ON SMP THIS ONLY CLEANS AND INVALIDATES THE CURRENT CPU CACHE, NOT OTHER CPU CACHES |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
301 |
asm("stmfd sp!, {r4-r5,r7,r9-r11} "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
302 |
asm("mrc p15, 1, r0, c0, c0, 1"); // Read CLIDR |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
303 |
asm("ands r3, r0, #%a0" : : "i" ((TInt)KLoCMask)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
304 |
asm("mov r3, r3, lsr #%a0" : : "i" ((TInt)(KLoCShift-1))); // r3 = LoC << 1 |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
305 |
asm("beq 5f"); // ... and finish if LoC is zero |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
306 |
asm("mov r10, #0"); // r10 = 0 (the current cache level) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
307 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
308 |
asm("1:"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
309 |
asm("add r2, r10, r10, lsr #1"); // Work out 3xcachelevel |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
310 |
asm("mov r1, r0, LSR r2"); // bottom 3 bits are the Ctype for this level |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
311 |
asm("and r1, r1, #7"); // get those 3 bits alone |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
312 |
asm("cmp r1, #2"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
313 |
asm("blt 4f"); // no cache or only instruction cache at this level |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
314 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
315 |
asm("mrs r4, cpsr"); // Disable interrupts while accessing CS Selection Reg & |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
316 |
CPSIDAIF; // CS ID Reg. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
317 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
318 |
asm("mcr p15, 2, r10, c0, c0, 0"); // write the Cache Size selection register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
319 |
asm("mov r1, #0"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
320 |
ARM_ISBSY; // ISB to sync the change to the CacheSizeID reg |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
321 |
asm("mrc p15, 1, r1, c0, c0, 0"); // reads current Cache Size ID register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
322 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
323 |
asm("msr cpsr_c, r4"); // Restore interrupts |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
324 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
325 |
asm("and r2, r1, #7"); // extract the line length field |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
326 |
asm("add r2, r2, #4"); // add 4 for the line length offset (log2 16 bytes) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
327 |
asm("ldr r4, =%a0" : : "i" ((TInt)KAssocMax)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
328 |
asm("ands r4, r4, r1, lsr #3"); // R4 is the max number on the way size (right aligned) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
329 |
CLZ(5,4); // R5 is the bit position of the way size increment |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
330 |
asm("ldr r7, =%a0" : : "i" ((TInt)KNumSetMax)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
331 |
asm("ands r7, r7, r1, lsr #13"); // R7 is the max number of the index size (right aligned) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
332 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
333 |
asm("2:"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
334 |
asm("mov r9, r4"); // R9 working copy of the max way size (right aligned) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
335 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
336 |
asm("3:"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
337 |
asm("orr r11, r10, r9, lsl r5"); // factor in the way number and cache number into R11 |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
338 |
asm("orr r11, r11, r7, lsl r2"); // factor in the index number |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
339 |
DCCISW(r11); // clean and invalidate by set/way |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
340 |
asm("subs r9, r9, #1"); // decrement the way number |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
341 |
asm("bge 3b"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
342 |
asm("subs r7, r7, #1"); // decrement the index |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
343 |
asm("bge 2b"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
344 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
345 |
asm("4:"); // SKIP |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
346 |
asm("add r10, r10, #2"); // increment the cache number |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
347 |
asm("cmp r3, r10"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
348 |
asm("bgt 1b"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
349 |
ARM_DSBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
350 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
351 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
352 |
asm("5:"); // FINISHED |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
353 |
asm("ldmfd sp!, {r4-r5,r7,r9-r11} "); // restore registers |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
354 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
355 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
356 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
357 |
__NAKED__ void InternalCache::Clean_PoU_DCache_All() |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
358 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
359 |
// NOTE: ON SMP THIS ONLY CLEANS THE CURRENT CPU CACHE, NOT OTHER CPU CACHES |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
360 |
asm("stmfd sp!, {r4-r5,r7,r9-r11} "); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
361 |
asm("mrc p15, 1, r0, c0, c0, 1"); // Read CLIDR |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
362 |
asm("ands r3, r0, #%a0" : : "i" ((TInt)KLoUMask)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
363 |
asm("mov r3, r3, lsr #%a0" : : "i" ((TInt)(KLoUShift-1))); // r3 = LoU << 1 |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
364 |
asm("beq 5f"); // ... and finish if LoU is zero |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
365 |
asm("mov r10, #0"); // r10 = 0 (the current cache level) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
366 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
367 |
asm("1:"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
368 |
asm("add r2, r10, r10, lsr #1"); // Work out 3xcachelevel |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
369 |
asm("mov r1, r0, LSR r2"); // bottom 3 bits are the Ctype for this level |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
370 |
asm("and r1, r1, #7"); // get those 3 bits alone |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
371 |
asm("cmp r1, #2"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
372 |
asm("blt 4f"); // no cache or only instruction cache at this level |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
373 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
374 |
asm("mrs r4, cpsr"); // Disable interrupts while accessing CS Selection Reg & |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
375 |
CPSIDAIF; // CS ID Reg. |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
376 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
377 |
asm("mcr p15, 2, r10, c0, c0, 0"); // write the Cache Size selection register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
378 |
asm("mov r1, #0"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
379 |
ARM_ISBSY; // ISB to sync the change to the CacheSizeID reg |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
380 |
asm("mrc p15, 1, r1, c0, c0, 0"); // reads current Cache Size ID register |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
381 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
382 |
asm("msr cpsr_c, r4"); // Restore interrupts |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
383 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
384 |
asm("and r2, r1, #7"); // extract the line length field |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
385 |
asm("add r2, r2, #4"); // add 4 for the line length offset (log2 16 bytes) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
386 |
asm("ldr r4, =%a0" : : "i" ((TInt)KAssocMax)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
387 |
asm("ands r4, r4, r1, lsr #3"); // R4 is the max number on the way size (right aligned) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
388 |
CLZ(5,4); // R5 is the bit position of the way size increment |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
389 |
asm("ldr r7, =%a0" : : "i" ((TInt)KNumSetMax)); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
390 |
asm("ands r7, r7, r1, lsr #13"); // R7 is the max number of the index size (right aligned) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
391 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
392 |
asm("2:"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
393 |
asm("mov r9, r4"); // R9 working copy of the max way size (right aligned) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
394 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
395 |
asm("3:"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
396 |
asm("orr r11, r10, r9, lsl r5"); // factor in the way number and cache number into R11 |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
397 |
asm("orr r11, r11, r7, lsl r2"); // factor in the index number |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
398 |
DCCSW(r11); // clean by set/way |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
399 |
asm("subs r9, r9, #1"); // decrement the way number |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
400 |
asm("bge 3b"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
401 |
asm("subs r7, r7, #1"); // decrement the index |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
402 |
asm("bge 2b"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
403 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
404 |
asm("4:"); // SKIP |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
405 |
asm("add r10, r10, #2"); // increment the cache number |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
406 |
asm("cmp r3, r10"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
407 |
asm("bgt 1b"); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
408 |
ARM_DSBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
409 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
410 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
411 |
asm("5:"); // FINISHED |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
412 |
asm("ldmfd sp!, {r4-r5,r7,r9-r11} "); // restore registers |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
413 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
414 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
415 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
416 |
#if defined(__BROADCAST_ISB) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
417 |
__NAKED__ void T_ISB_IPI::ISBIsr(TGenericIPI* /*aPtr*/) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
418 |
{ |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
419 |
ARM_ISBSY; |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
420 |
__JUMP(,lr); |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
421 |
} |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
422 |
#endif //defined(__BROADCAST_ISB) |
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
423 |
|
96e5fb8b040d
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
diff
changeset
|
424 |
#endif //#if defined(__CPU_ARMV7) |