| author | Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com> |
| Tue, 06 Jul 2010 15:50:07 +0300 | |
| changeset 201 | 43365a9b78a3 |
| parent 90 | 947f0dc9f7a8 |
| permissions | -rw-r--r-- |
| 0 | 1 |
// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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// All rights reserved. |
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// This component and the accompanying materials are made available |
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// under the terms of the License "Eclipse Public License v1.0" |
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// which accompanies this distribution, and is available |
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// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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// |
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// Initial Contributors: |
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// Nokia Corporation - initial contribution. |
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// |
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// Contributors: |
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// |
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// Description: |
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// e32\nkernsmp\arm\ncthrd.cpp |
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// |
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// |
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// NThreadBase member data |
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#define __INCLUDE_NTHREADBASE_DEFINES__ |
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#define __INCLUDE_REG_OFFSETS__ |
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#include <arm.h> |
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#include <arm_gic.h> |
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#include <arm_scu.h> |
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#include <arm_tmr.h> |
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#include <nk_irq.h> |
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const TInt KNThreadMinStackSize = 0x100; // needs to be enough for interrupt + reschedule stack |
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// Called by a thread when it first runs |
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extern "C" void __StartThread(); |
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// Initialise CPU registers |
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extern void initialiseState(TInt aCpu, TSubScheduler* aSS); |
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extern "C" void ExcFault(TAny*); |
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extern TUint32 __mpid(); |
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extern void InitTimestamp(TSubScheduler* aSS, SNThreadCreateInfo& aInfo); |
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TInt NThread::Create(SNThreadCreateInfo& aInfo, TBool aInitial) |
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{
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// Assert ParameterBlockSize is not negative and is a multiple of 8 bytes |
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__NK_ASSERT_ALWAYS((aInfo.iParameterBlockSize&0x80000007)==0); |
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__NK_ASSERT_ALWAYS(aInfo.iStackBase && aInfo.iStackSize>=aInfo.iParameterBlockSize+KNThreadMinStackSize); |
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TInt cpu = -1; |
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TSubScheduler* ss = 0; |
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new (this) NThread; |
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if (aInitial) |
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{
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cpu = __e32_atomic_add_ord32(&TheScheduler.iNumCpus, 1); |
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aInfo.iCpuAffinity = cpu; |
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// OK since we can't migrate yet |
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ss = &TheSubSchedulers[cpu]; |
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ss->iCurrentThread = this; |
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ss->iDeferShutdown = 0; |
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iRunCount.i64 = UI64LIT(1); |
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iActiveState = 1; |
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__KTRACE_OPT(KBOOT,DEBUGPRINT("Init: cpu=%d ss=%08x", cpu, ss));
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if (cpu) |
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{
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initialiseState(cpu,ss); |
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ArmLocalTimer& T = LOCAL_TIMER; |
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T.iWatchdogDisable = E_ArmTmrWDD_1; |
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T.iWatchdogDisable = E_ArmTmrWDD_2; |
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T.iTimerCtrl = 0; |
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T.iTimerIntStatus = E_ArmTmrIntStatus_Event; |
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T.iWatchdogCtrl = 0; |
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T.iWatchdogIntStatus = E_ArmTmrIntStatus_Event; |
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NIrq::HwInit2AP(); |
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T.iTimerCtrl = E_ArmTmrCtrl_IntEn | E_ArmTmrCtrl_Reload | E_ArmTmrCtrl_Enable; |
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__e32_atomic_ior_ord32(&TheScheduler.iThreadAcceptCpus, 1<<cpu); |
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__e32_atomic_ior_ord32(&TheScheduler.iIpiAcceptCpus, 1<<cpu); |
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__e32_atomic_ior_ord32(&TheScheduler.iCpusNotIdle, 1<<cpu); |
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__e32_atomic_add_ord32(&TheScheduler.iCCRequestLevel, 1); |
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__KTRACE_OPT(KBOOT,DEBUGPRINT("AP MPID=%08x",__mpid()));
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} |
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else |
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{
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Arm::DefaultDomainAccess = Arm::Dacr(); |
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Arm::ModifyCar(0, 0x00f00000); // full access to CP10, CP11 |
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Arm::DefaultCoprocessorAccess = Arm::Car(); |
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} |
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} |
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TInt r=NThreadBase::Create(aInfo,aInitial); |
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if (r!=KErrNone) |
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return r; |
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if (!aInitial) |
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{
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aInfo.iPriority = 0; |
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TLinAddr stack_top = (TLinAddr)iStackBase + (TLinAddr)iStackSize; |
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TLinAddr sp = stack_top; |
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TUint32 pb = (TUint32)aInfo.iParameterBlock; |
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SThreadStackStub* tss = 0; |
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if (aInfo.iParameterBlockSize) |
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{
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tss = (SThreadStackStub*)stack_top; |
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--tss; |
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tss->iExcCode = SThreadExcStack::EStub; |
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tss->iR15 = 0; |
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tss->iCPSR = 0; |
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sp = (TLinAddr)tss; |
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sp -= (TLinAddr)aInfo.iParameterBlockSize; |
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wordmove((TAny*)sp, aInfo.iParameterBlock, aInfo.iParameterBlockSize); |
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pb = (TUint32)sp; |
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tss->iPBlock = sp; |
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} |
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SThreadInitStack* tis = (SThreadInitStack*)sp; |
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--tis; |
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memclr(tis, sizeof(SThreadInitStack)); |
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iSavedSP = (TLinAddr)tis; |
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#ifdef __CPU_HAS_VFP |
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tis->iR.iFpExc = VFP_FPEXC_THRD_INIT; |
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#endif |
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tis->iR.iCar = Arm::DefaultCoprocessorAccess; |
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tis->iR.iDacr = Arm::DefaultDomainAccess; |
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tis->iR.iSpsrSvc = MODE_SVC; |
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tis->iR.iSPRschdFlg = TLinAddr(&tis->iX) | 1; |
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tis->iR.iR15 = (TUint32)&__StartThread; |
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tis->iX.iR0 = pb; |
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tis->iX.iR4 = (TUint32)this; |
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tis->iX.iR11 = stack_top; |
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tis->iX.iExcCode = SThreadExcStack::EInit; |
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tis->iX.iR15 = (TUint32)aInfo.iFunction; |
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tis->iX.iCPSR = MODE_SVC; |
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} |
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else |
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{
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NKern::EnableAllInterrupts(); |
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#if defined(__CPU_ARM_HAS_GLOBAL_TIMER_BLOCK) && defined(__NKERN_TIMESTAMP_USE_SCU_GLOBAL_TIMER__) |
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if (cpu == 0) |
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{
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// start global timer if necessary |
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ArmGlobalTimer& GT = GLOBAL_TIMER; |
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if (!(GT.iTimerCtrl & E_ArmGTmrCtrl_TmrEnb)) |
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{
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// timer not currently enabled |
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GT.iTimerCtrl = 0; |
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__e32_io_completion_barrier(); |
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GT.iTimerStatus = E_ArmGTmrStatus_Event; |
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__e32_io_completion_barrier(); |
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GT.iTimerCountLow = 0; |
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GT.iTimerCountHigh = 0; |
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__e32_io_completion_barrier(); |
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GT.iTimerCtrl = E_ArmGTmrCtrl_TmrEnb; // enable timer with prescale factor of 1 |
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__e32_io_completion_barrier(); |
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} |
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} |
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#endif |
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// start local timer |
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ArmLocalTimer& T = LOCAL_TIMER; |
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T.iTimerCtrl = E_ArmTmrCtrl_IntEn | E_ArmTmrCtrl_Reload | E_ArmTmrCtrl_Enable; |
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// Initialise timestamp |
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InitTimestamp(ss, aInfo); |
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} |
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AddToEnumerateList(); |
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InitLbInfo(); |
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#ifdef BTRACE_THREAD_IDENTIFICATION |
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BTrace4(BTrace::EThreadIdentification,BTrace::ENanoThreadCreate,this); |
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#endif |
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return KErrNone; |
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} |
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/** Called from generic layer when thread is killed asynchronously. |
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For ARM, save reason for last user->kernel switch (if any) so that user |
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context can be accessed from EDebugEventRemoveThread hook. Must be done |
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before forcing the thread to exit as this alters the saved return address |
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which is used to figure out where the context is saved. |
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@pre kernel locked |
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@post kernel locked |
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*/ |
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void NThreadBase::OnKill() |
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{
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} |
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/** Called from generic layer when thread exits. |
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For ARM, save that if the thread terminates synchronously the last |
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user->kernel switch was an exec call. Do nothing if non-user thread or |
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reason already saved in OnKill(). |
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@pre kernel locked |
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@post kernel locked |
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@see OnKill |
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*/ |
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void NThreadBase::OnExit() |
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{
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} |
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void DumpExcInfo(TArmExcInfo& a) |
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{
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DEBUGPRINT("Exc %1d Cpsr=%08x FAR=%08x FSR=%08x",a.iExcCode,a.iCpsr,a.iFaultAddress,a.iFaultStatus);
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DEBUGPRINT(" R0=%08x R1=%08x R2=%08x R3=%08x",a.iR0,a.iR1,a.iR2,a.iR3);
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DEBUGPRINT(" R4=%08x R5=%08x R6=%08x R7=%08x",a.iR4,a.iR5,a.iR6,a.iR7);
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DEBUGPRINT(" R8=%08x R9=%08x R10=%08x R11=%08x",a.iR8,a.iR9,a.iR10,a.iR11);
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DEBUGPRINT("R12=%08x R13=%08x R14=%08x R15=%08x",a.iR12,a.iR13,a.iR14,a.iR15);
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DEBUGPRINT("R13Svc=%08x R14Svc=%08x SpsrSvc=%08x",a.iR13Svc,a.iR14Svc,a.iSpsrSvc);
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TInt irq = NKern::DisableAllInterrupts(); |
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TSubScheduler& ss = SubScheduler(); |
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NThreadBase* ct = ss.iCurrentThread; |
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TInt inc = TInt(ss.iSSX.iIrqNestCount); |
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TInt cpu = ss.iCpuNum; |
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TInt klc = ss.iKernLockCount; |
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NKern::RestoreInterrupts(irq); |
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DEBUGPRINT("Thread %T, CPU %d, KLCount=%d, IrqNest=%d", ct, cpu, klc, inc);
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} |
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void DumpFullRegSet(SFullArmRegSet& a) |
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{
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SNormalRegs& r = a.iN; |
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DEBUGPRINT("MODE_USR:");
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DEBUGPRINT(" R0=%08x R1=%08x R2=%08x R3=%08x", r.iR0, r.iR1, r.iR2, r.iR3);
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DEBUGPRINT(" R4=%08x R5=%08x R6=%08x R7=%08x", r.iR4, r.iR5, r.iR6, r.iR7);
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DEBUGPRINT(" R8=%08x R9=%08x R10=%08x R11=%08x", r.iR8, r.iR9, r.iR10, r.iR11);
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DEBUGPRINT("R12=%08x R13=%08x R14=%08x R15=%08x", r.iR12, r.iR13, r.iR14, r.iR15);
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DEBUGPRINT("CPSR=%08x", r.iFlags);
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DEBUGPRINT("MODE_FIQ:");
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DEBUGPRINT(" R8=%08x R9=%08x R10=%08x R11=%08x", r.iR8Fiq, r.iR9Fiq, r.iR10Fiq, r.iR11Fiq);
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DEBUGPRINT("R12=%08x R13=%08x R14=%08x SPSR=%08x", r.iR12Fiq, r.iR13Fiq, r.iR14Fiq, r.iSpsrFiq);
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DEBUGPRINT("MODE_IRQ:");
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DEBUGPRINT("R13=%08x R14=%08x SPSR=%08x", r.iR13Irq, r.iR14Irq, r.iSpsrIrq);
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DEBUGPRINT("MODE_SVC:");
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DEBUGPRINT("R13=%08x R14=%08x SPSR=%08x", r.iR13Svc, r.iR14Svc, r.iSpsrSvc);
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DEBUGPRINT("MODE_ABT:");
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DEBUGPRINT("R13=%08x R14=%08x SPSR=%08x", r.iR13Abt, r.iR14Abt, r.iSpsrAbt);
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DEBUGPRINT("MODE_UND:");
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DEBUGPRINT("R13=%08x R14=%08x SPSR=%08x", r.iR13Und, r.iR14Und, r.iSpsrUnd);
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// DEBUGPRINT("MODE_MON:");
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|
242 |
// DEBUGPRINT("R13=%08x R14=%08x SPSR=%08x", r.iR13Mon, r.iR14Mon, r.iSpsrMon);
|
|
243 |
||
244 |
SAuxiliaryRegs& aux = a.iA; |
|
245 |
DEBUGPRINT("TEEHBR=%08x CPACR=%08x", aux.iTEEHBR, aux.iCPACR);
|
|
246 |
||
247 |
SBankedRegs& b = a.iB[0]; |
|
248 |
DEBUGPRINT(" SCTLR=%08x ACTLR=%08x PRRR=%08x NMRR=%08x", b.iSCTLR, b.iACTLR, b.iPRRR, b.iNMRR);
|
|
249 |
DEBUGPRINT(" DACR=%08x TTBR0=%08x TTBR1=%08x TTBCR=%08x", b.iDACR, b.iTTBR0, b.iTTBR1, b.iTTBCR);
|
|
250 |
DEBUGPRINT(" VBAR=%08x FCSEID=%08x CTXIDR=%08x", b.iVBAR, b.iFCSEIDR, b.iCTXIDR);
|
|
251 |
DEBUGPRINT("Thread ID RWRW=%08x RWRO=%08x RWNO=%08x", b.iRWRWTID, b.iRWROTID, b.iRWNOTID);
|
|
252 |
DEBUGPRINT(" DFSR=%08x DFAR=%08x IFSR=%08x IFAR=%08x", b.iDFSR, b.iDFAR, b.iIFSR, b.iIFAR);
|
|
253 |
DEBUGPRINT(" ADFSR=%08x AIFSR=%08x", b.iADFSR, b.iAIFSR);
|
|
254 |
#ifdef __CPU_HAS_VFP |
|
255 |
DEBUGPRINT("FPEXC %08x", a.iMore[0]);
|
|
256 |
#endif |
|
257 |
DEBUGPRINT("ExcCode %08x", a.iExcCode);
|
|
258 |
} |
|
259 |
||
260 |
||
261 |
#define CONTEXT_ELEMENT_UNDEFINED(val) \ |
|
262 |
{ \
|
|
263 |
TArmContextElement::EUndefined, \ |
|
264 |
val, \ |
|
265 |
0, \ |
|
266 |
0 \ |
|
267 |
} |
|
268 |
||
269 |
#define CONTEXT_ELEMENT_EXCEPTION(reg) \ |
|
270 |
{ \
|
|
271 |
TArmContextElement::EOffsetFromStackTop, \ |
|
272 |
((sizeof(SThreadExcStack)-_FOFF(SThreadExcStack,reg))>>2), \ |
|
273 |
0, \ |
|
274 |
0 \ |
|
275 |
} |
|
276 |
||
277 |
#define CONTEXT_ELEMENT_RESCHED(reg) \ |
|
278 |
{ \
|
|
279 |
TArmContextElement::EOffsetFromSp, \ |
|
280 |
(_FOFF(SThreadReschedStack,reg)>>2), \ |
|
281 |
0, \ |
|
282 |
0 \ |
|
283 |
} |
|
284 |
||
285 |
#define CONTEXT_ELEMENT_RESCHED_SP() \ |
|
286 |
{ \
|
|
287 |
TArmContextElement::EOffsetFromSpBic3, \ |
|
288 |
(_FOFF(SThreadReschedStack,iSPRschdFlg)>>2), \ |
|
289 |
0, \ |
|
290 |
0 \ |
|
291 |
} |
|
292 |
||
293 |
#define CONTEXT_ELEMENT_RESCHED_SP_PLUS(offset) \ |
|
294 |
{ \
|
|
295 |
TArmContextElement::EOffsetFromSpBic3_1, \ |
|
296 |
(_FOFF(SThreadReschedStack,iSPRschdFlg)>>2), \ |
|
297 |
(offset), \ |
|
298 |
0 \ |
|
299 |
} |
|
300 |
||
301 |
#define CONTEXT_ELEMENT_RESCHED_SP_OFFSET(offset) \ |
|
302 |
{ \
|
|
303 |
TArmContextElement::EOffsetFromSpBic3_2, \ |
|
304 |
(_FOFF(SThreadReschedStack,iSPRschdFlg)>>2), \ |
|
305 |
(offset), \ |
|
306 |
0 \ |
|
307 |
} |
|
308 |
||
309 |
#define CONTEXT_ELEMENT_RESCHED_IRQ(reg) \ |
|
310 |
{ \
|
|
311 |
TArmContextElement::EOffsetFromSpBic3_2, \ |
|
312 |
(_FOFF(SThreadReschedStack,iSPRschdFlg)>>2), \ |
|
313 |
((_FOFF(SThreadIrqStack,reg)-sizeof(SThreadReschedStack))>>2), \ |
|
314 |
0 \ |
|
315 |
} |
|
316 |
||
317 |
#define CONTEXT_ELEMENT_RESCHED_INIT(reg) \ |
|
318 |
{ \
|
|
319 |
TArmContextElement::EOffsetFromSpBic3_2, \ |
|
320 |
(_FOFF(SThreadReschedStack,iSPRschdFlg)>>2), \ |
|
321 |
((_FOFF(SThreadInitStack,reg)-sizeof(SThreadReschedStack))>>2), \ |
|
322 |
0 \ |
|
323 |
} |
|
324 |
||
325 |
||
326 |
const TArmContextElement ContextTableException[] = |
|
327 |
{
|
|
328 |
CONTEXT_ELEMENT_EXCEPTION(iR0), |
|
329 |
CONTEXT_ELEMENT_EXCEPTION(iR1), |
|
330 |
CONTEXT_ELEMENT_EXCEPTION(iR2), |
|
331 |
CONTEXT_ELEMENT_EXCEPTION(iR3), |
|
332 |
CONTEXT_ELEMENT_EXCEPTION(iR4), |
|
333 |
CONTEXT_ELEMENT_EXCEPTION(iR5), |
|
334 |
CONTEXT_ELEMENT_EXCEPTION(iR6), |
|
335 |
CONTEXT_ELEMENT_EXCEPTION(iR7), |
|
336 |
CONTEXT_ELEMENT_EXCEPTION(iR8), |
|
337 |
CONTEXT_ELEMENT_EXCEPTION(iR9), |
|
338 |
CONTEXT_ELEMENT_EXCEPTION(iR10), |
|
339 |
CONTEXT_ELEMENT_EXCEPTION(iR11), |
|
340 |
CONTEXT_ELEMENT_EXCEPTION(iR12), |
|
341 |
CONTEXT_ELEMENT_EXCEPTION(iR13usr), |
|
342 |
CONTEXT_ELEMENT_EXCEPTION(iR14usr), |
|
343 |
CONTEXT_ELEMENT_EXCEPTION(iR15), |
|
344 |
CONTEXT_ELEMENT_EXCEPTION(iCPSR), |
|
345 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
346 |
}; |
|
347 |
||
348 |
const TArmContextElement ContextTableUndefined[] = |
|
349 |
{
|
|
350 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
351 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
352 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
353 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
354 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
355 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
356 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
357 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
358 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
359 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
360 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
361 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
362 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
363 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
364 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
365 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
366 |
CONTEXT_ELEMENT_UNDEFINED(EUserMode), |
|
367 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
368 |
}; |
|
369 |
||
370 |
// Table used for non dying threads which have been preempted by an interrupt |
|
371 |
// while in user mode. |
|
372 |
const TArmContextElement ContextTableUserInterrupt[] = |
|
373 |
{
|
|
374 |
CONTEXT_ELEMENT_EXCEPTION(iR0), |
|
375 |
CONTEXT_ELEMENT_EXCEPTION(iR1), |
|
376 |
CONTEXT_ELEMENT_EXCEPTION(iR2), |
|
377 |
CONTEXT_ELEMENT_EXCEPTION(iR3), |
|
378 |
CONTEXT_ELEMENT_EXCEPTION(iR4), |
|
379 |
CONTEXT_ELEMENT_EXCEPTION(iR5), |
|
380 |
CONTEXT_ELEMENT_EXCEPTION(iR6), |
|
381 |
CONTEXT_ELEMENT_EXCEPTION(iR7), |
|
382 |
CONTEXT_ELEMENT_EXCEPTION(iR8), |
|
383 |
CONTEXT_ELEMENT_EXCEPTION(iR9), |
|
384 |
CONTEXT_ELEMENT_EXCEPTION(iR10), |
|
385 |
CONTEXT_ELEMENT_EXCEPTION(iR11), |
|
386 |
CONTEXT_ELEMENT_EXCEPTION(iR12), |
|
387 |
CONTEXT_ELEMENT_EXCEPTION(iR13usr), |
|
388 |
CONTEXT_ELEMENT_EXCEPTION(iR14usr), |
|
389 |
CONTEXT_ELEMENT_EXCEPTION(iR15), |
|
390 |
CONTEXT_ELEMENT_EXCEPTION(iCPSR), |
|
391 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
392 |
}; |
|
393 |
||
394 |
// Table used for threads which have been preempted by an interrupt while in |
|
395 |
// supervisor mode in the SWI handler either before the return address was |
|
396 |
// saved or after the registers were restored. |
|
397 |
const TArmContextElement ContextTableSvsrInterrupt1[] = |
|
398 |
{
|
|
399 |
CONTEXT_ELEMENT_EXCEPTION(iR0), |
|
400 |
CONTEXT_ELEMENT_EXCEPTION(iR1), |
|
401 |
CONTEXT_ELEMENT_EXCEPTION(iR2), |
|
402 |
CONTEXT_ELEMENT_EXCEPTION(iR3), |
|
403 |
CONTEXT_ELEMENT_EXCEPTION(iR4), |
|
404 |
CONTEXT_ELEMENT_EXCEPTION(iR5), |
|
405 |
CONTEXT_ELEMENT_EXCEPTION(iR6), |
|
406 |
CONTEXT_ELEMENT_EXCEPTION(iR7), |
|
407 |
CONTEXT_ELEMENT_EXCEPTION(iR8), |
|
408 |
CONTEXT_ELEMENT_EXCEPTION(iR9), |
|
409 |
CONTEXT_ELEMENT_EXCEPTION(iR10), |
|
410 |
CONTEXT_ELEMENT_EXCEPTION(iR11), |
|
411 |
CONTEXT_ELEMENT_EXCEPTION(iR12), |
|
412 |
CONTEXT_ELEMENT_EXCEPTION(iR13usr), |
|
413 |
CONTEXT_ELEMENT_EXCEPTION(iR14usr), |
|
414 |
CONTEXT_ELEMENT_EXCEPTION(iR15), |
|
415 |
CONTEXT_ELEMENT_UNDEFINED(EUserMode), // can't get flags so just use 'user mode' |
|
416 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
417 |
}; |
|
418 |
||
419 |
// Table used for non-dying threads blocked on their request semaphore. |
|
420 |
const TArmContextElement ContextTableWFAR[] = |
|
421 |
{
|
|
422 |
CONTEXT_ELEMENT_EXCEPTION(iR0), |
|
423 |
CONTEXT_ELEMENT_EXCEPTION(iR1), |
|
424 |
CONTEXT_ELEMENT_EXCEPTION(iR2), |
|
425 |
CONTEXT_ELEMENT_EXCEPTION(iR3), |
|
426 |
CONTEXT_ELEMENT_EXCEPTION(iR4), |
|
427 |
CONTEXT_ELEMENT_EXCEPTION(iR5), |
|
428 |
CONTEXT_ELEMENT_EXCEPTION(iR6), |
|
429 |
CONTEXT_ELEMENT_EXCEPTION(iR7), |
|
430 |
CONTEXT_ELEMENT_EXCEPTION(iR8), |
|
431 |
CONTEXT_ELEMENT_EXCEPTION(iR9), |
|
432 |
CONTEXT_ELEMENT_EXCEPTION(iR10), |
|
433 |
CONTEXT_ELEMENT_EXCEPTION(iR11), |
|
434 |
CONTEXT_ELEMENT_EXCEPTION(iR12), |
|
435 |
CONTEXT_ELEMENT_EXCEPTION(iR13usr), |
|
436 |
CONTEXT_ELEMENT_EXCEPTION(iR14usr), |
|
437 |
CONTEXT_ELEMENT_EXCEPTION(iR15), |
|
438 |
CONTEXT_ELEMENT_EXCEPTION(iCPSR), |
|
439 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
440 |
}; |
|
441 |
||
442 |
const TArmContextElement ContextTableExec[] = |
|
443 |
{
|
|
444 |
CONTEXT_ELEMENT_EXCEPTION(iR0), |
|
445 |
CONTEXT_ELEMENT_EXCEPTION(iR1), |
|
446 |
CONTEXT_ELEMENT_EXCEPTION(iR2), |
|
447 |
CONTEXT_ELEMENT_EXCEPTION(iR3), |
|
448 |
CONTEXT_ELEMENT_EXCEPTION(iR4), |
|
449 |
CONTEXT_ELEMENT_EXCEPTION(iR5), |
|
450 |
CONTEXT_ELEMENT_EXCEPTION(iR6), |
|
451 |
CONTEXT_ELEMENT_EXCEPTION(iR7), |
|
452 |
CONTEXT_ELEMENT_EXCEPTION(iR8), |
|
453 |
CONTEXT_ELEMENT_EXCEPTION(iR9), |
|
454 |
CONTEXT_ELEMENT_EXCEPTION(iR10), |
|
455 |
CONTEXT_ELEMENT_EXCEPTION(iR11), |
|
456 |
CONTEXT_ELEMENT_EXCEPTION(iR12), |
|
457 |
CONTEXT_ELEMENT_EXCEPTION(iR13usr), |
|
458 |
CONTEXT_ELEMENT_EXCEPTION(iR14usr), |
|
459 |
CONTEXT_ELEMENT_EXCEPTION(iR15), |
|
460 |
CONTEXT_ELEMENT_EXCEPTION(iCPSR), |
|
461 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
462 |
}; |
|
463 |
||
464 |
// Table used to retrieve a thread's kernel side context at the point where |
|
465 |
// Reschedule() returns. |
|
466 |
// Used for kernel threads. |
|
467 |
const TArmContextElement ContextTableKernel[] = |
|
468 |
{
|
|
469 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
470 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
471 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
472 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
473 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
474 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
475 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
476 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
477 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
478 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
479 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
480 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
481 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
482 |
CONTEXT_ELEMENT_RESCHED_SP(), // supervisor stack pointer before reschedule |
|
483 |
CONTEXT_ELEMENT_UNDEFINED(0), // supervisor lr is unknown |
|
484 |
CONTEXT_ELEMENT_RESCHED(iR15), // return address from reschedule |
|
485 |
CONTEXT_ELEMENT_UNDEFINED(ESvcMode), // can't get flags so just use 'user mode' |
|
486 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
487 |
}; |
|
488 |
||
489 |
// Table used to retrieve a thread's kernel side context at the point where |
|
490 |
// NKern::Unlock() or NKern::PreemptionPoint() returns. |
|
491 |
// Used for kernel threads. |
|
492 |
const TArmContextElement ContextTableKernel1[] = |
|
493 |
{
|
|
494 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
495 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
496 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
497 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
498 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(4), |
|
499 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(8), |
|
500 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(12), |
|
501 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(16), |
|
502 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(20), |
|
503 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(24), |
|
504 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(28), |
|
505 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(32), |
|
506 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
507 |
CONTEXT_ELEMENT_RESCHED_SP_PLUS(40), |
|
508 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(36), |
|
509 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(36), |
|
510 |
CONTEXT_ELEMENT_UNDEFINED(ESvcMode), |
|
511 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
512 |
}; |
|
513 |
||
514 |
// Table used to retrieve a thread's kernel side context at the point where |
|
515 |
// NKern::FSWait() or NKern::WaitForAnyRequest() returns. |
|
516 |
// Used for kernel threads. |
|
517 |
const TArmContextElement ContextTableKernel2[] = |
|
518 |
{
|
|
519 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
520 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
521 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
522 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
523 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(4), |
|
524 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(8), |
|
525 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(12), |
|
526 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(16), |
|
527 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(20), |
|
528 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(24), |
|
529 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(28), |
|
530 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(32), |
|
531 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
532 |
CONTEXT_ELEMENT_RESCHED_SP_PLUS(40), |
|
533 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(36), |
|
534 |
CONTEXT_ELEMENT_RESCHED_SP_OFFSET(36), |
|
535 |
CONTEXT_ELEMENT_UNDEFINED(ESvcMode), |
|
536 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
537 |
}; |
|
538 |
||
539 |
// Table used to retrieve a thread's kernel side context at the point where |
|
540 |
// an interrupt taken in supervisor mode returns. |
|
541 |
// Used for kernel threads. |
|
542 |
const TArmContextElement ContextTableKernel3[] = |
|
543 |
{
|
|
544 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR0), |
|
545 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR1), |
|
546 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR2), |
|
547 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR3), |
|
548 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR4), |
|
549 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR5), |
|
550 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR6), |
|
551 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR7), |
|
552 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR8), |
|
553 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR9), |
|
554 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR10), |
|
555 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR11), |
|
556 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR12), |
|
557 |
CONTEXT_ELEMENT_RESCHED_SP_PLUS((sizeof(SThreadExcStack)+8)), |
|
558 |
CONTEXT_ELEMENT_RESCHED_IRQ(iR14svc), |
|
559 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iR15), |
|
560 |
CONTEXT_ELEMENT_RESCHED_IRQ(iX.iCPSR), |
|
561 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
562 |
}; |
|
563 |
||
564 |
// Table used to retrieve a thread's kernel side context at the point where |
|
565 |
// Exec::WaitForAnyRequest() returns. |
|
566 |
// Used for kernel threads. |
|
567 |
const TArmContextElement ContextTableKernel4[] = |
|
568 |
{
|
|
569 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR0), |
|
570 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR1), |
|
571 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR2), |
|
572 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR3), |
|
573 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR4), |
|
574 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR5), |
|
575 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR6), |
|
576 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR7), |
|
577 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR8), |
|
578 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR9), |
|
579 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR10), |
|
580 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR11), |
|
581 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR12), |
|
582 |
CONTEXT_ELEMENT_RESCHED_SP_PLUS(sizeof(SThreadExcStack)), |
|
583 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR15), |
|
584 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iR15), |
|
585 |
CONTEXT_ELEMENT_RESCHED_INIT(iX.iCPSR), |
|
586 |
CONTEXT_ELEMENT_UNDEFINED(0), |
|
587 |
}; |
|
588 |
||
589 |
const TArmContextElement* const ThreadUserContextTables[] = |
|
590 |
{
|
|
591 |
ContextTableUndefined, // EContextNone |
|
592 |
ContextTableException, // EContextException |
|
593 |
ContextTableUndefined, // EContextUndefined |
|
594 |
ContextTableUserInterrupt, // EContextUserInterrupt |
|
595 |
ContextTableUndefined, // EContextUserInterruptDied (not used) |
|
596 |
ContextTableSvsrInterrupt1, // EContextSvsrInterrupt1 |
|
597 |
ContextTableUndefined, // EContextSvsrInterrupt1Died (not used) |
|
598 |
ContextTableUndefined, // EContextSvsrInterrupt2 (not used) |
|
599 |
ContextTableUndefined, // EContextSvsrInterrupt2Died (not used) |
|
600 |
ContextTableWFAR, // EContextWFAR |
|
601 |
ContextTableUndefined, // EContextWFARDied (not used) |
|
602 |
ContextTableExec, // EContextExec |
|
603 |
ContextTableKernel, // EContextKernel |
|
604 |
ContextTableKernel1, // EContextKernel1 |
|
605 |
ContextTableKernel2, // EContextKernel2 |
|
606 |
ContextTableKernel3, // EContextKernel3 |
|
607 |
ContextTableKernel4, // EContextKernel4 |
|
608 |
0 // Null terminated |
|
609 |
}; |
|
610 |
||
611 |
/** Return table of pointers to user context tables. |
|
612 |
||
613 |
Each user context table is an array of TArmContextElement objects, one per |
|
614 |
ARM CPU register, in the order defined in TArmRegisters. |
|
615 |
||
616 |
The master table contains pointers to the user context tables in the order |
|
617 |
defined in TUserContextType. There are as many user context tables as |
|
618 |
scenarii leading a user thread to switch to privileged mode. |
|
619 |
||
620 |
Stop-mode debug agents should use this function to store the address of the |
|
621 |
master table at a location known to the host debugger. Run-mode debug |
|
622 |
agents are advised to use NKern::GetUserContext() and |
|
623 |
NKern::SetUserContext() instead. |
|
624 |
||
625 |
@return A pointer to the master table. The master table is NULL |
|
626 |
terminated. The master and user context tables are guaranteed to remain at |
|
627 |
the same location for the lifetime of the OS execution so it is safe the |
|
628 |
cache the returned address. |
|
629 |
||
630 |
@see UserContextType |
|
631 |
@see TArmContextElement |
|
632 |
@see TArmRegisters |
|
633 |
@see TUserContextType |
|
634 |
@see NKern::SetUserContext |
|
635 |
@see NKern::GetUserContext |
|
636 |
||
637 |
@publishedPartner |
|
638 |
*/ |
|
639 |
EXPORT_C const TArmContextElement* const* NThread::UserContextTables() |
|
640 |
{
|
|
641 |
return &ThreadUserContextTables[0]; |
|
642 |
} |
|
643 |
||
644 |
||
645 |
/** Get a value which indicates where a thread's user mode context is stored. |
|
646 |
||
647 |
@return A value that can be used as an index into the tables returned by |
|
648 |
NThread::UserContextTables(). |
|
649 |
||
650 |
@pre any context |
|
651 |
@pre kernel locked |
|
652 |
@post kernel locked |
|
653 |
||
654 |
@see UserContextTables |
|
655 |
@publishedPartner |
|
656 |
*/ |
|
657 |
EXPORT_C NThread::TUserContextType NThread::UserContextType() |
|
658 |
{
|
|
659 |
CHECK_PRECONDITIONS(MASK_KERNEL_LOCKED,"NThread::UserContextType"); |
|
660 |
||
661 |
/* |
|
662 |
The SMP nanokernel always saves R0-R12,R13usr,R14usr,ExcCode,PC,CPSR on any |
|
663 |
entry to the kernel, so getting the user context is always the same. |
|
664 |
The only possible problem is an FIQ occurring immediately after any other |
|
665 |
exception, before the registers have been saved. In this case the registers |
|
666 |
saved by the FIQ will be the ones observed and they will be correct except |
|
667 |
that the CPSR value will indicate a mode other than USR, which can be used |
|
668 |
to detect the condition. |
|
669 |
*/ |
|
670 |
return EContextException; |
|
671 |
} |
|
672 |
||
673 |
||
674 |
// Enter and return with kernel locked |
|
675 |
void NThread::GetUserContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask) |
|
676 |
{
|
|
677 |
NThread* pC = NCurrentThreadL(); |
|
678 |
TSubScheduler* ss = 0; |
|
679 |
if (pC != this) |
|
680 |
{
|
|
681 |
AcqSLock(); |
|
|
90
947f0dc9f7a8
Revision: 201015
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
682 |
if (iWaitState.ThreadIsDead() || i_NThread_Initial) |
| 0 | 683 |
{
|
684 |
RelSLock(); |
|
685 |
aAvailRegistersMask = 0; |
|
686 |
return; |
|
687 |
} |
|
688 |
if (iReady && iParent->iReady) |
|
689 |
{
|
|
690 |
ss = TheSubSchedulers + (iParent->iReady & EReadyCpuMask); |
|
691 |
ss->iReadyListLock.LockOnly(); |
|
692 |
} |
|
693 |
if (iCurrent) |
|
694 |
{
|
|
695 |
// thread is actually running on another CPU |
|
696 |
// interrupt that CPU and wait for it to enter interrupt mode |
|
697 |
// this allows a snapshot of the thread user state to be observed |
|
698 |
// and ensures the thread cannot return to user mode |
|
699 |
send_resched_ipi_and_wait(iLastCpu); |
|
700 |
} |
|
701 |
} |
|
702 |
SThreadExcStack* txs = (SThreadExcStack*)(TLinAddr(iStackBase) + TLinAddr(iStackSize)); |
|
703 |
--txs; |
|
704 |
if (txs->iExcCode <= SThreadExcStack::EInit) // if not, thread never entered user mode |
|
705 |
{
|
|
706 |
aContext.iR0 = txs->iR0; |
|
707 |
aContext.iR1 = txs->iR1; |
|
708 |
aContext.iR2 = txs->iR2; |
|
709 |
aContext.iR3 = txs->iR3; |
|
710 |
aContext.iR4 = txs->iR4; |
|
711 |
aContext.iR5 = txs->iR5; |
|
712 |
aContext.iR6 = txs->iR6; |
|
713 |
aContext.iR7 = txs->iR7; |
|
714 |
aContext.iR8 = txs->iR8; |
|
715 |
aContext.iR9 = txs->iR9; |
|
716 |
aContext.iR10 = txs->iR10; |
|
717 |
aContext.iR11 = txs->iR11; |
|
718 |
aContext.iR12 = txs->iR12; |
|
719 |
aContext.iR13 = txs->iR13usr; |
|
720 |
aContext.iR14 = txs->iR14usr; |
|
721 |
aContext.iR15 = txs->iR15; |
|
722 |
aContext.iFlags = txs->iCPSR; |
|
723 |
if ((aContext.iFlags & 0x1f) == 0x10) |
|
724 |
aAvailRegistersMask = 0x1ffffu; // R0-R15,CPSR all valid |
|
725 |
else |
|
726 |
{
|
|
727 |
aContext.iFlags = 0x10; // account for FIQ in SVC case |
|
728 |
aAvailRegistersMask = 0x0ffffu; // CPSR not valid |
|
729 |
} |
|
730 |
} |
|
731 |
if (pC != this) |
|
732 |
{
|
|
733 |
if (ss) |
|
734 |
ss->iReadyListLock.UnlockOnly(); |
|
735 |
RelSLock(); |
|
736 |
} |
|
737 |
} |
|
738 |
||
739 |
class TGetContextIPI : public TGenericIPI |
|
740 |
{
|
|
741 |
public: |
|
742 |
void Get(TInt aCpu, TArmRegSet& aContext, TUint32& aAvailRegistersMask); |
|
743 |
static void Isr(TGenericIPI*); |
|
744 |
public: |
|
745 |
TArmRegSet* iContext; |
|
746 |
TUint32* iAvailRegsMask; |
|
747 |
}; |
|
748 |
||
749 |
extern "C" TLinAddr get_sp_svc(); |
|
750 |
extern "C" TLinAddr get_lr_svc(); |
|
751 |
extern "C" TInt get_kernel_context_type(TLinAddr /*aReschedReturn*/); |
|
752 |
||
753 |
void TGetContextIPI::Isr(TGenericIPI* aPtr) |
|
754 |
{
|
|
755 |
TGetContextIPI& ipi = *(TGetContextIPI*)aPtr; |
|
756 |
TArmRegSet& a = *ipi.iContext; |
|
757 |
SThreadExcStack* txs = (SThreadExcStack*)get_sp_svc(); |
|
758 |
a.iR0 = txs->iR0; |
|
759 |
a.iR1 = txs->iR1; |
|
760 |
a.iR2 = txs->iR2; |
|
761 |
a.iR3 = txs->iR3; |
|
762 |
a.iR4 = txs->iR4; |
|
763 |
a.iR5 = txs->iR5; |
|
764 |
a.iR6 = txs->iR6; |
|
765 |
a.iR7 = txs->iR7; |
|
766 |
a.iR8 = txs->iR8; |
|
767 |
a.iR9 = txs->iR9; |
|
768 |
a.iR10 = txs->iR10; |
|
769 |
a.iR11 = txs->iR11; |
|
770 |
a.iR12 = txs->iR12; |
|
771 |
a.iR13 = TUint32(txs) + sizeof(SThreadExcStack); |
|
772 |
a.iR14 = get_lr_svc(); |
|
773 |
a.iR15 = txs->iR15; |
|
774 |
a.iFlags = txs->iCPSR; |
|
775 |
*ipi.iAvailRegsMask = 0x1ffffu; |
|
776 |
} |
|
777 |
||
778 |
void TGetContextIPI::Get(TInt aCpu, TArmRegSet& aContext, TUint32& aAvailRegsMask) |
|
779 |
{
|
|
780 |
iContext = &aContext; |
|
781 |
iAvailRegsMask = &aAvailRegsMask; |
|
782 |
Queue(&Isr, 1u<<aCpu); |
|
783 |
WaitCompletion(); |
|
784 |
} |
|
785 |
||
786 |
void GetRegs(TArmRegSet& aContext, TLinAddr aStart, TUint32 aMask) |
|
787 |
{
|
|
788 |
TUint32* d = (TUint32*)&aContext; |
|
789 |
const TUint32* s = (const TUint32*)aStart; |
|
790 |
for (; aMask; aMask>>=1, ++d) |
|
791 |
{
|
|
792 |
if (aMask & 1) |
|
793 |
*d = *s++; |
|
794 |
} |
|
795 |
} |
|
796 |
||
797 |
// Enter and return with kernel locked |
|
798 |
void NThread::GetSystemContext(TArmRegSet& aContext, TUint32& aAvailRegsMask) |
|
799 |
{
|
|
800 |
aAvailRegsMask = 0; |
|
801 |
NThread* pC = NCurrentThreadL(); |
|
802 |
__NK_ASSERT_ALWAYS(pC!=this); |
|
803 |
TSubScheduler* ss = 0; |
|
804 |
AcqSLock(); |
|
805 |
if (iWaitState.ThreadIsDead()) |
|
806 |
{
|
|
807 |
RelSLock(); |
|
808 |
return; |
|
809 |
} |
|
810 |
if (iReady && iParent->iReady) |
|
811 |
{
|
|
812 |
ss = TheSubSchedulers + (iParent->iReady & EReadyCpuMask); |
|
813 |
ss->iReadyListLock.LockOnly(); |
|
814 |
} |
|
815 |
if (iCurrent) |
|
816 |
{
|
|
817 |
// thread is actually running on another CPU |
|
818 |
// use an interprocessor interrupt to get a snapshot of the state |
|
819 |
TGetContextIPI ipi; |
|
820 |
ipi.Get(iLastCpu, aContext, aAvailRegsMask); |
|
821 |
} |
|
822 |
else |
|
823 |
{
|
|
824 |
// thread is not running and can't start |
|
825 |
SThreadReschedStack* trs = (SThreadReschedStack*)iSavedSP; |
|
826 |
TInt kct = get_kernel_context_type(trs->iR15); |
|
827 |
__NK_ASSERT_ALWAYS(kct>=0); // couldn't match return address from reschedule |
|
828 |
TLinAddr sp = trs->iSPRschdFlg &~ 3; |
|
829 |
switch (kct) |
|
830 |
{
|
|
831 |
case 0: // thread not yet started |
|
832 |
case 5: // Exec::WaitForAnyRequest() |
|
833 |
GetRegs(aContext, sp, 0x01fffu); |
|
834 |
aContext.iR13 = sp + sizeof(SThreadExcStack); |
|
835 |
GetRegs(aContext, sp+64, 0x18000u); |
|
836 |
aAvailRegsMask =0x1bfffu; |
|
837 |
break; |
|
838 |
case 1: // unlock |
|
839 |
case 2: // preemption point |
|
840 |
case 3: // NKern::WaitForAnyRequest() or NKern::FSWait() |
|
841 |
GetRegs(aContext, sp+4, 0x08ff0u); |
|
842 |
aContext.iR14 = aContext.iR15; |
|
843 |
aContext.iR13 = sp+40; |
|
844 |
aAvailRegsMask =0x0eff0u; |
|
845 |
break; |
|
846 |
case 4: // IRQ/FIQ |
|
847 |
GetRegs(aContext, sp+4, 0x04000u); |
|
848 |
GetRegs(aContext, sp+8, 0x01fffu); |
|
849 |
GetRegs(aContext, sp+64, 0x18000u); |
|
850 |
aContext.iR13 = sp + sizeof(SThreadExcStack) + 8; |
|
851 |
aAvailRegsMask =0x1ffffu; |
|
852 |
break; |
|
853 |
default: |
|
854 |
__NK_ASSERT_ALWAYS(0); |
|
855 |
} |
|
856 |
} |
|
857 |
if (ss) |
|
858 |
ss->iReadyListLock.UnlockOnly(); |
|
859 |
RelSLock(); |
|
860 |
} |
|
861 |
||
862 |
// Enter and return with kernel locked |
|
863 |
void NThread::SetUserContext(const TArmRegSet& aContext, TUint32& aRegMask) |
|
864 |
{
|
|
865 |
NThread* pC = NCurrentThreadL(); |
|
866 |
TSubScheduler* ss = 0; |
|
867 |
if (pC != this) |
|
868 |
{
|
|
869 |
AcqSLock(); |
|
|
90
947f0dc9f7a8
Revision: 201015
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
870 |
if (iWaitState.ThreadIsDead() || i_NThread_Initial) |
| 0 | 871 |
{
|
872 |
RelSLock(); |
|
873 |
aRegMask = 0; |
|
874 |
return; |
|
875 |
} |
|
876 |
if (iReady && iParent->iReady) |
|
877 |
{
|
|
878 |
ss = TheSubSchedulers + (iParent->iReady & EReadyCpuMask); |
|
879 |
ss->iReadyListLock.LockOnly(); |
|
880 |
} |
|
881 |
if (iCurrent) |
|
882 |
{
|
|
883 |
// thread is actually running on another CPU |
|
884 |
// interrupt that CPU and wait for it to enter interrupt mode |
|
885 |
// this allows a snapshot of the thread user state to be observed |
|
886 |
// and ensures the thread cannot return to user mode |
|
887 |
send_resched_ipi_and_wait(iLastCpu); |
|
888 |
} |
|
889 |
} |
|
890 |
SThreadExcStack* txs = (SThreadExcStack*)(TLinAddr(iStackBase) + TLinAddr(iStackSize)); |
|
891 |
--txs; |
|
892 |
aRegMask &= 0x1ffffu; |
|
893 |
if (txs->iExcCode <= SThreadExcStack::EInit) // if not, thread never entered user mode |
|
894 |
{
|
|
895 |
if (aRegMask & 0x0001u) |
|
896 |
txs->iR0 = aContext.iR0; |
|
897 |
if (aRegMask & 0x0002u) |
|
898 |
txs->iR1 = aContext.iR1; |
|
899 |
if (aRegMask & 0x0004u) |
|
900 |
txs->iR2 = aContext.iR2; |
|
901 |
if (aRegMask & 0x0008u) |
|
902 |
txs->iR3 = aContext.iR3; |
|
903 |
if (aRegMask & 0x0010u) |
|
904 |
txs->iR4 = aContext.iR4; |
|
905 |
if (aRegMask & 0x0020u) |
|
906 |
txs->iR5 = aContext.iR5; |
|
907 |
if (aRegMask & 0x0040u) |
|
908 |
txs->iR6 = aContext.iR6; |
|
909 |
if (aRegMask & 0x0080u) |
|
910 |
txs->iR7 = aContext.iR7; |
|
911 |
if (aRegMask & 0x0100u) |
|
912 |
txs->iR8 = aContext.iR8; |
|
913 |
if (aRegMask & 0x0200u) |
|
914 |
txs->iR9 = aContext.iR9; |
|
915 |
if (aRegMask & 0x0400u) |
|
916 |
txs->iR10 = aContext.iR10; |
|
917 |
if (aRegMask & 0x0800u) |
|
918 |
txs->iR11 = aContext.iR11; |
|
919 |
if (aRegMask & 0x1000u) |
|
920 |
txs->iR12 = aContext.iR12; |
|
921 |
if (aRegMask & 0x2000u) |
|
922 |
txs->iR13usr = aContext.iR13; |
|
923 |
if (aRegMask & 0x4000u) |
|
924 |
txs->iR14usr = aContext.iR14; |
|
925 |
if (aRegMask & 0x8000u) |
|
926 |
txs->iR15 = aContext.iR15; |
|
927 |
// Assert that target thread is in USR mode, and update only the flags part of the PSR |
|
928 |
__NK_ASSERT_ALWAYS((txs->iCPSR & 0x1f) == 0x10); |
|
929 |
if (aRegMask & 0x10000u) |
|
930 |
{
|
|
931 |
// NZCVQ.......GE3-0................ |
|
932 |
const TUint32 writableFlags = 0xF80F0000; |
|
933 |
txs->iCPSR &= ~writableFlags; |
|
934 |
txs->iCPSR |= aContext.iFlags & writableFlags; |
|
935 |
} |
|
936 |
} |
|
937 |
else |
|
938 |
aRegMask = 0; |
|
939 |
if (pC != this) |
|
940 |
{
|
|
941 |
if (ss) |
|
942 |
ss->iReadyListLock.UnlockOnly(); |
|
943 |
RelSLock(); |
|
944 |
} |
|
945 |
} |
|
946 |
||
947 |
/** Get (subset of) user context of specified thread. |
|
948 |
||
949 |
The nanokernel does not systematically save all registers in the supervisor |
|
950 |
stack on entry into privileged mode and the exact subset depends on why the |
|
951 |
switch to privileged mode occured. So in general only a subset of the |
|
952 |
register set is available. |
|
953 |
||
954 |
@param aThread Thread to inspect. It can be the current thread or a |
|
955 |
non-current one. |
|
956 |
||
957 |
@param aContext Pointer to TArmRegSet structure where the context is |
|
958 |
copied. |
|
959 |
||
960 |
@param aAvailRegistersMask Bit mask telling which subset of the context is |
|
961 |
available and has been copied to aContext (1: register available / 0: not |
|
962 |
available). Bit 0 stands for register R0. |
|
963 |
||
964 |
@see TArmRegSet |
|
965 |
@see ThreadSetUserContext |
|
966 |
||
967 |
@pre Call in a thread context. |
|
968 |
@pre Interrupts must be enabled. |
|
969 |
*/ |
|
970 |
EXPORT_C void NKern::ThreadGetUserContext(NThread* aThread, TAny* aContext, TUint32& aAvailRegistersMask) |
|
971 |
{
|
|
972 |
CHECK_PRECONDITIONS(MASK_INTERRUPTS_ENABLED|MASK_NOT_ISR|MASK_NOT_IDFC,"NKern::ThreadGetUserContext"); |
|
973 |
TArmRegSet& a = *(TArmRegSet*)aContext; |
|
974 |
memclr(aContext, sizeof(TArmRegSet)); |
|
975 |
NKern::Lock(); |
|
976 |
aThread->GetUserContext(a, aAvailRegistersMask); |
|
977 |
NKern::Unlock(); |
|
978 |
} |
|
979 |
||
980 |
/** Get (subset of) system context of specified thread. |
|
981 |
||
982 |
@param aThread Thread to inspect. It can be the current thread or a |
|
983 |
non-current one. |
|
984 |
||
985 |
@param aContext Pointer to TArmRegSet structure where the context is |
|
986 |
copied. |
|
987 |
||
988 |
@param aAvailRegistersMask Bit mask telling which subset of the context is |
|
989 |
available and has been copied to aContext (1: register available / 0: not |
|
990 |
available). Bit 0 stands for register R0. |
|
991 |
||
992 |
@see TArmRegSet |
|
993 |
@see ThreadSetUserContext |
|
994 |
||
995 |
@pre Call in a thread context. |
|
996 |
@pre Interrupts must be enabled. |
|
997 |
*/ |
|
998 |
EXPORT_C void NKern::ThreadGetSystemContext(NThread* aThread, TAny* aContext, TUint32& aAvailRegistersMask) |
|
999 |
{
|
|
1000 |
CHECK_PRECONDITIONS(MASK_INTERRUPTS_ENABLED|MASK_NOT_ISR|MASK_NOT_IDFC,"NKern::ThreadGetSystemContext"); |
|
1001 |
TArmRegSet& a = *(TArmRegSet*)aContext; |
|
1002 |
memclr(aContext, sizeof(TArmRegSet)); |
|
1003 |
NKern::Lock(); |
|
1004 |
aThread->GetSystemContext(a, aAvailRegistersMask); |
|
1005 |
NKern::Unlock(); |
|
1006 |
} |
|
1007 |
||
1008 |
/** Set (subset of) user context of specified thread. |
|
1009 |
||
1010 |
@param aThread Thread to modify. It can be the current thread or a |
|
1011 |
non-current one. |
|
1012 |
||
1013 |
@param aContext Pointer to TArmRegSet structure containing the context |
|
1014 |
to set. The values of registers which aren't part of the context saved |
|
1015 |
on the supervisor stack are ignored. |
|
1016 |
||
1017 |
@see TArmRegSet |
|
1018 |
@see ThreadGetUserContext |
|
1019 |
||
1020 |
@pre Call in a thread context. |
|
1021 |
@pre Interrupts must be enabled. |
|
1022 |
*/ |
|
1023 |
EXPORT_C void NKern::ThreadSetUserContext(NThread* aThread, TAny* aContext) |
|
1024 |
{
|
|
1025 |
CHECK_PRECONDITIONS(MASK_INTERRUPTS_ENABLED|MASK_NOT_ISR|MASK_NOT_IDFC,"NKern::ThreadSetUserContext"); |
|
1026 |
TArmRegSet& a = *(TArmRegSet*)aContext; |
|
1027 |
TUint32 mask = 0x1ffffu; |
|
1028 |
NKern::Lock(); |
|
1029 |
aThread->SetUserContext(a, mask); |
|
1030 |
NKern::Unlock(); |
|
1031 |
} |
|
1032 |
||
1033 |
||
1034 |
#ifdef __CPU_HAS_VFP |
|
1035 |
extern void VfpContextSave(void*); |
|
1036 |
#endif |
|
1037 |
/** Complete the saving of a thread's context |
|
1038 |
||
1039 |
This saves the VFP/NEON registers if necessary once we know that we are definitely |
|
1040 |
switching threads. |
|
1041 |
||
1042 |
@internalComponent |
|
1043 |
*/ |
|
1044 |
void NThread::CompleteContextSave() |
|
1045 |
{
|
|
1046 |
#ifdef __CPU_HAS_VFP |
|
1047 |
if (Arm::VfpThread[NKern::CurrentCpu()] == this) |
|
1048 |
{
|
|
1049 |
VfpContextSave(iExtraContext); // Disables VFP |
|
1050 |
} |
|
1051 |
#endif |
|
1052 |
} |
|
1053 |
||
1054 |
||
1055 |
extern "C" TInt HandleSpecialOpcode(TArmExcInfo* aContext, TInt aType) |
|
1056 |
{
|
|
1057 |
TUint32 cpsr = aContext->iCpsr; |
|
1058 |
TUint32 mode = cpsr & 0x1f; |
|
1059 |
TUint32 opcode = aContext->iFaultStatus; |
|
1060 |
||
1061 |
// Coprocessor abort from CP15 or E7FFDEFF -> crash immediately |
|
1062 |
if ( (aType==15 && opcode!=0xee000f20) |
|
1063 |
|| (aType==32 && opcode==0xe7ffdeff) |
|
1064 |
|| (aType==33 && opcode==0xdeff) |
|
1065 |
) |
|
1066 |
{
|
|
1067 |
if (mode != 0x10) |
|
1068 |
ExcFault(aContext); // crash instruction in privileged mode |
|
1069 |
return 0; // crash instruction in user mode - handle normally |
|
1070 |
} |
|
1071 |
if ( (aType==15 && opcode==0xee000f20) |
|
1072 |
|| (aType==32 && opcode==0xe7ffdefc) |
|
1073 |
|| (aType==33 && opcode==0xdefc) |
|
1074 |
) |
|
1075 |
{
|
|
1076 |
// checkpoint |
|
1077 |
__KTRACE_OPT(KPANIC,DumpExcInfo(*aContext)); |
|
1078 |
if (aType==32) |
|
1079 |
aContext->iR15 += 4; |
|
1080 |
else |
|
1081 |
aContext->iR15 += 2; |
|
1082 |
return 1; |
|
1083 |
} |
|
1084 |
return 0; |
|
1085 |
} |
|
1086 |
||
1087 |
||
1088 |
TInt NKern::QueueUserModeCallback(NThreadBase* aThread, TUserModeCallback* aCallback) |
|
1089 |
{
|
|
1090 |
__e32_memory_barrier(); |
|
1091 |
if (aCallback->iNext != KUserModeCallbackUnqueued) |
|
1092 |
return KErrInUse; |
|
|
90
947f0dc9f7a8
Revision: 201015
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
1093 |
if (aThread->i_NThread_Initial) |
|
947f0dc9f7a8
Revision: 201015
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
1094 |
return KErrArgument; |
| 0 | 1095 |
TInt result = KErrDied; |
1096 |
NKern::Lock(); |
|
1097 |
TUserModeCallback* listHead = aThread->iUserModeCallbacks; |
|
1098 |
do {
|
|
1099 |
if (TLinAddr(listHead) & 3) |
|
1100 |
goto done; // thread exiting |
|
1101 |
aCallback->iNext = listHead; |
|
1102 |
} while (!__e32_atomic_cas_ord_ptr(&aThread->iUserModeCallbacks, &listHead, aCallback)); |
|
1103 |
result = KErrNone; |
|
1104 |
||
1105 |
if (!listHead) // if this isn't first callback someone else will have done this bit |
|
1106 |
{
|
|
1107 |
/* |
|
1108 |
* If aThread is currently running on another CPU we need to send an IPI so |
|
1109 |
* that it will enter kernel mode and run the callback. |
|
1110 |
* The synchronization is tricky here. We want to check if the thread is |
|
1111 |
* running and if so on which core. We need to avoid any possibility of |
|
1112 |
* the thread entering user mode without having seen the callback, |
|
1113 |
* either because we thought it wasn't running so didn't send an IPI or |
|
1114 |
* because the thread migrated after we looked and we sent the IPI to |
|
1115 |
* the wrong processor. Sending a redundant IPI is not a problem (e.g. |
|
1116 |
* because the thread is running in kernel mode - which we can't tell - |
|
1117 |
* or because the thread stopped running after we looked) |
|
1118 |
* The following events are significant: |
|
1119 |
* Event A: Target thread writes to iCurrent when it starts running |
|
1120 |
* Event B: Target thread reads iUserModeCallbacks before entering user |
|
1121 |
* mode |
|
1122 |
* Event C: This thread writes to iUserModeCallbacks |
|
1123 |
* Event D: This thread reads iCurrent to check if aThread is running |
|
1124 |
* There is a DMB and DSB between A and B since A occurs with the ready |
|
1125 |
* list lock for the CPU involved or the thread lock for aThread held |
|
1126 |
* and this lock is released before B occurs. |
|
1127 |
* There is a DMB between C and D (part of __e32_atomic_cas_ord_ptr). |
|
1128 |
* Any observer which observes B must also have observed A. |
|
1129 |
* Any observer which observes D must also have observed C. |
|
1130 |
* If aThread observes B before C (i.e. enters user mode without running |
|
1131 |
* the callback) it must observe A before C and so it must also observe |
|
1132 |
* A before D (i.e. D reads the correct value for iCurrent). |
|
1133 |
*/ |
|
1134 |
TInt current = aThread->iCurrent; |
|
1135 |
if (current) |
|
1136 |
{
|
|
1137 |
TInt cpu = current & NSchedulable::EReadyCpuMask; |
|
1138 |
if (cpu != NKern::CurrentCpu()) |
|
1139 |
send_resched_ipi(cpu); |
|
1140 |
} |
|
1141 |
} |
|
1142 |
done: |
|
1143 |
NKern::Unlock(); |
|
1144 |
return result; |
|
1145 |
} |
|
1146 |