; Copyright (c) 2003-2008 Nokia Corporation and/or its subsidiary(-ies).

; All rights reserved.

; This component and the accompanying materials are made available

; under the terms of the License "Eclipse Public License v1.0"

; which accompanies this distribution, and is available

; at the URL "http://www.eclipse.org/legal/epl-v10.html".

;

; Initial Contributors:

; Nokia Corporation - initial contribution.

;

; Contributors:

;

; Description:

; e32\include\kernel\arm\bootcpu.inc

;

;

;*******************************************************************************

;

; CPU/MMU definitions for bootstrap

;

	IF	:LNOT: :DEF: __BOOTCPU_INC__

	GBLL	__BOOTCPU_INC__

	MACRO

	INIT_LOGICAL_SYMBOL	$sym, $count

	IF :LNOT: :DEF: $sym

		GBLL	$sym

$sym	SETL	{FALSE}

	ELSE

$sym	SETL	{TRUE}

		IF :LEN: "$count" > 0

$count		SETA	$count + 1

		ENDIF

	ENDIF

	MEND

	MACRO

	INIT_NUMERIC_SYMBOL	$sym, $default

	IF :LNOT: :DEF: $sym

		GBLA	$sym

$sym	SETA	$default

	ENDIF

	MEND

	MACRO

	INIT_NUMERIC_CONSTANT	$sym, $default

	IF :LNOT: :DEF: $sym

$sym	EQU		$default

	ENDIF

	MEND

; CP15 control register bits

; Define these here so they can be used in config.inc to override MMU settings

MMUCR_M		EQU		0x00000001			; MMU enable

MMUCR_A		EQU		0x00000002			; Alignment check

MMUCR_C		EQU		0x00000004			; DCache enable

MMUCR_W		EQU		0x00000008			; Write buffer enable

MMUCR_SBO	EQU		0x00000070			; Always 1

MMUCR_B		EQU		0x00000080			; Big endian

MMUCR_S		EQU		0x00000100			; System permission modifier

MMUCR_R		EQU		0x00000200			; ROM permission modifier

MMUCR_F		EQU		0x00000400			;

MMUCR_Z		EQU		0x00000800			; Flow prediction enable

MMUCR_I		EQU		0x00001000			; ICache enable

MMUCR_V		EQU		0x00002000			; High vectors

MMUCR_RR	EQU		0x00004000			; Round Robin cache replacement

MMUCR_L4	EQU		0x00008000			; LDR PC v4 behaviour (don't set T bit)

MMUCR_DT	EQU		0x00010000			; DTCM enable

MMUCR_IT	EQU		0x00040000			; ITCM enable

MMUCR_FI	EQU		0x00200000			; Fast Interrupt configuration (low latency)

MMUCR_U		EQU		0x00400000			; Unaligned data access enable (mixed endian)

MMUCR_XP	EQU		0x00800000			; ARMv6 extended page table format

MMUCR_VE	EQU		0x01000000			; Vectored interrupt enable

MMUCR_EE	EQU		0x02000000			; CPSR E bit following exception (mixed endian)

MMUCR_L2XSCALE	EQU	0x04000000			; L2 Cache enable on XScale platform

MMUCR_TRE	EQU		0x10000000			; TEX remapping

MMUCR_FA	EQU		0x20000000			; AP[0] is used as Access Bit. Four (instead of eight) access permissions are available.

	INCLUDE	config.inc

	INIT_LOGICAL_SYMBOL	CFG_DebugBootRom

	INIT_LOGICAL_SYMBOL	CFG_CustomVectors

	INIT_LOGICAL_SYMBOL	CFG_UseBootstrapVectors

	INIT_LOGICAL_SYMBOL	CFG_AutoDetectROM

	INIT_LOGICAL_SYMBOL	CFG_IncludeRAMAllocator

	INIT_LOGICAL_SYMBOL	CFG_BootLoader

	INIT_LOGICAL_SYMBOL	SMP

	IF	SMP

	GBLL	CFG_USE_SHARED_MEMORY

CFG_USE_SHARED_MEMORY		SETL	{TRUE}

	ENDIF

	INCLUDE	bootmacro.inc

	INCLUDE	bootdefs.inc

	INCLUDE kernboot.inc

	INCLUDE e32rom.inc

; Check memory model definition

	GBLA	NMM

NMM	SETA	0

	INIT_LOGICAL_SYMBOL	CFG_MMDirect, NMM

	INIT_LOGICAL_SYMBOL	CFG_MMMoving, NMM

	INIT_LOGICAL_SYMBOL	CFG_MMMultiple, NMM

	INIT_LOGICAL_SYMBOL	CFG_MMFlexible, NMM

	IF	NMM=0

		! 1, "No memory model specified"

	ENDIF

	IF	NMM>1

		! 2, "More than one memory model specified"

	ENDIF

	IF :LNOT: CFG_MMDirect

		INCLUDE	mmboot.inc

	ENDIF

	INIT_NUMERIC_CONSTANT	CFG_RomSizeAlign, 16	; 64K by default

; First declare variables

	GBLA	NCPU

NCPU	SETA	0

	IF	:DEF: CPUOK

NCPU	SETA	1

	ENDIF

	GBLL	CFG_ARMV7

CFG_ARMV7					SETL	{FALSE}

	GBLL	CFG_ARMV6

CFG_ARMV6					SETL	{FALSE}

	GBLL	CFG_MMUPresent

CFG_MMUPresent				SETL	{FALSE}

	GBLL	CFG_CachePresent

CFG_CachePresent			SETL	{FALSE}

	GBLL	CFG_WriteBufferPresent

CFG_WriteBufferPresent		SETL	{FALSE}

	GBLL	CFG_SplitCache

CFG_SplitCache				SETL	{FALSE}

	GBLL	CFG_SplitTLB

CFG_SplitTLB				SETL	{FALSE}

	GBLL	CFG_AltDCachePresent

CFG_AltDCachePresent		SETL	{FALSE}

	GBLL	CFG_WriteBackCache

CFG_WriteBackCache			SETL	{FALSE}

	GBLL	CFG_CacheWriteAllocate

CFG_CacheWriteAllocate		SETL	{FALSE}

	GBLL	CFG_CachePhysicalTag

CFG_CachePhysicalTag		SETL	{FALSE}

	GBLL	CFG_CacheFlushByDataRead

CFG_CacheFlushByDataRead	SETL	{FALSE}

	GBLL	CFG_CacheFlushByWaySetIndex

CFG_CacheFlushByWaySetIndex	SETL	{FALSE}

	GBLL	CFG_CacheFlushByLineAlloc

CFG_CacheFlushByLineAlloc	SETL	{FALSE}

	GBLL	CFG_CachePolicyInPTE

CFG_CachePolicyInPTE		SETL	{FALSE}

	GBLL	CFG_TEX

CFG_TEX						SETL	{FALSE}

	GBLL	CFG_SingleEntryDCacheFlush

CFG_SingleEntryDCacheFlush	SETL	{FALSE}

	GBLL	CFG_SingleEntryICacheFlush

CFG_SingleEntryICacheFlush	SETL	{FALSE}

	GBLL	CFG_SingleEntryITLBFlush

CFG_SingleEntryITLBFlush	SETL	{FALSE}

	GBLL	CFG_SingleEntryTLBFlush

CFG_SingleEntryTLBFlush		SETL	{FALSE}

	GBLL	CFG_CacheTypeReg

CFG_CacheTypeReg			SETL	{FALSE}

	GBLL	CFG_BTBPresent

CFG_BTBPresent				SETL	{FALSE}

	GBLL	CFG_AuxCRPresent

CFG_AuxCRPresent			SETL	{FALSE}

	GBLL	CFG_CARPresent

CFG_CARPresent				SETL	{FALSE}

	GBLL	CFG_PrefetchBuffer

CFG_PrefetchBuffer			SETL	{FALSE}

	GBLL	CFG_FCSE_Present

CFG_FCSE_Present			SETL	{FALSE}

	GBLL	CFG_ASID_Present

CFG_ASID_Present			SETL	{FALSE}

	GBLL	CFG_Cpu_Has_CLZ

CFG_Cpu_Has_CLZ				SETL	{FALSE}

	GBLL	CFG_Cpu_Has_TrustZone

CFG_Cpu_Has_TrustZone		SETL	{FALSE}

;TrustZone platforms with Symbian OS Kernel running in Non-Secure Mode

	GBLL	CFG_TrustZone_NonSecure

CFG_TrustZone_NonSecure		SETL	{FALSE}

; Cache attributes are re-mapped into TEX[0]:C:B only. TEX[2:1] are freed up for S/W purpose.

; Also, access permissions are mapped to APX:AP[1] only. AP[0] is freed up for S/W purpose.

	GBLL	CFG_MemoryTypeRemapping

CFG_MemoryTypeRemapping		SETL	{FALSE}

; Page tables are Write-Back cached. Mandatory if CFG_MemoryTypeRemapping is TRUE 

	GBLL	CFG_WriteThroughDisabled

CFG_WriteThroughDisabled	SETL	{FALSE}

	GBLL	CFG_Cpu_Has_WFE_SEV

CFG_Cpu_Has_WFE_SEV			SETL	{FALSE}

	GBLL	CFG_Cpu_Has_WFI

CFG_Cpu_Has_WFI				SETL	{FALSE}

;*******************************************************************************

	IF	:DEF: CFG_CPU_GENERIC_ARM4

NCPU	SETA	NCPU+1

	ENDIF

;*******************************************************************************

	IF	:DEF: CFG_CPU_ARM710T :LOR: :DEF: CFG_CPU_ARM720T

NCPU	SETA	NCPU+1

CFG_MMUPresent				SETL	{TRUE}

CFG_CachePresent			SETL	{TRUE}

CFG_WriteBufferPresent		SETL	{TRUE}

CFG_SingleEntryTLBFlush		SETL	{TRUE}

	IF	:DEF: CFG_CPU_ARM720T

CFG_FCSE_Present			SETL	{TRUE}

	ENDIF

	INIT_NUMERIC_CONSTANT	InitialMMUCR,	MMUCR_A+MMUCR_SBO+MMUCR_R

	INIT_NUMERIC_CONSTANT	ExtraMMUCR,		MMUCR_M+MMUCR_C+MMUCR_W

PDE_EXTRA					EQU		0x00000010

	ENDIF

;*******************************************************************************

	IF	:DEF: CFG_CPU_SA1

NCPU	SETA	NCPU+1

CFG_MMUPresent				SETL	{TRUE}

CFG_CachePresent			SETL	{TRUE}

CFG_WriteBufferPresent		SETL	{TRUE}

CFG_SplitCache				SETL	{TRUE}

CFG_SplitTLB				SETL	{TRUE}

CFG_AltDCachePresent		SETL	{TRUE}

CFG_WriteBackCache			SETL	{TRUE}

CFG_CacheFlushByDataRead	SETL	{TRUE}

CFG_SingleEntryDCacheFlush	SETL	{TRUE}

CFG_FCSE_Present			SETL	{TRUE}

	INIT_NUMERIC_CONSTANT	InitialMMUCR,	MMUCR_A+MMUCR_SBO+MMUCR_R+MMUCR_I

	INIT_NUMERIC_CONSTANT	ExtraMMUCR,		MMUCR_M+MMUCR_C+MMUCR_W+MMUCR_V

PDE_EXTRA					EQU		0x00000000

	ENDIF

;*******************************************************************************

	IF	:DEF: CFG_CPU_ARM920T	:LOR:	:DEF: CFG_CPU_ARM925T	:LOR:	:DEF: CFG_CPU_ARM926J

NCPU	SETA	NCPU+1

CFG_MMUPresent				SETL	{TRUE}

CFG_CachePresent			SETL	{TRUE}

CFG_WriteBufferPresent		SETL	{TRUE}

CFG_SplitCache				SETL	{TRUE}

CFG_SplitTLB				SETL	{TRUE}

CFG_WriteBackCache			SETL	{TRUE}

CFG_CacheFlushByWaySetIndex	SETL	{TRUE}

CFG_CachePolicyInPTE		SETL	{TRUE}

CFG_CacheTypeReg			SETL	{TRUE}

CFG_SingleEntryDCacheFlush	SETL	{TRUE}

CFG_SingleEntryICacheFlush	SETL	{TRUE}

CFG_SingleEntryITLBFlush	SETL	{TRUE}

CFG_FCSE_Present			SETL	{TRUE}

	IF	:DEF: CFG_CPU_ARM926J

CFG_Cpu_Has_CLZ				SETL	{TRUE}

	ENDIF

	IF	:DEF: CFG_CPU_ARM926J

	INIT_NUMERIC_CONSTANT	InitialMMUCR,	MMUCR_A+MMUCR_W+MMUCR_SBO+MMUCR_R+MMUCR_I+0x00050000

	ELSE

	INIT_NUMERIC_CONSTANT	InitialMMUCR,	MMUCR_A+MMUCR_W+MMUCR_SBO+MMUCR_R+MMUCR_I

	ENDIF

	IF	:DEF: CFG_CPU_ARM920T

	INIT_NUMERIC_CONSTANT	ExtraMMUCR,		MMUCR_M+MMUCR_C+MMUCR_V+0xC0000000	; FastBus + AsyncClock

	ELSE

	INIT_NUMERIC_CONSTANT	ExtraMMUCR,		MMUCR_M+MMUCR_C+MMUCR_V

	ENDIF

PDE_EXTRA					EQU		0x00000010

	ENDIF

;*******************************************************************************

	IF	:DEF: CFG_CPU_XSCALE

NCPU	SETA	NCPU+1

CFG_Cpu_Has_CLZ				SETL	{TRUE}

CFG_MMUPresent				SETL	{TRUE}

CFG_CachePresent			SETL	{TRUE}

CFG_WriteBufferPresent		SETL	{TRUE}

CFG_SplitCache				SETL	{TRUE}

CFG_SplitTLB				SETL	{TRUE}

	IF	:LNOT: :DEF: CFG_CPU_MANZANO

CFG_AltDCachePresent		SETL	{TRUE}

CFG_CacheFlushByLineAlloc	SETL	{TRUE}

	ENDIF

CFG_CacheWriteAllocate		SETL	{TRUE}

CFG_WriteBackCache			SETL	{TRUE}

CFG_SingleEntryDCacheFlush	SETL	{TRUE}

CFG_SingleEntryICacheFlush	SETL	{TRUE}

CFG_SingleEntryITLBFlush	SETL	{TRUE}

CFG_CachePolicyInPTE		SETL	{TRUE}

CFG_CacheTypeReg			SETL	{TRUE}

CFG_BTBPresent				SETL	{TRUE}

CFG_AuxCRPresent			SETL	{TRUE}

CFG_CARPresent				SETL	{TRUE}

CFG_FCSE_Present			SETL	{TRUE}

CFG_TEX						SETL	{TRUE}

	INIT_NUMERIC_CONSTANT	InitialMMUCR,	MMUCR_A+MMUCR_W+MMUCR_SBO+MMUCR_R+MMUCR_I

	IF	:DEF: CFG_HasXScaleL2Cache

	INIT_NUMERIC_CONSTANT	ExtraMMUCR,		MMUCR_M+MMUCR_C+MMUCR_V+MMUCR_Z+MMUCR_L2XSCALE

	ELSE

	INIT_NUMERIC_CONSTANT	ExtraMMUCR,		MMUCR_M+MMUCR_C+MMUCR_V+MMUCR_Z

	ENDIF

	INIT_NUMERIC_CONSTANT	DefaultAuxCRClear,	0xFFFFFFFF

	INIT_NUMERIC_CONSTANT	DefaultAuxCRSet,	0x00000020	; enable WB coalescing, minicache WTRA

PDE_EXTRA					EQU		0x00000000

	ENDIF

;*******************************************************************************

	IF	:DEF: CFG_CPU_ARM1136

NCPU	SETA	NCPU+1

CFG_ARMV6					SETL	{TRUE}

CFG_MMUPresent				SETL	{TRUE}

CFG_CachePresent			SETL	{TRUE}

CFG_CachePhysicalTag		SETL	{TRUE}

CFG_WriteBufferPresent		SETL	{TRUE}

CFG_SplitCache				SETL	{TRUE}

CFG_CacheWriteAllocate		SETL	{TRUE}

CFG_WriteBackCache			SETL	{TRUE}

CFG_CacheFlushByWaySetIndex	SETL	{TRUE}

CFG_SingleEntryDCacheFlush	SETL	{TRUE}

CFG_SingleEntryICacheFlush	SETL	{TRUE}

CFG_SingleEntryTLBFlush		SETL	{TRUE}

CFG_CachePolicyInPTE		SETL	{TRUE}

CFG_CacheTypeReg			SETL	{TRUE}

CFG_BTBPresent				SETL	{TRUE}

CFG_AuxCRPresent			SETL	{TRUE}

CFG_CARPresent				SETL	{TRUE}

CFG_PrefetchBuffer			SETL	{TRUE}

CFG_FCSE_Present			SETL	{TRUE}

CFG_ASID_Present			SETL	{TRUE}

CFG_Cpu_Has_CLZ				SETL	{TRUE}

CFG_TEX						SETL	{TRUE}

	IF  (:LNOT: :DEF: CFG_CPU_ARM1136_ERRATUM_399234_FIXED)

CFG_WriteThroughDisabled	SETL	{TRUE}

	ENDIF

	INIT_NUMERIC_CONSTANT	InitialMMUCR,	MMUCR_A+MMUCR_W+MMUCR_SBO+MMUCR_I+MMUCR_IT+MMUCR_DT

	INIT_NUMERIC_CONSTANT	ExtraMMUCR,		MMUCR_M+MMUCR_C+MMUCR_V+MMUCR_Z+MMUCR_XP+MMUCR_U

	INIT_NUMERIC_CONSTANT	DefaultAuxCRClear,	0x0000003F

	IF  (:LNOT: :DEF: CFG_CPU_ARM1136_ERRATUM_415662_FIXED :LOR: :LNOT: :DEF: CFG_CPU_ARM1136_ERRATUM_411920_FIXED)

	; base port should also ensure that BPR_AuxCRSet parameter (if used) has RV bit set

	INIT_NUMERIC_CONSTANT	DefaultAuxCRSet,	0x00000027	; enable static/dynamic/return prediction and

															; disable "Block Transfer Cache Operations" (RV bit)

	ELSE

	INIT_NUMERIC_CONSTANT	DefaultAuxCRSet,	0x00000007	; enable static/dynamic/return prediction

	ENDIF

PDE_EXTRA					EQU		0x00000000

	ENDIF

;*******************************************************************************

	IF	:DEF: CFG_CPU_ARM1176

NCPU	SETA	NCPU+1

CFG_ARMV6					SETL	{TRUE}

CFG_MMUPresent				SETL	{TRUE}

CFG_CachePresent			SETL	{TRUE}

CFG_CachePhysicalTag		SETL	{TRUE}

CFG_WriteBufferPresent		SETL	{TRUE}

CFG_SplitCache				SETL	{TRUE}

CFG_CacheWriteAllocate		SETL	{TRUE}

CFG_WriteBackCache			SETL	{TRUE}

CFG_CacheFlushByWaySetIndex	SETL	{TRUE}

CFG_SingleEntryDCacheFlush	SETL	{TRUE}

CFG_SingleEntryICacheFlush	SETL	{TRUE}

CFG_SingleEntryTLBFlush		SETL	{TRUE}

CFG_CachePolicyInPTE		SETL	{TRUE}

CFG_CacheTypeReg			SETL	{TRUE}

CFG_BTBPresent				SETL	{TRUE}

;CFG_AuxCRPresent			SETL	{TRUE} ;set to false because AuxCR is not write accessible in non-secure mode

CFG_CARPresent				SETL	{TRUE}

CFG_PrefetchBuffer			SETL	{TRUE}

CFG_FCSE_Present			SETL	{TRUE}

CFG_ASID_Present			SETL	{TRUE}

CFG_Cpu_Has_CLZ				SETL	{TRUE}

CFG_TEX						SETL	{TRUE}

CFG_MemoryTypeRemapping		SETL	{TRUE}

CFG_WriteThroughDisabled	SETL	{TRUE}

CFG_Cpu_Has_TrustZone		SETL	{TRUE}

	IF :LNOT: :DEF: CFG_TrustZone_Secure

CFG_TrustZone_NonSecure		SETL	{TRUE}

	ENDIF

	INIT_NUMERIC_CONSTANT	InitialMMUCR,	MMUCR_A+MMUCR_W+MMUCR_SBO+MMUCR_I+MMUCR_IT+MMUCR_DT+MMUCR_TRE+MMUCR_FA

	INIT_NUMERIC_CONSTANT	ExtraMMUCR,		MMUCR_M+MMUCR_C+MMUCR_V+MMUCR_Z+MMUCR_XP+MMUCR_U

	INIT_NUMERIC_CONSTANT	DefaultAuxCRClear,	0x0000003F

	IF  (:LNOT: :DEF: CFG_CPU_ARM1136_ERRATUM_411920_FIXED)

	; ARM1136 errata suggests this fix for 1176 as well

	; base port should also ensure that BPR_AuxCRSet parameter (if used) has RV bit set

	INIT_NUMERIC_CONSTANT	DefaultAuxCRSet,	0x00000027	; enable static/dynamic/return prediction and

															; disable "Block Transfer Cache Operations" (RV bit)

	ELSE

	INIT_NUMERIC_CONSTANT	DefaultAuxCRSet,	0x00000007	; enable static/dynamic/return prediction

	ENDIF

PDE_EXTRA					EQU		0x00000000

	ENDIF

;*******************************************************************************

	IF	:DEF: CFG_CPU_ARM11MP

NCPU	SETA	NCPU+1

CFG_ARMV6					SETL	{TRUE}

CFG_MMUPresent				SETL	{TRUE}

CFG_CachePresent			SETL	{TRUE}

CFG_CachePhysicalTag		SETL	{TRUE}

CFG_WriteBufferPresent		SETL	{TRUE}

CFG_SplitCache				SETL	{TRUE}

CFG_CacheWriteAllocate		SETL	{TRUE}

CFG_WriteBackCache			SETL	{TRUE}

CFG_CacheFlushByWaySetIndex	SETL	{TRUE}

CFG_SingleEntryDCacheFlush	SETL	{TRUE}

CFG_SingleEntryICacheFlush	SETL	{TRUE}

CFG_SingleEntryTLBFlush		SETL	{TRUE}

CFG_CachePolicyInPTE		SETL	{TRUE}

CFG_CacheTypeReg			SETL	{TRUE}

CFG_BTBPresent				SETL	{TRUE}

CFG_AuxCRPresent			SETL	{TRUE}

CFG_CARPresent				SETL	{TRUE}

CFG_PrefetchBuffer			SETL	{TRUE}

CFG_FCSE_Present			SETL	{TRUE}

CFG_ASID_Present			SETL	{TRUE}

CFG_TEX						SETL	{TRUE}

CFG_MemoryTypeRemapping		SETL	{TRUE}

CFG_Cpu_Has_CLZ				SETL	{TRUE}

CFG_WriteThroughDisabled	SETL	{TRUE}

CFG_Cpu_Has_WFE_SEV			SETL	{TRUE}

CFG_Cpu_Has_WFI				SETL	{TRUE}

	INIT_NUMERIC_CONSTANT	InitialMMUCR,	MMUCR_A+MMUCR_W+MMUCR_SBO+MMUCR_I+MMUCR_IT+MMUCR_DT+MMUCR_TRE+MMUCR_FA

	INIT_NUMERIC_CONSTANT	ExtraMMUCR,		MMUCR_M+MMUCR_C+MMUCR_V+MMUCR_Z+MMUCR_XP+MMUCR_U

	INIT_NUMERIC_CONSTANT	DefaultAuxCRClear,	0x0000003F

	IF :DEF: CFG_USE_SHARED_MEMORY

	INIT_NUMERIC_CONSTANT	SET_AUXSMP,	0x20

	ELSE

	INIT_NUMERIC_CONSTANT	SET_AUXSMP,	0x0

	ENDIF

	INIT_NUMERIC_CONSTANT	DefaultAuxCRSet,	0x00000007 | SET_AUXSMP	; enable static/dynamic/return prediction

PDE_EXTRA					EQU		0x00000000

	ENDIF

;*******************************************************************************

	IF	:DEF: CFG_CPU_CORTEX_A8N

	IF	:LNOT: :DEF: CFG_CPU_CORTEX_A8

	GBLL	CFG_CPU_CORTEX_A8

	ENDIF

	ENDIF

	IF	:DEF: CFG_CPU_CORTEX_A8

NCPU	SETA	NCPU+1

CFG_ARMV7					SETL	{TRUE}

CFG_MMUPresent				SETL	{TRUE}

CFG_CachePresent			SETL	{TRUE}

CFG_CachePhysicalTag		SETL	{TRUE}

CFG_WriteBufferPresent		SETL	{TRUE}

CFG_SplitCache				SETL	{TRUE}

CFG_AltDCachePresent		SETL	{TRUE}

CFG_CacheWriteAllocate		SETL	{TRUE}

CFG_WriteBackCache			SETL	{TRUE}

CFG_CacheFlushByWaySetIndex	SETL	{TRUE}

CFG_SingleEntryDCacheFlush	SETL	{TRUE}

CFG_SingleEntryICacheFlush	SETL	{TRUE}

CFG_SingleEntryTLBFlush		SETL	{TRUE}

CFG_CachePolicyInPTE		SETL	{TRUE}

CFG_CacheTypeReg			SETL	{TRUE}

CFG_BTBPresent				SETL	{TRUE}

CFG_CARPresent				SETL	{TRUE}

CFG_PrefetchBuffer			SETL	{TRUE}

CFG_FCSE_Present			SETL	{TRUE}

CFG_ASID_Present			SETL	{TRUE}

CFG_TEX						SETL	{TRUE}

CFG_Cpu_Has_CLZ				SETL	{TRUE}

CFG_Cpu_Has_TrustZone		SETL	{TRUE}

	IF :LNOT: :DEF: CFG_TrustZone_Secure

CFG_TrustZone_NonSecure		SETL	{TRUE}