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// Copyright (c) 2006-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// Cache maintenance primitives on ARMv7 (and later) platforms.
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// eka\kernel\arm\cachev7.cia
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//
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#include <e32cia.h>
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#include <arm.h>
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#include "cache_maintenance.h"
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#if defined(__CPU_ARMV7)
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// These constant defines LoC & LoU position in Cache Level ID Register
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const TInt KLoCMask = 0x07000000; // LoC field in CLIDR
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const TInt KLoCShift = 24;
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#if defined(__SMP__)
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// LoUIS seems to be not implemented on cortex_a9.
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//const TInt KLoUMask = 0x00e00000; // LoUIS field in CLIDR
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//const TInt KLoUShift = 21;
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const TInt KLoUMask = 0x38000000; // LoUU field in CLIDR
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const TInt KLoUShift = 27;
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#else
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const TInt KLoUMask = 0x38000000; // LoUU field in CLIDR
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const TInt KLoUShift = 27;
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#endif
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// These constant defines max values in Cache Size Id Register
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const TInt KAssocMax = 0x3ff; //Max value of associativity (10 bits reserved for this)
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const TInt KNumSetMax = 0x7fff; //MaxValue for Set Number (15 bits resrved for this)
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__NAKED__ TUint32 InternalCache::TypeRegister()
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{
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asm("mrc p15, 0, r0, c0, c0, 1 ");
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__JUMP(,lr);
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}
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__NAKED__ TUint32 InternalCache::LevelIDRegister()
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{
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asm("mrc p15, 1, r0, c0, c0, 1 ");
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__JUMP(,lr);
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}
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__NAKED__ TUint32 InternalCache::SizeIdRegister(TUint32 /*aType*/, TUint32 /*aLevel*/)
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{
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asm("orr r0, r1, lsl #1"); // r0 = entry for Cache Size Selection Reg.
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asm("mcr p15, 2, r0, c0, c0, 0 "); // set Cache Size Selection Register
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asm("mov r1, #0");
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ARM_ISBSY; // prefetchFlush to sync the change to the CacheSizeID reg
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asm("mrc p15, 1, r0, c0, c0, 0 "); // read Cache Size Id Register
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__JUMP(,lr);
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}
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__NAKED__ void InternalCache::DrainBuffers()
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{
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// Drain write buffer is rather archaic vocabulary from ARMv5.
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// On ARMv7, data & instruction sync barriers apply.
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asm("mov r0, #0 ");
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ARM_DSBSY;
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ARM_ISBSY;
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__JUMP(,lr);
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asm("__DCacheInfoPoU: ");
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asm(".word %a0" : : "i" ((TInt)&InternalCache::Info[KCacheInfoD_PoU]));
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asm("__DCacheInfoPoC: ");
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asm(".word %a0" : : "i" ((TInt)&InternalCache::Info[KCacheInfoD]));
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asm("__ICacheInfo: ");
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asm(".word %a0" : : "i" ((TInt)&InternalCache::Info[KCacheInfoI]));
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}
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__NAKED__ void InternalCache::IMB_CacheLine(TLinAddr /*aAddr*/)
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{
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asm("mov r1, #0 "); //will need zero reg for coprocessor instructions
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//--Round the address down to the start of line--//
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asm("ldr r2, __DCacheInfoPoU ");
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asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength));
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asm("sub ip, r3, #1 "); // ip=mask for offset within line
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asm("bic r0, r0, ip "); // r0 = cache line base
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DCCMVAU(r0); // Clean DCache line to Point-of-Unification
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ARM_DSBSY;
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ICIMVAU(r0);
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BPIMVA(r0);
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ARM_DSBSH;
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ARM_ISBSY;
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__JUMP(,lr);
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}
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__NAKED__ void InternalCache::Invalidate_ICache_Region(TLinAddr /*aBase*/, TUint /*aSize*/)
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{
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asm("ldr r2, __ICacheInfo ");
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asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength));
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asm("sub ip, r3, #1 "); // ip=mask for offset within line
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asm("and ip, ip, r0 "); // ip=offset of start address within line
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asm("add r1, r1, ip "); // add this to the size
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asm("sub ip, r3, #1 ");
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asm("bic r0, r0, ip "); // round base address down to start of line
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asm("add r1, r1, ip "); // round size up
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asm("1: ");
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asm("subs r1, r1, r3 "); // decrement size by line length
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asm("bcc 2f ");
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ICIMVAU(r0);
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asm("2: ");
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asm("add r0, r0, r3 "); // step address on
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asm("bhi 1b "); // loop if more lines
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#ifdef __SMP__ // }
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BPIALLIS; // } flush branch predictor
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#else // }
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BPIALL; // }
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#endif
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ARM_DSBSH;
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ARM_ISBSY;
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__JUMP(,lr);
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}
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__NAKED__ void InternalCache::Invalidate_ICache_All()
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{
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#ifdef __SMP__
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ICIALLUIS;
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// BPIALLIS; NOT NEEDED SINCE IT IS INCORPORATED IN ICIALLUIS
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ARM_DSBSH;
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#else
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ICIALLU;
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// BPIALL; NOT NEEDED SINCE IT IS INCORPORATED IN ICIALLU
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ARM_DSBSY;
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#endif
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ARM_ISBSY;
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__JUMP(,lr);
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}
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__NAKED__ void InternalCache::Invalidate_DCache_Region(TLinAddr /*aBase*/, TUint /*aSize*/)
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{
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asm("ldr r2, __DCacheInfoPoC ");
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asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength));
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asm("sub ip, r3, #1 "); // ip=mask for offset within line
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asm("and ip, ip, r0 "); // ip=offset of start address within line
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asm("add r1, r1, ip "); // add this to the size
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asm("sub ip, r3, #1 ");
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asm("bic r0, r0, ip "); // round base address down to start of line
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asm("add r1, r1, ip "); // round size up
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asm("1: ");
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asm("subs r1, r1, r3 "); // decrement size by line length
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asm("bcc 2f ");
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DCIMVAC(r0);
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asm("2: ");
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asm("add r0, r0, r3 "); // step address on
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asm("bhi 1b "); // loop if more lines
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ARM_DSBSY;
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ARM_ISBSY;
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__JUMP(,lr);
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}
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__NAKED__ void InternalCache::Clean_DCache_Region(TLinAddr /*aBase*/, TUint /*aSize*/)
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{
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asm("ldr r2, __DCacheInfoPoC ");
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asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength));
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asm("sub ip, r3, #1 "); // ip=mask for offset within line
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asm("and ip, ip, r0 "); // ip=offset of start address within line
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asm("add r1, r1, ip "); // add this to the size
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asm("sub ip, r3, #1 ");
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asm("bic r0, r0, ip "); // round base address down to start of line
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asm("add r1, r1, ip "); // round size up
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asm("1: ");
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asm("subs r1, r1, r3 "); // decrement size by line length
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asm("bcc 2f ");
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DCCMVAC(r0);
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#if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571771_FIXED)
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DCCMVAC(r13); // ARM Cortex-A9 MPCore erratum 571771 workaround
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// Execute additional cache clean to enforce barrier on other CPUs
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#endif
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asm("2: ");
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asm("add r0, r0, r3 "); // step address on
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asm("bhi 1b "); // loop if more lines
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ARM_DSBSY;
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ARM_ISBSY;
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__JUMP(,lr);
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}
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__NAKED__ void InternalCache::Clean_PoU_DCache_Region(TLinAddr /*aBase*/, TUint /*aSize*/)
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{
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asm("ldr r2, __DCacheInfoPoU ");
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asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength));
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asm("sub ip, r3, #1 "); // ip=mask for offset within line
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asm("and ip, ip, r0 "); // ip=offset of start address within line
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asm("add r1, r1, ip "); // add this to the size
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asm("sub ip, r3, #1 ");
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asm("bic r0, r0, ip "); // round base address down to start of line
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asm("add r1, r1, ip "); // round size up
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asm("1: ");
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asm("subs r1, r1, r3 "); // decrement size by line length
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asm("bcc 2f ");
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DCCMVAU(r0);
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asm("2: ");
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asm("add r0, r0, r3 "); // step address on
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asm("bhi 1b "); // loop if more lines
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ARM_DSBSH;
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ARM_ISBSY;
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__JUMP(,lr);
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}
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__NAKED__ void InternalCache::CleanAndInvalidate_DCache_Region(TLinAddr, TUint)
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{
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asm("ldr r2, __DCacheInfoPoC ");
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asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength));
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asm("sub ip, r3, #1 "); // ip=mask for offset within line
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asm("and ip, ip, r0 "); // ip=offset of start address within line
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asm("add r1, r1, ip "); // add this to the size
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asm("sub ip, r3, #1 ");
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asm("bic r0, r0, ip "); // round base address down to start of line
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asm("add r1, r1, ip "); // round size up
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asm("1: ");
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asm("subs r1, r1, r3 "); // decrement size by line length
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asm("bcc 2f ");
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DCCIMVAC(r0);
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#if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571771_FIXED)
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DCCIMVAC(r13); // ARM Cortex-A9 MPCore erratum 571771 workaround
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// Execute additional cache clean to enforce barrier on other CPUs
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#endif
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asm("2: ");
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asm("add r0, r0, r3 "); // step address on
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asm("bhi 1b "); // loop if more lines
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ARM_DSBSY;
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ARM_ISBSY;
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__JUMP(,lr);
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}
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__NAKED__ void InternalCache::Clean_DCache_All()
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{
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//NOTE: ON SMP THIS ONLY CLEANS THE CURRENT CPU CACHE, NOT OTHER CPU CACHES
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asm("stmfd sp!, {r4-r5,r7,r9-r11} ");
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asm("mrc p15, 1, r0, c0, c0, 1"); // Read CLIDR
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asm("ands r3, r0, #%a0" : : "i" ((TInt)KLoCMask));
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asm("mov r3, r3, lsr #%a0" : : "i" ((TInt)(KLoCShift-1))); // r3 = LoC << 1
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asm("beq 5f"); // ... and finish if LoC is zero
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asm("mov r10, #0"); // r10 = 0 (the current cache level)
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asm("1:");
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asm("add r2, r10, r10, lsr #1"); // Work out 3xcachelevel
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asm("mov r1, r0, LSR r2"); // bottom 3 bits are the Ctype for this level
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asm("and r1, r1, #7"); // get those 3 bits alone
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asm("cmp r1, #2");
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asm("blt 4f"); // no cache or only instruction cache at this level
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asm("mrs r4, cpsr"); // Disable interrupts while accessing CS Selection Reg &
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CPSIDAIF; // CS ID Reg.
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asm("mcr p15, 2, r10, c0, c0, 0"); // write the Cache Size selection register
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asm("mov r1, #0");
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ARM_ISBSY; // ISB to sync the change to the CacheSizeID reg
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asm("mrc p15, 1, r1, c0, c0, 0"); // reads current Cache Size ID register
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asm("msr cpsr_c, r4"); // Restore interrupts
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asm("and r2, r1, #7"); // extract the line length field
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asm("add r2, r2, #4"); // add 4 for the line length offset (log2 16 bytes)
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asm("ldr r4, =%a0" : : "i" ((TInt)KAssocMax));
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asm("ands r4, r4, r1, lsr #3"); // R4 is the max number on the way size (right aligned)
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CLZ(5,4); // R5 is the bit position of the way size increment
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asm("ldr r7, =%a0" : : "i" ((TInt)KNumSetMax));
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asm("ands r7, r7, r1, lsr #13"); // R7 is the max number of the index size (right aligned)
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asm("2:");
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asm("mov r9, r4"); // R9 working copy of the max way size (right aligned)
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asm("3:");
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asm("orr r11, r10, r9, lsl r5"); // factor in the way number and cache number into R11
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asm("orr r11, r11, r7, lsl r2"); // factor in the index number
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DCCSW(r11); // clean by set/way
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asm("subs r9, r9, #1"); // decrement the way number
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asm("bge 3b");
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asm("subs r7, r7, #1"); // decrement the index
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asm("bge 2b");
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asm("4:"); // SKIP
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asm("add r10, r10, #2"); // increment the cache number
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asm("cmp r3, r10");
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asm("bgt 1b");
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ARM_DSBSY;
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ARM_ISBSY;
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asm("5:"); // FINISHED
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asm("ldmfd sp!, {r4-r5,r7,r9-r11} "); // restore registers
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__JUMP(,lr);
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}
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__NAKED__ void InternalCache::CleanAndInvalidate_DCache_All()
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{
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//NOTE: ON SMP THIS ONLY CLEANS AND INVALIDATES THE CURRENT CPU CACHE, NOT OTHER CPU CACHES
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asm("stmfd sp!, {r4-r5,r7,r9-r11} ");
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asm("mrc p15, 1, r0, c0, c0, 1"); // Read CLIDR
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asm("ands r3, r0, #%a0" : : "i" ((TInt)KLoCMask));
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asm("mov r3, r3, lsr #%a0" : : "i" ((TInt)(KLoCShift-1))); // r3 = LoC << 1
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asm("beq 5f"); // ... and finish if LoC is zero
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asm("mov r10, #0"); // r10 = 0 (the current cache level)
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asm("1:");
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asm("add r2, r10, r10, lsr #1"); // Work out 3xcachelevel
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asm("mov r1, r0, LSR r2"); // bottom 3 bits are the Ctype for this level
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asm("and r1, r1, #7"); // get those 3 bits alone
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asm("cmp r1, #2");
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asm("blt 4f"); // no cache or only instruction cache at this level
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asm("mrs r4, cpsr"); // Disable interrupts while accessing CS Selection Reg &
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CPSIDAIF; // CS ID Reg.
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asm("mcr p15, 2, r10, c0, c0, 0"); // write the Cache Size selection register
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asm("mov r1, #0");
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ARM_ISBSY; // ISB to sync the change to the CacheSizeID reg
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asm("mrc p15, 1, r1, c0, c0, 0"); // reads current Cache Size ID register
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asm("msr cpsr_c, r4"); // Restore interrupts
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asm("and r2, r1, #7"); // extract the line length field
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asm("add r2, r2, #4"); // add 4 for the line length offset (log2 16 bytes)
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asm("ldr r4, =%a0" : : "i" ((TInt)KAssocMax));
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asm("ands r4, r4, r1, lsr #3"); // R4 is the max number on the way size (right aligned)
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CLZ(5,4); // R5 is the bit position of the way size increment
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asm("ldr r7, =%a0" : : "i" ((TInt)KNumSetMax));
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asm("ands r7, r7, r1, lsr #13"); // R7 is the max number of the index size (right aligned)
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asm("2:");
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asm("mov r9, r4"); // R9 working copy of the max way size (right aligned)
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asm("3:");
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asm("orr r11, r10, r9, lsl r5"); // factor in the way number and cache number into R11
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asm("orr r11, r11, r7, lsl r2"); // factor in the index number
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|
338 |
DCCISW(r11); // clean and invalidate by set/way
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|
339 |
asm("subs r9, r9, #1"); // decrement the way number
|
|
340 |
asm("bge 3b");
|
|
341 |
asm("subs r7, r7, #1"); // decrement the index
|
|
342 |
asm("bge 2b");
|
|
343 |
|
|
344 |
asm("4:"); // SKIP
|
|
345 |
asm("add r10, r10, #2"); // increment the cache number
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|
346 |
asm("cmp r3, r10");
|
|
347 |
asm("bgt 1b");
|
|
348 |
ARM_DSBSY;
|
|
349 |
ARM_ISBSY;
|
|
350 |
|
|
351 |
asm("5:"); // FINISHED
|
|
352 |
asm("ldmfd sp!, {r4-r5,r7,r9-r11} "); // restore registers
|
|
353 |
__JUMP(,lr);
|
|
354 |
}
|
|
355 |
|
|
356 |
__NAKED__ void InternalCache::Clean_PoU_DCache_All()
|
|
357 |
{
|
|
358 |
// NOTE: ON SMP THIS ONLY CLEANS THE CURRENT CPU CACHE, NOT OTHER CPU CACHES
|
|
359 |
asm("stmfd sp!, {r4-r5,r7,r9-r11} ");
|
|
360 |
asm("mrc p15, 1, r0, c0, c0, 1"); // Read CLIDR
|
|
361 |
asm("ands r3, r0, #%a0" : : "i" ((TInt)KLoUMask));
|
|
362 |
asm("mov r3, r3, lsr #%a0" : : "i" ((TInt)(KLoUShift-1))); // r3 = LoU << 1
|
|
363 |
asm("beq 5f"); // ... and finish if LoU is zero
|
|
364 |
asm("mov r10, #0"); // r10 = 0 (the current cache level)
|
|
365 |
|
|
366 |
asm("1:");
|
|
367 |
asm("add r2, r10, r10, lsr #1"); // Work out 3xcachelevel
|
|
368 |
asm("mov r1, r0, LSR r2"); // bottom 3 bits are the Ctype for this level
|
|
369 |
asm("and r1, r1, #7"); // get those 3 bits alone
|
|
370 |
asm("cmp r1, #2");
|
|
371 |
asm("blt 4f"); // no cache or only instruction cache at this level
|
|
372 |
|
|
373 |
asm("mrs r4, cpsr"); // Disable interrupts while accessing CS Selection Reg &
|
|
374 |
CPSIDAIF; // CS ID Reg.
|
|
375 |
|
|
376 |
asm("mcr p15, 2, r10, c0, c0, 0"); // write the Cache Size selection register
|
|
377 |
asm("mov r1, #0");
|
|
378 |
ARM_ISBSY; // ISB to sync the change to the CacheSizeID reg
|
|
379 |
asm("mrc p15, 1, r1, c0, c0, 0"); // reads current Cache Size ID register
|
|
380 |
|
|
381 |
asm("msr cpsr_c, r4"); // Restore interrupts
|
|
382 |
|
|
383 |
asm("and r2, r1, #7"); // extract the line length field
|
|
384 |
asm("add r2, r2, #4"); // add 4 for the line length offset (log2 16 bytes)
|
|
385 |
asm("ldr r4, =%a0" : : "i" ((TInt)KAssocMax));
|
|
386 |
asm("ands r4, r4, r1, lsr #3"); // R4 is the max number on the way size (right aligned)
|
|
387 |
CLZ(5,4); // R5 is the bit position of the way size increment
|
|
388 |
asm("ldr r7, =%a0" : : "i" ((TInt)KNumSetMax));
|
|
389 |
asm("ands r7, r7, r1, lsr #13"); // R7 is the max number of the index size (right aligned)
|
|
390 |
|
|
391 |
asm("2:");
|
|
392 |
asm("mov r9, r4"); // R9 working copy of the max way size (right aligned)
|
|
393 |
|
|
394 |
asm("3:");
|
|
395 |
asm("orr r11, r10, r9, lsl r5"); // factor in the way number and cache number into R11
|
|
396 |
asm("orr r11, r11, r7, lsl r2"); // factor in the index number
|
|
397 |
DCCSW(r11); // clean by set/way
|
|
398 |
asm("subs r9, r9, #1"); // decrement the way number
|
|
399 |
asm("bge 3b");
|
|
400 |
asm("subs r7, r7, #1"); // decrement the index
|
|
401 |
asm("bge 2b");
|
|
402 |
|
|
403 |
asm("4:"); // SKIP
|
|
404 |
asm("add r10, r10, #2"); // increment the cache number
|
|
405 |
asm("cmp r3, r10");
|
|
406 |
asm("bgt 1b");
|
|
407 |
ARM_DSBSY;
|
|
408 |
ARM_ISBSY;
|
|
409 |
|
|
410 |
asm("5:"); // FINISHED
|
|
411 |
asm("ldmfd sp!, {r4-r5,r7,r9-r11} "); // restore registers
|
|
412 |
__JUMP(,lr);
|
|
413 |
}
|
|
414 |
|
|
415 |
#if defined(__BROADCAST_ISB)
|
|
416 |
__NAKED__ void T_ISB_IPI::ISBIsr(TGenericIPI* /*aPtr*/)
|
|
417 |
{
|
|
418 |
ARM_ISBSY;
|
|
419 |
__JUMP(,lr);
|
|
420 |
}
|
|
421 |
#endif //defined(__BROADCAST_ISB)
|
|
422 |
|
|
423 |
#endif //#if defined(__CPU_ARMV7)
|