| author | Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com> |
| Fri, 14 May 2010 17:13:29 +0300 | |
| changeset 109 | b3a1d9898418 |
| parent 36 | 538db54a451d |
| child 257 | 3e88ff8f41d5 |
| child 279 | 957c583b417b |
| permissions | -rw-r--r-- |
| 0 | 1 |
// Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies). |
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// All rights reserved. |
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// This component and the accompanying materials are made available |
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// under the terms of the License "Eclipse Public License v1.0" |
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// which accompanies this distribution, and is available |
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// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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// |
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// Initial Contributors: |
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// Nokia Corporation - initial contribution. |
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// |
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// Contributors: |
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// |
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// Description: |
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// |
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#include <x86_mem.h> |
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#include "cache_maintenance.inl" |
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#include "execs.h" |
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#include "mm.h" |
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#include "mmu.h" |
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#include "mpager.h" |
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#include "mpdalloc.h" |
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TPte PteGlobal; // =0x100 on processors which support global pages, 0 on processors which don't |
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#if defined(KMMU) |
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extern "C" void __DebugMsgFlushTLB() |
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{
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__KTRACE_OPT(KMMU,Kern::Printf("FlushTLB"));
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} |
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extern "C" void __DebugMsgLocalFlushTLB() |
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{
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__KTRACE_OPT(KMMU,Kern::Printf("FlushTLB"));
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} |
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extern "C" void __DebugMsgINVLPG(int a) |
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{
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__KTRACE_OPT(KMMU,Kern::Printf("INVLPG(%08x)",a));
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} |
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#endif |
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extern void DoLocalInvalidateTLB(); |
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#ifndef __SMP__ |
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FORCE_INLINE void LocalInvalidateTLB() |
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{
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DoLocalInvalidateTLB(); |
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} |
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#else // __SMP__ |
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const TInt KMaxPages = 1; |
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class TTLBIPI : public TGenericIPI |
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{
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public: |
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TTLBIPI(); |
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static void InvalidateForPagesIsr(TGenericIPI*); |
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static void LocalInvalidateIsr(TGenericIPI*); |
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static void InvalidateIsr(TGenericIPI*); |
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static void WaitAndInvalidateIsr(TGenericIPI*); |
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void AddAddress(TLinAddr aAddr); |
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void InvalidateList(); |
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public: |
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volatile TInt iFlag; |
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TInt iCount; |
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TLinAddr iAddr[KMaxPages]; |
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}; |
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TTLBIPI::TTLBIPI() |
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: iFlag(0), iCount(0) |
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{
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} |
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void TTLBIPI::LocalInvalidateIsr(TGenericIPI*) |
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{
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TRACE2(("TLBLocInv"));
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DoLocalInvalidateTLB(); |
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} |
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void TTLBIPI::InvalidateIsr(TGenericIPI*) |
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{
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TRACE2(("TLBInv"));
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DoInvalidateTLB(); |
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} |
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void TTLBIPI::WaitAndInvalidateIsr(TGenericIPI* aTLBIPI) |
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{
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TRACE2(("TLBWtInv"));
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TTLBIPI& a = *(TTLBIPI*)aTLBIPI; |
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while (!a.iFlag) |
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{}
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if (a.iCount == 1) |
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DoInvalidateTLBForPage(a.iAddr[0]); |
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else |
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DoInvalidateTLB(); |
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} |
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void TTLBIPI::InvalidateForPagesIsr(TGenericIPI* aTLBIPI) |
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{
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TTLBIPI& a = *(TTLBIPI*)aTLBIPI; |
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TInt i; |
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for (i=0; i<a.iCount; ++i) |
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{
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TRACE2(("TLBInv %08x", a.iAddr[i]));
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DoInvalidateTLBForPage(a.iAddr[i]); |
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} |
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} |
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void TTLBIPI::AddAddress(TLinAddr aAddr) |
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{
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iAddr[iCount] = aAddr; |
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if (++iCount == KMaxPages) |
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InvalidateList(); |
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} |
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void TTLBIPI::InvalidateList() |
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{
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NKern::Lock(); |
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InvalidateForPagesIsr(this); |
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QueueAllOther(&InvalidateForPagesIsr); |
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NKern::Unlock(); |
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WaitCompletion(); |
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iCount = 0; |
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} |
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void LocalInvalidateTLB() |
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{
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TTLBIPI ipi; |
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NKern::Lock(); |
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DoLocalInvalidateTLB(); |
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ipi.QueueAllOther(&TTLBIPI::LocalInvalidateIsr); |
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NKern::Unlock(); |
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ipi.WaitCompletion(); |
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} |
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void InvalidateTLB() |
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{
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TTLBIPI ipi; |
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NKern::Lock(); |
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DoInvalidateTLB(); |
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ipi.QueueAllOther(&TTLBIPI::InvalidateIsr); |
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NKern::Unlock(); |
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ipi.WaitCompletion(); |
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} |
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void InvalidateTLBForPage(TLinAddr aAddr) |
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{
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TTLBIPI ipi; |
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ipi.AddAddress(aAddr); |
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ipi.InvalidateList(); |
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} |
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#endif // __SMP__ |
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void InvalidateTLBForAsid(TUint aAsid) |
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{
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if(aAsid==KKernelOsAsid) |
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InvalidateTLB(); |
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else |
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LocalInvalidateTLB(); |
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} |
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void SinglePdeUpdated(TPde* aPde) |
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{
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CacheMaintenance::SinglePdeUpdated((TLinAddr)aPde); |
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PageDirectories.GlobalPdeChanged(aPde); |
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} |
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// |
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// Functions for class Mmu |
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// |
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TPhysAddr Mmu::PtePhysAddr(TPte aPte, TUint /*aPteIndex*/) |
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{
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if(aPte&KPdePtePresent) |
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return aPte & KPdePtePhysAddrMask; |
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return KPhysAddrInvalid; |
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} |
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TPte* Mmu::PageTableFromPde(TPde aPde) |
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{
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if((aPde&(KPdeLargePage|KPdePtePresent)) == KPdePtePresent) |
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{
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SPageInfo* pi = SPageInfo::FromPhysAddr(aPde); |
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TInt id = (pi->Index()<<KPtClusterShift) | ((aPde>>KPageTableShift)&KPtClusterMask); |
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return (TPte*)(KPageTableBase+(id<<KPageTableShift)); |
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} |
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return 0; |
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} |
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TPte* Mmu::SafePageTableFromPde(TPde aPde) |
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{
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if((aPde&(KPdeLargePage|KPdePtePresent)) == KPdePtePresent) |
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{
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SPageInfo* pi = SPageInfo::SafeFromPhysAddr(aPde&~KPageMask); |
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if(pi) |
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{
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TInt id = (pi->Index()<<KPtClusterShift) | ((aPde>>KPageTableShift)&KPtClusterMask); |
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return (TPte*)(KPageTableBase+(id<<KPageTableShift)); |
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} |
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} |
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return 0; |
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} |
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/** |
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Return the base phsical address of the section table referenced by the given |
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Page Directory Entry (PDE) \a aPde. If the PDE doesn't refer to a |
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section then KPhysAddrInvalid is returned. |
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@pre #MmuLock held. |
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*/ |
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TPhysAddr Mmu::SectionBaseFromPde(TPde aPde) |
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{
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if(PdeMapsSection(aPde)) |
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return aPde&KPdeLargePagePhysAddrMask; |
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return KPhysAddrInvalid; |
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} |
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TPte* Mmu::PtePtrFromLinAddr(TLinAddr aAddress, TInt aOsAsid) |
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{
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TPde pde = PageDirectory(aOsAsid)[aAddress>>KChunkShift]; |
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SPageInfo* pi = SPageInfo::FromPhysAddr(pde); |
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TPte* pt = (TPte*)(KPageTableBase+(pi->Index()<<KPageShift)+(pde&(KPageMask&~KPageTableMask))); |
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pt += (aAddress>>KPageShift)&(KChunkMask>>KPageShift); |
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return pt; |
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} |
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TPte* Mmu::SafePtePtrFromLinAddr(TLinAddr aAddress, TInt aOsAsid) |
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{
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TPde pde = PageDirectory(aOsAsid)[aAddress>>KChunkShift]; |
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TPte* pt = SafePageTableFromPde(pde); |
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if(pt) |
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pt += (aAddress>>KPageShift)&(KChunkMask>>KPageShift); |
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return pt; |
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} |
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TPhysAddr Mmu::PageTablePhysAddr(TPte* aPt) |
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{
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__NK_ASSERT_DEBUG(MmuLock::IsHeld() || PageTablesLockIsHeld()); |
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TInt pdeIndex = ((TLinAddr)aPt)>>KChunkShift; |
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TPde pde = PageDirectory(KKernelOsAsid)[pdeIndex]; |
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__NK_ASSERT_DEBUG((pde&(KPdePtePresent|KPdeLargePage))==KPdePtePresent); |
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SPageInfo* pi = SPageInfo::FromPhysAddr(pde); |
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TPte* pPte = (TPte*)(KPageTableBase+(pi->Index(true)<<KPageShift)); |
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TPte pte = pPte[(((TLinAddr)aPt)&KChunkMask)>>KPageShift]; |
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__NK_ASSERT_DEBUG(pte & KPdePtePresent); |
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return pte&KPdePtePhysAddrMask; |
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} |
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TPhysAddr Mmu::UncheckedLinearToPhysical(TLinAddr aLinAddr, TInt aOsAsid) |
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{
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TRACE2(("Mmu::UncheckedLinearToPhysical(%08x,%d)",aLinAddr,aOsAsid));
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TInt pdeIndex = aLinAddr>>KChunkShift; |
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TPde pde = PageDirectory(aOsAsid)[pdeIndex]; |
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TPhysAddr pa=KPhysAddrInvalid; |
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if (pde & KPdePtePresent) |
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{
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if(pde&KPdeLargePage) |
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{
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pa=(pde&KPdeLargePagePhysAddrMask)+(aLinAddr&~KPdeLargePagePhysAddrMask); |
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__KTRACE_OPT(KMMU,Kern::Printf("Mapped with large table - returning %08x",pa));
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} |
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else |
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{
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SPageInfo* pi = SPageInfo::FromPhysAddr(pde); |
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TInt id = (pi->Index(true)<<KPtClusterShift) | ((pde>>KPageTableShift)&KPtClusterMask); |
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TPte* pPte = (TPte*)(KPageTableBase+(id<<KPageTableShift)); |
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TPte pte = pPte[(aLinAddr&KChunkMask)>>KPageShift]; |
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if (pte & KPdePtePresent) |
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{
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pa=(pte&KPdePtePhysAddrMask)+(aLinAddr&KPageMask); |
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__KTRACE_OPT(KMMU,Kern::Printf("Mapped with page table - returning %08x",pa));
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} |
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} |
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} |
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return pa; |
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} |
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void Mmu::Init1() |
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{
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TRACEB(("Mmu::Init1"));
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TUint pge = TheSuperPage().iCpuId & EX86Feat_PGE; |
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PteGlobal = pge ? KPdePteGlobal : 0; |
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X86_UseGlobalPTEs = pge!=0; |
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#ifdef __SMP__ |
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ApTrampolinePage = KApTrampolinePageLin; |
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TInt i; |
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for (i=0; i<KMaxCpus; ++i) |
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{
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TSubScheduler& ss = TheSubSchedulers[i]; |
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TLinAddr a = KIPCAlias + (i<<KChunkShift); |
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ss.i_AliasLinAddr = (TAny*)a; |
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ss.i_AliasPdePtr = (TAny*)(KPageDirectoryBase + (a>>KChunkShift)*sizeof(TPde)); |
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} |
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#endif |
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Init1Common(); |
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} |
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void Mmu::Init2() |
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{
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TRACEB(("Mmu::Init2"));
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Init2Common(); |
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} |
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void Mmu::Init2Final() |
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{
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TRACEB(("Mmu::Init2Final"));
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Init2FinalCommon(); |
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} |
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const TPde KPdeForBlankPageTable = KPdePtePresent|KPdePteWrite|KPdePteUser; |
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TPde Mmu::BlankPde(TMemoryAttributes aAttributes) |
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{
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(void)aAttributes; |
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TPde pde = KPdeForBlankPageTable; |
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TRACE2(("Mmu::BlankPde(%x) returns 0x%x",aAttributes,pde));
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return pde; |
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} |
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TPde Mmu::BlankSectionPde(TMemoryAttributes aAttributes, TUint aPteType) |
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{
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return PageToSectionEntry(BlankPte(aAttributes, aPteType), KPdeForBlankPageTable); |
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} |
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TPte Mmu::BlankPte(TMemoryAttributes aAttributes, TUint aPteType) |
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{
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TPte pte = KPdePtePresent; |
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if(aPteType&EPteTypeUserAccess) |
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pte |= KPdePteUser; |
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if(aPteType&EPteTypeWritable) |
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pte |= KPdePteWrite; |
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if(aPteType&EPteTypeGlobal) |
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pte |= PteGlobal; |
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switch((TMemoryType)(aAttributes&EMemoryAttributeTypeMask)) |
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{
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case EMemAttStronglyOrdered: |
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case EMemAttDevice: |
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case EMemAttNormalUncached: |
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pte |= KPdePteUncached; |
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break; |
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case EMemAttNormalCached: |
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break; |
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default: |
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__NK_ASSERT_ALWAYS(0); |
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break; |
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} |
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TRACE2(("Mmu::BlankPte(%x,%x) returns 0x%x",aAttributes,aPteType,pte));
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return pte; |
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} |
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TPte Mmu::SectionToPageEntry(TPde& aPde) |
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{
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TPte pte = aPde&~(KPdePtePhysAddrMask|KPdeLargePage); |
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aPde = KPdeForBlankPageTable; |
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return pte; |
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} |
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TPde Mmu::PageToSectionEntry(TPte aPte, TPde /*aPde*/) |
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{
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TPte pde = aPte&~KPdeLargePagePhysAddrMask; |
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pde |= KPdeLargePage; |
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return pde; |
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} |
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TMemoryAttributes Mmu::CanonicalMemoryAttributes(TMemoryAttributes aAttr) |
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{
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TUint attr = aAttr; |
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if(attr&EMemoryAttributeDefaultShareable) |
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{
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// sharing not specified, use default... |
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#if defined (__CPU_USE_SHARED_MEMORY) |
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attr |= EMemoryAttributeShareable; |
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#else |
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attr &= ~EMemoryAttributeShareable; |
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#endif |
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} |
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// remove invalid attributes... |
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attr &= ~(EMemoryAttributeUseECC); |
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return (TMemoryAttributes)(attr&EMemoryAttributeMask); |
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} |
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423 |
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void Mmu::PagesAllocated(TPhysAddr* aPageList, TUint aCount, TRamAllocFlags aFlags, TBool aReallocate) |
|
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{
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TRACE2(("Mmu::PagesAllocated(0x%08x,%d,0x%x,%d)",aPageList, aCount, aFlags, (bool)aReallocate));
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__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
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TBool wipe = !(aFlags&EAllocNoWipe); // do we need to wipe page contents? |
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TMemoryType newType = (TMemoryType)(aFlags&KMemoryTypeMask); // memory type that pages will be used for |
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TUint8 wipeByte = (aFlags&EAllocUseCustomWipeByte) ? (aFlags>>EAllocWipeByteShift)&0xff : 0x03; // value to wipe memory with |
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433 |
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// process each page in turn... |
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while(aCount--) |
|
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{
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|
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// get physical address of next page... |
|
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TPhysAddr pagePhys; |
|
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if((TPhysAddr)aPageList&1) |
|
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{
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// aPageList is actually the physical address to use... |
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pagePhys = (TPhysAddr)aPageList&~1; |
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*(TPhysAddr*)&aPageList += KPageSize; |
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} |
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else |
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pagePhys = *aPageList++; |
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__NK_ASSERT_DEBUG((pagePhys&KPageMask)==0); |
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// get info about page... |
|
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SPageInfo* pi = SPageInfo::FromPhysAddr(pagePhys); |
|
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TMemoryType oldType = (TMemoryType)(pi->Flags(true)&KMemoryTypeMask); |
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||
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TRACE2(("Mmu::PagesAllocated page=0x%08x, oldType=%d, wipe=%d",pagePhys,oldType,wipe));
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if(wipe) |
|
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{
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|
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// work out temporary mapping values... |
|
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TLinAddr tempLinAddr = iTempMap[0].iLinAddr; |
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TPte* tempPte = iTempMap[0].iPtePtr; |
|
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||
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// temporarily map page... |
|
461 |
*tempPte = pagePhys | iTempPteCached; |
|
462 |
CacheMaintenance::SinglePteUpdated((TLinAddr)tempPte); |
|
463 |
InvalidateTLBForPage(tempLinAddr|KKernelOsAsid); |
|
464 |
||
465 |
// wipe contents of memory... |
|
466 |
memset((TAny*)tempLinAddr, wipeByte, KPageSize); |
|
467 |
__e32_io_completion_barrier(); |
|
468 |
||
469 |
// invalidate temporary mapping... |
|
470 |
*tempPte = KPteUnallocatedEntry; |
|
471 |
CacheMaintenance::SinglePteUpdated((TLinAddr)tempPte); |
|
472 |
InvalidateTLBForPage(tempLinAddr|KKernelOsAsid); |
|
473 |
} |
|
474 |
||
475 |
// indicate page has been allocated... |
|
476 |
if(aReallocate==false) |
|
477 |
pi->SetAllocated(); |
|
478 |
} |
|
479 |
} |
|
480 |
||
481 |
||
482 |
void Mmu::PageFreed(SPageInfo* aPageInfo) |
|
483 |
{
|
|
484 |
__NK_ASSERT_DEBUG(MmuLock::IsHeld()); |
|
485 |
||
486 |
if(aPageInfo->Type()==SPageInfo::EUnused) |
|
487 |
return; |
|
488 |
||
489 |
aPageInfo->SetUnused(); |
|
490 |
||
491 |
TRACE2(("Mmu::PageFreed page=0x%08x type=%d colour=%d",aPageInfo->PhysAddr(),aPageInfo->Flags()&KMemoryTypeMask,aPageInfo->Index()&KPageColourMask));
|
|
492 |
} |
|
493 |
||
494 |
||
495 |
void Mmu::CleanAndInvalidatePages(TPhysAddr* aPages, TUint aCount, TMemoryAttributes aAttributes, TUint aColour) |
|
496 |
{
|
|
497 |
TMemoryType type = (TMemoryType)(aAttributes&EMemoryAttributeTypeMask); |
|
498 |
if(!CacheMaintenance::IsCached(type)) |
|
499 |
{
|
|
500 |
TRACE2(("Mmu::CleanAndInvalidatePages - nothing to do"));
|
|
501 |
return; |
|
502 |
} |
|
503 |
||
504 |
RamAllocLock::Lock(); |
|
505 |
||
506 |
while(aCount--) |
|
507 |
{
|
|
508 |
TPhysAddr pagePhys = *aPages++; |
|
509 |
TRACE2(("Mmu::CleanAndInvalidatePages 0x%08x",pagePhys));
|
|
510 |
||
511 |
// work out temporary mapping values... |
|
512 |
TLinAddr tempLinAddr = iTempMap[0].iLinAddr; |
|
513 |
TPte* tempPte = iTempMap[0].iPtePtr; |
|
514 |
||
515 |
// temporarily map page... |
|
516 |
*tempPte = pagePhys | iTempPteCached; |
|
517 |
CacheMaintenance::SinglePteUpdated((TLinAddr)tempPte); |
|
518 |
InvalidateTLBForPage(tempLinAddr|KKernelOsAsid); |
|
519 |
||
520 |
// sort out cache for memory reuse... |
|
521 |
CacheMaintenance::PageToPreserveAndReuse(tempLinAddr, type, KPageSize); |
|
522 |
||
523 |
// invalidate temporary mapping... |
|
524 |
*tempPte = KPteUnallocatedEntry; |
|
525 |
CacheMaintenance::SinglePteUpdated((TLinAddr)tempPte); |
|
526 |
InvalidateTLBForPage(tempLinAddr|KKernelOsAsid); |
|
527 |
||
528 |
RamAllocLock::Flash(); |
|
529 |
} |
|
530 |
RamAllocLock::Unlock(); |
|
531 |
} |
|
532 |
||
533 |
||
534 |
TInt DMemModelThread::Alias(TLinAddr aAddr, DMemModelProcess* aProcess, TInt aSize, TLinAddr& aAliasAddr, TUint& aAliasSize) |
|
535 |
// |
|
536 |
// Set up an alias mapping starting at address aAddr in specified process. |
|
537 |
// Note: Alias is removed if an exception is trapped by DThread::IpcExcHandler. |
|
538 |
// |
|
539 |
{
|
|
540 |
TRACE2(("Thread %O Alias %08x+%x Process %O",this,aAddr,aSize,aProcess));
|
|
541 |
__NK_ASSERT_DEBUG(this==TheCurrentThread); // many bad things can happen if false |
|
542 |
// If there is an existing alias it should be on the same process otherwise |
|
543 |
// the os asid reference may be leaked. |
|
544 |
__NK_ASSERT_DEBUG(!iAliasLinAddr || aProcess == iAliasProcess); |
|
545 |
||
546 |
if(TUint(aAddr^KIPCAlias)<TUint(KIPCAliasAreaSize)) |
|
547 |
return KErrBadDescriptor; // prevent access to alias region |
|
548 |
||
|
109
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Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
549 |
#ifdef _DEBUG |
|
b3a1d9898418
Revision: 201019
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
550 |
if (KDebugNum(KFORCEKUPAGEFAULTS)) |
|
b3a1d9898418
Revision: 201019
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
551 |
{
|
|
b3a1d9898418
Revision: 201019
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
552 |
TInt r = ThePager.FlushRegion(aProcess, aAddr, aSize); |
|
b3a1d9898418
Revision: 201019
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
553 |
if (r != KErrNone) |
|
b3a1d9898418
Revision: 201019
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
554 |
return r; |
|
b3a1d9898418
Revision: 201019
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
555 |
} |
|
b3a1d9898418
Revision: 201019
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
556 |
#endif |
|
b3a1d9898418
Revision: 201019
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
557 |
|
| 0 | 558 |
// Grab the mmu lock before opening a reference on os asid so that this thread |
559 |
// is in an implicit critical section and therefore can't leak the reference by |
|
560 |
// dying before iAliasLinAddr is set. |
|
561 |
MmuLock::Lock(); |
|
562 |
||
563 |
TInt osAsid; |
|
564 |
if (!iAliasLinAddr) |
|
565 |
{// There isn't any existing alias.
|
|
566 |
// Open a reference on the aProcess's os asid so that it is not freed and/or reused |
|
567 |
// while we are aliasing an address belonging to it. |
|
568 |
osAsid = aProcess->TryOpenOsAsid(); |
|
569 |
if (osAsid < 0) |
|
570 |
{// Couldn't open os asid so aProcess is no longer running.
|
|
571 |
MmuLock::Unlock(); |
|
572 |
return KErrBadDescriptor; |
|
573 |
} |
|
574 |
} |
|
575 |
else |
|
576 |
{
|
|
577 |
// Just read the os asid of the process being aliased we already have a reference on it. |
|
578 |
osAsid = aProcess->OsAsid(); |
|
579 |
} |
|
580 |
||
581 |
// Now we have the os asid check access to kernel memory. |
|
582 |
if(aAddr >= KUserMemoryLimit && osAsid != (TUint)KKernelOsAsid) |
|
583 |
{
|
|
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
584 |
NKern::ThreadEnterCS(); |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
585 |
MmuLock::Unlock(); |
| 0 | 586 |
if (!iAliasLinAddr) |
587 |
{// Close the new reference as RemoveAlias won't do as iAliasLinAddr is not set.
|
|
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
588 |
aProcess->AsyncCloseOsAsid(); // Asynchronous close as this method should be quick. |
| 0 | 589 |
} |
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
590 |
NKern::ThreadLeaveCS(); |
| 0 | 591 |
return KErrBadDescriptor; // prevent access to supervisor only memory |
592 |
} |
|
593 |
||
594 |
// Now we know all accesses to global memory are safe so check if aAddr is global. |
|
595 |
if(aAddr >= KGlobalMemoryBase) |
|
596 |
{
|
|
597 |
// address is in global section, don't bother aliasing it... |
|
598 |
if (!iAliasLinAddr) |
|
599 |
{// Close the new reference as not required.
|
|
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
600 |
NKern::ThreadEnterCS(); |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
601 |
MmuLock::Unlock(); |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
602 |
aProcess->AsyncCloseOsAsid(); // Asynchronous close as this method should be quick. |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
603 |
NKern::ThreadLeaveCS(); |
| 0 | 604 |
} |
605 |
else |
|
606 |
{// Remove the existing alias as it is not required.
|
|
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
607 |
DoRemoveAlias(iAliasLinAddr); // Releases mmulock. |
| 0 | 608 |
} |
609 |
aAliasAddr = aAddr; |
|
610 |
TInt maxSize = KChunkSize-(aAddr&KChunkMask); |
|
611 |
aAliasSize = aSize<maxSize ? aSize : maxSize; |
|
612 |
TRACE2(("DMemModelThread::Alias() abandoned as memory is globally mapped"));
|
|
613 |
return KErrNone; |
|
614 |
} |
|
615 |
||
616 |
TPde* pd = Mmu::PageDirectory(osAsid); |
|
617 |
TInt pdeIndex = aAddr>>KChunkShift; |
|
618 |
TPde pde = pd[pdeIndex]; |
|
619 |
#ifdef __SMP__ |
|
620 |
TLinAddr aliasAddr; |
|
621 |
#else |
|
622 |
TLinAddr aliasAddr = KIPCAlias+(aAddr&(KChunkMask & ~KPageMask)); |
|
623 |
#endif |
|
624 |
if(pde==iAliasPde && iAliasLinAddr) |
|
625 |
{
|
|
626 |
// pde already aliased, so just update linear address... |
|
627 |
#ifdef __SMP__ |
|
628 |
__NK_ASSERT_DEBUG(iCpuRestoreCookie>=0); |
|
629 |
aliasAddr = iAliasLinAddr & ~KChunkMask; |
|
630 |
aliasAddr |= (aAddr & (KChunkMask & ~KPageMask)); |
|
631 |
#endif |
|
632 |
iAliasLinAddr = aliasAddr; |
|
633 |
} |
|
634 |
else |
|
635 |
{
|
|
636 |
// alias PDE changed... |
|
637 |
if(!iAliasLinAddr) |
|
638 |
{
|
|
639 |
TheMmu.iAliasList.Add(&iAliasLink); // add to list if not already aliased |
|
640 |
#ifdef __SMP__ |
|
641 |
__NK_ASSERT_DEBUG(iCpuRestoreCookie==-1); |
|
642 |
iCpuRestoreCookie = NKern::FreezeCpu(); // temporarily lock current thread to this processor |
|
643 |
#endif |
|
644 |
} |
|
645 |
iAliasPde = pde; |
|
646 |
iAliasProcess = aProcess; |
|
647 |
#ifdef __SMP__ |
|
648 |
TSubScheduler& ss = SubScheduler(); // OK since we are locked to this CPU |
|
649 |
aliasAddr = TLinAddr(ss.i_AliasLinAddr) + (aAddr & (KChunkMask & ~KPageMask)); |
|
650 |
iAliasPdePtr = (TPde*)(TLinAddr(ss.i_AliasPdePtr) + (osAsid << KPageTableShift)); |
|
651 |
#endif |
|
652 |
iAliasLinAddr = aliasAddr; |
|
653 |
*iAliasPdePtr = pde; |
|
654 |
} |
|
655 |
TRACE2(("DMemModelThread::Alias() PDEntry=%x, iAliasLinAddr=%x",pde, aliasAddr));
|
|
656 |
LocalInvalidateTLBForPage(aliasAddr); |
|
657 |
TInt offset = aAddr&KPageMask; |
|
658 |
aAliasAddr = aliasAddr | offset; |
|
659 |
TInt maxSize = KPageSize - offset; |
|
660 |
aAliasSize = aSize<maxSize ? aSize : maxSize; |
|
661 |
iAliasTarget = aAddr & ~KPageMask; |
|
662 |
||
663 |
MmuLock::Unlock(); |
|
664 |
||
665 |
return KErrNone; |
|
666 |
} |
|
667 |
||
668 |
||
669 |
void DMemModelThread::RemoveAlias() |
|
670 |
// |
|
671 |
// Remove alias mapping (if present) |
|
672 |
// |
|
673 |
{
|
|
674 |
TRACE2(("Thread %O RemoveAlias", this));
|
|
675 |
__NK_ASSERT_DEBUG(this==TheCurrentThread); // many bad things can happen if false |
|
676 |
||
677 |
TLinAddr addr = iAliasLinAddr; |
|
678 |
if(addr) |
|
679 |
{
|
|
680 |
MmuLock::Lock(); |
|
681 |
||
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
682 |
DoRemoveAlias(addr); // Unlocks mmulock. |
| 0 | 683 |
} |
684 |
} |
|
685 |
||
686 |
||
687 |
/** |
|
688 |
Remove the alias mapping. |
|
689 |
||
690 |
@pre Mmulock held |
|
691 |
*/ |
|
692 |
void DMemModelThread::DoRemoveAlias(TLinAddr aAddr) |
|
693 |
{
|
|
694 |
iAliasLinAddr = 0; |
|
695 |
iAliasPde = KPdeUnallocatedEntry; |
|
696 |
*iAliasPdePtr = KPdeUnallocatedEntry; |
|
697 |
SinglePdeUpdated(iAliasPdePtr); |
|
698 |
__NK_ASSERT_DEBUG((aAddr&KPageMask)==0); |
|
699 |
LocalInvalidateTLBForPage(aAddr); |
|
700 |
iAliasLink.Deque(); |
|
701 |
#ifdef __SMP__ |
|
702 |
__NK_ASSERT_DEBUG(iCpuRestoreCookie>=0); |
|
703 |
NKern::EndFreezeCpu(iCpuRestoreCookie); |
|
704 |
iCpuRestoreCookie = -1; |
|
705 |
#endif |
|
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
706 |
|
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
707 |
// Must close the os asid while in critical section to prevent it being |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
708 |
// leaked. However, we can't hold the mmu lock so we have to enter an |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
709 |
// explict crtical section. It is ok to release the mmu lock as the |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
710 |
// iAliasLinAddr and iAliasProcess members are only ever updated by the |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
711 |
// current thread. |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
712 |
NKern::ThreadEnterCS(); |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
713 |
MmuLock::Unlock(); |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
714 |
iAliasProcess->AsyncCloseOsAsid(); // Asynchronous close as this method should be quick. |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
715 |
NKern::ThreadLeaveCS(); |
| 0 | 716 |
} |
717 |
||
718 |
||
719 |
TInt M::DemandPagingFault(TAny* aExceptionInfo) |
|
720 |
{
|
|
721 |
TX86ExcInfo& exc=*(TX86ExcInfo*)aExceptionInfo; |
|
722 |
if(exc.iExcId!=EX86VectorPageFault) |
|
723 |
return KErrAbort; // not a page fault |
|
724 |
||
725 |
/* |
|
726 |
Meanings of exc.iExcErrorCode when exception type is EX86VectorPageFault... |
|
727 |
||
728 |
Bit 0 0 The fault was caused by a non-present page. |
|
729 |
1 The fault was caused by a page-level protection violation. |
|
730 |
Bit 1 0 The access causing the fault was a read. |
|
731 |
1 The access causing the fault was a write. |
|
732 |
Bit 2 0 The access causing the fault originated when the processor was executing in supervisor mode. |
|
733 |
1 The access causing the fault originated when the processor was executing in user mode. |
|
734 |
Bit 3 0 The fault was not caused by reserved bit violation. |
|
735 |
1 The fault was caused by reserved bits set to 1 in a page directory. |
|
736 |
Bit 4 0 The fault was not caused by an instruction fetch. |
|
737 |
1 The fault was caused by an instruction fetch. |
|
738 |
*/ |
|
739 |
||
740 |
// check access type... |
|
741 |
TUint accessPermissions = EUser; // we only allow paging of user memory |
|
742 |
if(exc.iExcErrorCode&(1<<1)) |
|
743 |
accessPermissions |= EReadWrite; |
|
744 |
||
745 |
// let TheMmu handle the fault... |
|
746 |
return TheMmu.HandlePageFault(exc.iEip, exc.iFaultAddress, accessPermissions, aExceptionInfo); |
|
747 |
} |
|
748 |
||
749 |