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// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32\kernel\x86\cache.cpp
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//
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//
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#include <x86.h>
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#include <kernel/cache.h>
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#include "cache_maintenance.h"
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#ifdef __CPU_HAS_CACHE
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#define CACHEFAULT() CacheFault(__LINE__)
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void CacheFault(TInt aLine)
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{
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Kern::Fault("CacheFault",aLine);
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}
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EXPORT_C void Cache::IMB_Range(TLinAddr, TUint)
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{
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}
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EXPORT_C void Cache::SyncMemoryBeforeDmaWrite(TLinAddr, TUint)
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{
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}
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EXPORT_C void Cache::SyncMemoryBeforeDmaRead(TLinAddr, TUint)
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{
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}
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EXPORT_C void Cache::SyncMemoryAfterDmaRead(TLinAddr, TUint)
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{
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}
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EXPORT_C void Cache::AtomicSyncMemory()
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{
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}
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149
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EXPORT_C void Cache::CpuRetires()
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{
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}
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EXPORT_C void Cache::KernelRetires()
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{
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}
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0
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EXPORT_C void Cache::SyncMemoryBeforeDmaWrite(TLinAddr, TUint, TUint32)
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{
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}
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EXPORT_C void Cache::SyncMemoryBeforeDmaRead(TLinAddr, TUint, TUint32)
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{
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}
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EXPORT_C void Cache::SyncMemoryAfterDmaRead(TLinAddr, TUint, TUint32)
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{
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}
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EXPORT_C TInt Cache::GetThresholds(TCacheThresholds&, TUint)
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{
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return KErrNotSupported;
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}
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EXPORT_C TInt Cache::SetThresholds(const TCacheThresholds&, TUint)
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{
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return KErrNotSupported;
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}
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EXPORT_C TUint Cache::DmaBufferAlignment()
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{
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return 1;
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}
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void CacheMaintenance::Init1()
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{
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__KTRACE_OPT(KBOOT,Kern::Printf("CacheMaintenance::Init1"));
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}
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TBool CacheMaintenance::PageToReuse (TLinAddr, TMemoryType, TPhysAddr, TInt)
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{
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return EFalse;
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}
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void CacheMaintenance::PageToPreserveAndReuse ( TLinAddr, TMemoryType, TPhysAddr aPhysAddr)
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{
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}
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TMemoryType CacheMaintenance::TemporaryMapping()
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{
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return EMemAttNormalCached;
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}
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void CacheMaintenance::CodeChanged(TLinAddr, TUint, TCodeChangedBy)
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{
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}
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void CacheMaintenance::MakeCPUChangesVisible(TLinAddr, TUint, TUint32, TPhysAddr)
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{
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}
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void CacheMaintenance::PrepareMemoryForExternalWrites(TLinAddr, TUint, TUint32, TPhysAddr)
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{
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}
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void CacheMaintenance::MakeExternalChangesVisible(TLinAddr, TUint, TUint32, TPhysAddr)
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{
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}
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TBool CacheMaintenance::IsNormal(TMemoryType aType)
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{
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switch (aType)
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{
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case EMemAttStronglyOrdered:
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case EMemAttDevice:
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return EFalse;
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default:
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return ETrue;
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}
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}
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TBool CacheMaintenance::IsCached(TMemoryType aType)
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{
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switch (aType)
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{
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case EMemAttStronglyOrdered:
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case EMemAttDevice:
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case EMemAttNormalUncached:
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return EFalse;
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default:
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return ETrue;
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}
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}
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#if defined(__MEMMODEL_MULTIPLE__)
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void CacheMaintenance::MemoryToPreserveAndReuse(TLinAddr, TUint, TUint32)
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{
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}
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void CacheMaintenance::SyncPhysicalCache_All()
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{
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}
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#endif //defined(__MEMMODEL_MULTIPLE__)
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TUint32 InternalCache::TypeToCachingAttributes(TMemoryType)
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{
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return EMapAttrCachedMax;
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}
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#endif //__CPU_HAS_CACHE
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