154 STR r0, [r10, #SSuperPageBase_iDebugPort] ; set the debug port in the super page |
154 STR r0, [r10, #SSuperPageBase_iDebugPort] ; set the debug port in the super page |
155 DEBUG_INIT_STACKS ; r0..r2 modified (if) |
155 DEBUG_INIT_STACKS ; r0..r2 modified (if) |
156 |
156 |
157 PRTLN "InitialiseHardware use of optional SuperPage fields:" |
157 PRTLN "InitialiseHardware use of optional SuperPage fields:" |
158 IF :DEF: CFG_ENABLE_SMR_SUPPORT ; When defined the bootstrap PSL in InitialiseHardware() |
158 IF :DEF: CFG_ENABLE_SMR_SUPPORT ; When defined the bootstrap PSL in InitialiseHardware() |
159 LDR r0, [r10, #SSuperPageBase_iSmrData] ; must set this field to a valid adderss of the SMRIB or |
159 LDR r0, [r10, #SSuperPageBase_iSmrData] ; must set this field to a valid address of the SMRIB or |
160 ; KSuperPageAddressFieldUndefined if no SMRIB found. |
160 ; KSuperPageAddressFieldUndefined if no SMRIB found. |
161 DWORD r0, " SMR_SUPPORT Enabled - iSmrData" |
161 DWORD r0, " SMR_SUPPORT Enabled - iSmrData" |
162 ELSE |
162 ELSE |
163 MVN r0, #0 ; Set iSmrData field to KSuperPageAddressFieldUndefined (-1) |
163 MVN r0, #0 ; Set iSmrData field to KSuperPageAddressFieldUndefined (-1) |
164 STR r0, [r10, #SSuperPageBase_iSmrData] ; when SMR feature not supported in ROM image. This is |
164 STR r0, [r10, #SSuperPageBase_iSmrData] ; when SMR feature not supported in ROM image. This is |
418 ; On exit from this section pre-allocated entries may have been added: |
418 ; On exit from this section pre-allocated entries may have been added: |
419 ; <free ram region><><null entry><pre-allocated ram region><><null entry> |
419 ; <free ram region><><null entry><pre-allocated ram region><><null entry> |
420 ; |
420 ; |
421 ; - Setup R11 to point to free entry after first null entry in iRamBootData list |
421 ; - Setup R11 to point to free entry after first null entry in iRamBootData list |
422 ; - Reserve any SMRs in the SP SMRIB by adding them to the pre-allocation list |
422 ; - Reserve any SMRs in the SP SMRIB by adding them to the pre-allocation list |
423 ; - Call the bootstrap PSL to allow futher platform specific RAM reservation |
423 ; - Call the bootstrap PSL to allow further platform-specific RAM reservation |
424 ; |
424 ; |
425 |
425 |
426 ; Point R11 to preallocated block list |
426 ; Point R11 to preallocated block list |
427 LDR r11, [r10, #SSuperPageBase_iRamBootData] |
427 LDR r11, [r10, #SSuperPageBase_iRamBootData] |
428 3 |
428 3 |
703 IF :LNOT: CFG_MMDirect |
703 IF :LNOT: CFG_MMDirect |
704 MOV r0, #KPrimaryIOBase ; linear address for HW |
704 MOV r0, #KPrimaryIOBase ; linear address for HW |
705 ENDIF |
705 ENDIF |
706 |
706 |
707 IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache |
707 IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache |
708 MOV r7, #0 ; Flag to indicate if H/W bank that matches SSuperPageBase::iArmL2CacheBase is found. |
708 LDR r5, [r10, #SSuperPageBase_iArmL2CacheBase] ; r5 = PhysAddr of External Cache Controller. |
709 ; When found, we should stop searching. (Otherwise could be fatal if linear address of |
709 MOV r7, #1 ; R7 != 0 => LinAddr of ExtCacheCtrl is not found yet. Set R7 to 0 when found. |
710 ; External Cache Controller accidentally matches physical address of a H/W bank.) |
|
711 ENDIF |
710 ENDIF |
712 MapHwBank |
711 MapHwBank |
713 LDR r1, [r9], #4 ; get phys addr / size |
712 LDR r1, [r9], #4 ; get phys addr / size |
714 DWORD r1, "HwBank Entry" |
713 DWORD r1, "HwBank Entry" |
715 MVN r14, #0 |
714 MVN r14, #0 |
736 ELSE |
735 ELSE |
737 MVN r6, r14, LSL r4 ; r6 = 2^r4-1 |
736 MVN r6, r14, LSL r4 ; r6 = 2^r4-1 |
738 ADD r0, r0, r6 |
737 ADD r0, r0, r6 |
739 BIC r0, r0, r6 ; round up linear address |
738 BIC r0, r0, r6 ; round up linear address |
740 ENDIF |
739 ENDIF |
741 |
740 BL MapContiguous ; make mapping |
742 IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache |
741 IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache |
743 CMP r7, #0 |
742 MOV r4, r0 ; r4 = LinAddr of the current HwBank |
744 LDREQ r5, [r10, #SSuperPageBase_iArmL2CacheBase] ; get L2 cache controller base address from super page |
743 ENDIF |
745 CMPEQ r1,r5 ; if physical address matches ... |
|
746 STREQ r0, [r10, #SSuperPageBase_iArmL2CacheBase] ; ...set linear address in super page |
|
747 MOVEQ r7, #1 ; mark that L2CacheBase PhysToLinear transfer is completed |
|
748 ENDIF |
|
749 BL MapContiguous ; make mapping |
|
750 ADD r0, r0, r3 ; increment linear address |
744 ADD r0, r0, r3 ; increment linear address |
|
745 IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache |
|
746 B MapHwBank3 ; test whether the current HwBank contains ExtCacheCtrl |
|
747 ELSE |
751 B MapHwBank ; next bank |
748 B MapHwBank ; next bank |
|
749 ENDIF |
752 MapHwBank2 |
750 MapHwBank2 |
753 STR r0, [sp, #-4]! ; save default linear address |
751 STR r0, [sp, #-4]! ; save default linear address |
754 MOV r0, r6 ; r0 = specified linear address |
752 MOV r0, r6 ; r0 = specified linear address |
755 |
753 BL MapContiguous ; make mapping |
756 IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache |
754 IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache |
757 CMP r7, #0 |
755 MOV r4, r0 ; r4 = LinAddr of the current HwBank |
758 LDREQ r5, [r10, #SSuperPageBase_iArmL2CacheBase] ; get L2 cache controller base address from super page |
756 ENDIF |
759 CMPEQ r1,r5 ; if physical address matches ... |
|
760 STREQ r0, [r10, #SSuperPageBase_iArmL2CacheBase] ; ...set linear address in super page |
|
761 MOVEQ r7, #1 ; mark that L2CacheBase PhysToLinear transfer is completed |
|
762 ENDIF |
|
763 BL MapContiguous ; make mapping |
|
764 LDR r0, [sp], #4 ; restore default linear address |
757 LDR r0, [sp], #4 ; restore default linear address |
|
758 |
|
759 IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache |
|
760 MapHwBank3 |
|
761 ; Check if the current HW bank contains External Cache Controller. |
|
762 ; If so, write down its virtual address into SSuperPageBase::iArmL2CacheBase. |
|
763 ; r5 = phys. address of the external cache controller |
|
764 ; r1 = physical address of the current HW bank |
|
765 ; r4 = virtual address of the current HW bank |
|
766 ; r3 = the size of the current bank |
|
767 ; r7 = 0 if we have already found cache controller in of the previous HW banks |
|
768 CMP r7, #0 ; Still in search for linear address of external cache controller? |
|
769 BEQ MapHwBank ; If no, go to the next HwBank |
|
770 |
|
771 SUBS r7, r5, r1 ; r7 = PhysAddr of ExtCacheCtrl - PhysAddr of current HwBank |
|
772 ; i.e. offset of cache controller with respect to the current bank |
|
773 BLO MapHwBank ; ofsset(in r7) is <0 so not in this bank (and r7 != 0) |
|
774 |
|
775 CMP r7, r3 ; If 0 <= r7 < r3 then it's in this bank |
|
776 BHS MapHwBank ; Not in this bank (and r7 != 0) |
|
777 |
|
778 ; The current HwBank holds External Cache Controller |
|
779 ADD r5, r7, r4 ; r5 = LinAddr of ExtCacheCtrl |
|
780 STR r5, [r10, #SSuperPageBase_iArmL2CacheBase] ; Set Linear Address of ExtCacheCtrl in super page |
|
781 |
|
782 MOV r7, #0 ; Mark that Linear Address of ExtCacheCtrl is found |
|
783 ENDIF ; IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache |
|
784 |
765 B MapHwBank ; next bank |
785 B MapHwBank ; next bank |
766 |
786 |
767 MapHwBank_End |
787 MapHwBank_End |
768 |
788 |
769 ; dummy uncached mapping |
789 ; dummy uncached mapping |