; Copyright (c) 2003-2009 Nokia Corporation and/or its subsidiary(-ies).

; All rights reserved.

; This component and the accompanying materials are made available

; under the terms of the License "Eclipse Public License v1.0"

; which accompanies this distribution, and is available

; at the URL "http://www.eclipse.org/legal/epl-v10.html".

;

; Initial Contributors:

; Nokia Corporation - initial contribution.

;

; Contributors:

;

; Description:

; e32\kernel\arm\bootmain.s

; Bootstrap main program

;

		GBLL	__BOOTMAIN_S__

		INCLUDE	bootcpu.inc

;

;*******************************************************************************

;

        AREA |Boot$$Code|, CODE, READONLY, ALIGN=6

;

;*******************************************************************************

;

	EXPORT	TheRomHeader

TheRomHeader							; this label represents the base of the ROM header

	IF	CFG_CustomVectors

		INCLUDE	custom_vectors.inc

	ELSE

; Reset vector

		B	ResetEntry

	IF	CFG_MMDirect :LAND: (:LNOT: CFG_MMUPresent :LOR: CFG_UseBootstrapVectors)

		B	. + KernelCodeOffset		; undef

		B	. + KernelCodeOffset		; swi

		B	. + KernelCodeOffset		; prefetch

		B	. + KernelCodeOffset		; data

		B	. + KernelCodeOffset		;

		B	. + KernelCodeOffset		; irq

		B	. + KernelCodeOffset		; fiq

	ELSE

		IF	CFG_DebugBootRom

	IMPORT	HandleUndef

	IMPORT	HandleSwi

	IMPORT	HandleAbtPrefetch

	IMPORT	HandleAbtData

	IMPORT	HandleRsvdVector

	IMPORT	HandleIrq

	IMPORT	HandleFiq

		B	HandleUndef

		B	HandleSwi

		B	HandleAbtPrefetch

		B	HandleAbtData

		B	HandleRsvdVector

		B	HandleIrq

		B	HandleFiq

		ELSE

		FAULT

		FAULT

		FAULT

		FAULT

		FAULT

		FAULT

		FAULT

		ENDIF

	ENDIF

	ENDIF

RestartPadBegin

		%	124 - (RestartPadBegin - TheRomHeader)

; Restart vector - called to reboot under software control

	IMPORT	RestartEntry

		B	RestartEntry

; Leave additional space for the rest of the ROM header

		%	TRomHeader_sz - 128

;***************************************************************************************

; MAIN ENTRY POINT

;	Called on hardware reset

;***************************************************************************************

	EXPORT	ResetEntry

ResetEntry

		GETCPSR r3						; cpsr (r3) & r2 MUST be preserved for

										; entry into InitialiseHardware() to 

										; allow pre-OS loaders to pass info to 

										; bootstrap PSL

	IF :DEF: CFG_BootedInSecureState

	IMPORT	SwitchToNonSecureState

		BL		SwitchToNonSecureState	; corrupts r0,r1

	ENDIF

		MOV		r0, r3

		BIC		r0, r0, #0x1f

		ORR		r0, r0, #0xd3			; 32-bit SVC mode, no interrupts

	IF	CFG_ARMV6 :LOR: CFG_ARMV7

		ORR		r0, r0, #0x100			; on V6 disable imprecise aborts

	ENDIF

		SETCPSR	r0

		ADR		r12, TheRomHeader

;

; The following call should, at a minimum

;	1.	Determine the hardware configuration

;	2.	Determine the reset reason. If it is wakeup from a low power mode, perform

;		whatever reentry sequence is required and jump back to the kernel.

;	3.	Set up the memory controller so that at least some RAM is available

;	4.	Set R10 to point to the super page or to a temporary version of the super page

;		with at least the following fields valid:

;			iBootTable, iCodeBase, iActiveVariant, iCpuId

;		and optionally:

;			iSmrData

;	5.	In debug builds initialise the debug serial port

;

; Enter with:

;		R2	= value as at entry to ResetEntry, preserved unmodified

;		R3	= value of cpsr on entry to ResetEntry

;		R12 = points to TRomHeader

;		NO STACK

;		R14 = return address (as usual)

;

; Leave with :

;		R10 = physical address of super page

;

;	All registers may be modified by this call

;

	IMPORT	InitialiseHardware

		BL		InitialiseHardware						; r0..r14 modified

		ADR		r12, TheRomHeader

		ADD		sp, r10, #CpuBootStackTop				; set up a boot stack

		LDR		r0, [r12, #TRomHeader_iDebugPort]

		STR		r0, [r10, #SSuperPageBase_iDebugPort]	; set the debug port in the super page

		DEBUG_INIT_STACKS								; r0..r2 modified (if)

		PRTLN	"InitialiseHardware use of optional SuperPage fields:"

	IF	:DEF: CFG_ENABLE_SMR_SUPPORT					; When defined the bootstrap PSL in InitialiseHardware()

														; KSuperPageAddressFieldUndefined if no SMRIB found.

		DWORD	r0, "  SMR_SUPPORT Enabled - iSmrData"	

	ELSE

		MVN		r0, #0									; Set iSmrData field to KSuperPageAddressFieldUndefined (-1)

		STR		r0, [r10, #SSuperPageBase_iSmrData] 	; when SMR feature not supported in ROM image. This is    

		DWORD	r0, "  SMR_SUPPORT Disabled - iSmrData" ; done to ensure kernel-side code can tell if SMRIB exists.	       

	ENDIF

	IF	CFG_BootLoader :LOR: :DEF: CFG_CopyRomToAddress

; Copy the code to RAM

		PRTLN	"Copy code to RAM"

		LDR		r0, [r10, #SSuperPageBase_iCodeBase]	; source

	; Two methods of obtaining the destination physical address: either the

	; config.inc can define CFG_CopyRomToAddress as a numeric constant or it

	; will use the romlinearbase for bootloaders.

	IF	:DEF: CFG_CopyRomToAddress

		LDR		r1, =CFG_CopyRomToAddress				; destination defined in config.inc (must be physical address)

	ELSE

		LDR		r1, [r12, #TRomHeader_iRomBase]			; destination defined in header.iby (must be physical address)

	ENDIF

	IF	:DEF: CFG_SupportEmulatedRomPaging

		LDR		r2, [r12, #TRomHeader_iUncompressedSize]; size of rom

	ELSE

		LDR		r2, [r12, #TRomHeader_iPageableRomStart]; size of unpaged part of ROM

		CMP		r2, #0

		LDREQ	r2, [r12, #TRomHeader_iUncompressedSize]; size if not a pageable rom

	ENDIF

		ADD		r2, r2, #0x3

		BIC		r2, r2, #0x3							; make 4byte aligned

		SUB		r4, r1, r0								; save offset destination - source

		DWORD	r0, "Source"

		DWORD	r1, "Dest"

		DWORD	r2, "Size"

		DWORD	r4, "Offset"

		ADR		lr, ReturnHereAfterCopy

		ADD		lr, lr, r4								; lr = return address in RAM

		B		WordMove								; copy the code, return to RAM copy

		LTORG		; Required when CFG_DebugBootRom is enabled

		; WordMove returns to here in RAM

ReturnHereAfterCopy

		LDR		r0, [r10, #SSuperPageBase_iCodeBase]	;

		ADD		r0, r0, r4								;

		STR		r0, [r10, #SSuperPageBase_iCodeBase]	; fix up iCodeBase

		LDR		r1, [r10, #SSuperPageBase_iBootTable]	;

		ADD		r1, r1, r4								;

		STR		r1, [r10, #SSuperPageBase_iBootTable]	; fix up iBootTable

		ADD		r12, r12, r4							; fix up R12 (points to TRomHeader)

		DWORD	r0, "New iCodeBase"

		DWORD	r1, "New iBootTable"

		DWORD	r12, "R12"

		DWORD	pc, "PC"

	ENDIF

		LDR		r0, [r12, #TRomHeader_iRomRootDirectoryList]

		STR		r0, [r10, #SSuperPageBase_iRootDirList]

		LDR		r7, [r10, #SSuperPageBase_iBootFlags]	; get boot flags

		BIC		r7, r7, #0xff000000

		STR		r7, [r10, #SSuperPageBase_iBootFlags]	; clear top 8 bits

		STR		r12, [r10, #SSuperPageBase_iRomHeaderPhys]

; Live registers here are R10, R12, R13

; Determine the machine RAM configuration

		PRTLN	"Determine RAM config"

		ADD		r11, r10, #CpuRamTableOffset

		STR		r11, [r10, #SSuperPageBase_iRamBootData]

		ADD		r0, r10, #CpuRomTableOffset

		STR		r0, [r10, #SSuperPageBase_iRomBootData]

		MOV		r1, #CpuRamTableTop-CpuRomTableOffset

		MOV		r2, #0

		BL		WordFill					; zero-fill RAM boot data

		BOOTCALL	BTF_RamBanks			; r0 points to list of possible RAM banks

											; in increasing physical address order

		MOV		r9, r0						; into r9

TestRamBank1

		LDR		r1, [r9], #4				; r1 = physical address of bank

		LDR		r8, [r9], #4				; r8 = size of bank

		DWORD	r1, "TRB Base"

		DWORD	r8, "TRB Size"

		CMP		r8, #0						; reached end?

		BEQ		TestRamBank_End				; branch if end

		TST		r1, #RAM_VERBATIM			; if flag set, accept bank verbatim

		BIC		r2, r1, #RAM_VERBATIM		; clear flag

		MOVNE	r0, r11

		STRNE	r2, [r0], #4				; store base

		STRNE	r8, [r0], #4				; store size

		BNE		TestRamBank3				; do PC check and then next bank

		MVN		r3, #0

		BOOTCALL	BTF_SetupRamBank		; set width to 32

		BL		FindRamBankWidth			; test for presence of RAM

		DWORD	r3, "TRB ByteLane"

		CMP		r3, #0						;

		BEQ		TestRamBank1				; if no RAM, try next

		BOOTCALL	BTF_SetupRamBank		; set width

TestRamBank3

		MOV		r0, pc						; check if PC is in RAM

		SUBS	r0, r0, r1					; PC - base

		CMPHS	r8, r0						; if PC>=base, check size>(PC-base)

		LDRHI	r7, [r10, #SSuperPageBase_iBootFlags]		; 

		ORRHI	r7, r7, #KBootFlagRunFromRAM				; if so, we are running from RAM

		STRHI	r7, [r10, #SSuperPageBase_iBootFlags]		; so set boot flag

		TST		r1, #RAM_VERBATIM			; if flag set, accept bank verbatim

		ADDNE	r0, r11, #8

		BNE		TestRamBank4

		MOV		r2, r8						; r2 = max bank size

		MOV		r0, r11						; r0 = allocator data ptr

		BL		FindRamBankConfig			; find blocks

TestRamBank4

	IF	CFG_DebugBootRom

TestRamBank2

		LDR		r1, [r11], #4

		DWORD	r1, "Block base"

		LDR		r1, [r11], #4

		DWORD	r1, "Block size"

		CMP		r11, r0

		BLO		TestRamBank2

	ENDIF

		MOV		r11, r0						; save allocator data ptr

		B		TestRamBank1				; next bank

TestRamBank_End

; Determine the machine ROM configuration

		LDR		r11, [r10, #SSuperPageBase_iRomBootData]

		LDR		r0, [r10, #SSuperPageBase_iBootFlags]

		TST		r0, #KBootFlagRunFromRAM

		BEQ		TestRomBanks				; branch if running from ROM

; ROM is actually in RAM

		PRTLN	"Running from RAM"

	IF	:DEF: CFG_SupportEmulatedRomPaging

		LDR		r8, [r12, #TRomHeader_iUncompressedSize]; r8=size of ROM

	ELSE

		LDR		r8, [r12, #TRomHeader_iPageableRomStart]; r8=size of unpaged part of ROM

		CMP		r8, #0

		LDREQ	r8, [r12, #TRomHeader_iUncompressedSize]; r8=size of ROM if not a pageable rom

	ENDIF

		MVN		r2, #0									; round this up to 64k

		ADD		r8, r8, r2, lsr #(32 - CFG_RomSizeAlign)

		BIC		r8, r8, r2, lsr #(32 - CFG_RomSizeAlign)

		LDR		r9, [r10, #SSuperPageBase_iRamBootData]

		LDR		r0, [r10, #SSuperPageBase_iCodeBase]	; running from RAM - ROM base = code base

		LDR		r2, [r12, #TRomHeader_iRomBase]			; r2=linear base of ROM block

		MOV		r1, r8									; size of area to excise

		BL		ExciseRamArea							; remove RAM which holds image from free list

		LDR		r0, [r9, #SRamBank_iSize]

		CMP		r0, #0

		BEQ		RomInRam1								; reached end of RAM list - no extension ROM

		LDR		r0, [r9, #SRamBank_iBase]				; r0 = next RAM address after kernel ROM image

		BL		CheckForExtensionRom					; check for extension ROM

		BEQ		RomInRam1								; skip if not present

		LDR		r1, [r0, #TExtensionRomHeader_iUncompressedSize] ; else r1=extension ROM size

		MVN		r2, #0									; round this up to 64k

		ADD		r1, r1, r2, lsr #(32 - CFG_RomSizeAlign)

		BIC		r1, r1, r2, lsr #(32 - CFG_RomSizeAlign)

		ADD		r8, r8, r1								; accumulate ROM size

		LDR		r2, [r0, #TExtensionRomHeader_iRomRootDirectoryList]

		STR		r2, [r10, #SSuperPageBase_iRootDirList]		; and update root dir ptr

		LDR		r2, [r0, #TExtensionRomHeader_iRomBase]		; r2=linear base of extension ROM block

		BL		ExciseRamArea							; remove RAM which holds extension ROM image from free list

RomInRam1

		B		DoneRomBanks				; finished with ROM

; ROM is actually in ROM or FLASH

TestRomBanks

		PRTLN	"Running from ROM/FLASH"

		BOOTCALL	BTF_RomBanks			; r0 points to list of possible ROM banks

											; in increasing physical address order

		MOV		r9, r0						; R9 -> bank list

		MOV		r11, #0

		BOOTCALL	BTF_SetupRomBank		; do any setup prior to detection

		LDR		r11, [r10, #SSuperPageBase_iRomBootData]

; Walk through list of possible banks

; Call a setup function for each one

; This should set up width/wait states if not set by earlier initialisation.

; It may also do detection of optional banks if required.

TestRomBank1

		LDMIA	r9!, {r1-r4}

		STMIA	r11, {r1-r4}

		DWORD	r1, "TROMB Base"

		DWORD	r2, "TROMB Size"

		DWORD	r4, "TROMB LinB"

		CMP		r2, #0						; end of list?

		BEQ		CalcRomLinBases				; branch if so

		BOOTCALL	BTF_SetupRomBank		; do detection if needed (for optional ROMs)

		LDMIA	r11, {r1-r4}

	IF	CFG_DebugBootRom

		DWORD	r1, "TROMB PostDet Base"

		DWORD	r2, "TROMB PostDet Size"

		DWORD	r4, "TROMB PostDet LinB"

	ENDIF

		CMP		r2, #0

		ADDNE	r11, r11, #SRomBank_sz		; if bank present, increment r11

		B		TestRomBank1

CalcRomLinBases

		LDR		r11, [r10, #SSuperPageBase_iRomBootData]

		MOV		r8, #0						; total ROM size

CalcRomLinBases1

		LDMIA	r11!, {r0,r2-r4}			; r0=phys base, r2=size, r4=lin base

		DWORD	r0, "CRLB Base"

		DWORD	r2, "CRLB Size"

		DWORD	r4, "CRLB LinB"

		CMP		r2, #0						; reached end?

		BEQ		CalcRomLinBases_End

		ADD		r8, r8, r2					; accumulate size

	IF	CFG_MMUPresent

		CMP		r4, #0						; lin addr override?

		MOVNE	r9, r4						; if so, take it

	ELSE

		MOV		r9, r0						; if no MMU, lin = phys

	ENDIF

		SUBS	r1, r12, r0					; check if this is boot block - R1=rom header phys-base

		CMPHS	r2, r1						; if rom hdr phys>=base, compare size with rom header phys-base

	IF	CFG_MMUPresent

		LDRHI	r9, [r12, #TRomHeader_iRomBase]	; linear base of boot ROM (= lin addr of rom header)

		SUBHI	r9, r9, r1					; calculate linear address corresponding to base of ROM block

	ENDIF

		BHI		CalcRomLinBases2			; skip if boot block

		BL		CheckForExtensionRom		; else check if this is extension ROM

		BEQ		CalcRomLinBases2			; skip if not

	IF	CFG_MMUPresent

		LDR		r9, [r0, #TExtensionRomHeader_iRomBase]	; if it is, take linear address override

	ENDIF

		LDR		r1, [r0, #TExtensionRomHeader_iRomRootDirectoryList]

		STR		r1, [r10, #SSuperPageBase_iRootDirList]		; and update root dir ptr

CalcRomLinBases2

		DWORD	r9, "CRLB Final Linear Base"

		STR		r9, [r11, #-4]				; write final linear base

	IF	CFG_MMUPresent

		ADD		r9, r9, r2					; and step on by size

	ENDIF

		B		CalcRomLinBases1			; do next bank

CalcRomLinBases_End

DoneRomBanks

		STR		r8, [r10, #SSuperPageBase_iTotalRomSize]	; save total ROM size

; Support for areas?

; Put it here if needed.

; RAM reservation/pre-allocation section

;

; SSuperPageBase_iRamBootData member points to two arrays/lists that are

; used to initialise the kernel RAM Allocator. On entry to this section the

; list contains the free RAM regions and no pre-allocations:

;	<free ram region><...><null entry><null entry>

;

; On exit from this section pre-allocated entries may have been added:

; 	<free ram region><><null entry><pre-allocated ram region><><null entry>

;

; - Setup R11 to point to free entry after first null entry in iRamBootData list

; - Reserve any SMRs in the SP SMRIB by adding them to the pre-allocation list

;

; Point R11 to preallocated block list

		LDR		r11, [r10, #SSuperPageBase_iRamBootData]

3

		LDMIA	r11!, {r0,r1}

		CMP		r1, #0

		BNE		%BT3

; At this point in bootstrap:

; r10 = pointer to super page (SP)

; r11 = address of first pre-alloc SRamBank after first terminator entry

; r12 = pointer to ROM header

; r13 = stack pointer

; Reserve SMR memory blocks, if SMRIB valid in super page

		MOV		r6, #0						; Setup r6 to count SMRIB entries for trace

		LDR		r5, [r10, #SSuperPageBase_iSmrData]

		CMN	 	r5, #1						; Compare to KSuperPageAddressFieldUndefined	

		BCS	 	NoSMRIB						; jump over if no SMRIB

		PRTLN	"Processing (any) SMRIB..."

4

		LDMIA	r5, {r0, r1}				; load iBase and iSize members		

		ADD	 	r5, r5, #SSmrBank_sz		; Skip the two other members, inc R5 to next entry

		CMP	 	r1, #0

		BEQ	 	DoneSMRReservation			; Jump out of loop if no more SMRs

		MVN		r3, #0

		ANDS	r2, r1, r3, LSR #20

		FAULT	NE							; Fault if SMR Size is not multiple of 4Kb

		STMIA	r11!, {r0, r1}				; Add SMR to pre-alloc list

		ADD		r6, r6, #1

		B		%BT4

											; No need to add null entry as the 

DoneSMRReservation							; SRamBank area has been zero filled   

		CMP		r6, #0

		BNE		%FT5

		PRTLN	"PSL created SMRIB of zero size!"

		B		NoSMRIB		

5

		DWORD	r6, "PSL created SMRIB of X entries"

	IF	CFG_DebugBootRom

		PRTLN	"SMRIB Memory Dump:"

		LDR		r5, [r10, #SSuperPageBase_iSmrData]

		MOV		r6, r6, LSL #4 

		MEMDUMP	r5, r6

	ENDIF

NoSMRIB

; Here r11 points to the null terminator of the preallocated block list

; Reserve any platform-dependent extra physical memory here.

; Two methods are available:

;	1.	ExciseRamArea - the kernel will then not treat the region as RAM

;	2.	Add preallocation regions to the RAM bank list. R11 has been set

;		to point to the first of these. List is terminated by a zero size.

;		The kernel will treat these regions as RAM.

;

		BOOTCALL	BTF_Reserve

	IF	CFG_DebugBootRom

; In debug, dump ROM and RAM bank config

		PRTLN	"ROM and RAM config:"

		LDR		r11, [r10, #SSuperPageBase_iRomBootData]

		MOV		r1, #CpuRamTableTop-CpuRomTableOffset

		MEMDUMP	r11, r1

	ENDIF

; Calculate total RAM size

		LDR		r11, [r10, #SSuperPageBase_iRamBootData]

		MOV		r9, #0

AccumulateRamSize

		LDMIA	r11!, {r0,r1}

		ADD		r9, r9, r1

		CMP		r1, #0

		BNE		AccumulateRamSize

		DWORD	r9, "TotalRamSize"

		STR		r9, [r10, #SSuperPageBase_iTotalRamSize]

; RAM reservation/pre-allocation section end

;

; find the kernel image and point R11 to it

		PRTLN	"Find primary"

		BL		FindPrimary

		STR		r11, [sp, #-4]!

	IF	CFG_MMDirect

		; direct model - work out the end of the kernel memory area

		LDR		r8, [r12, #TRomHeader_iKernelLimit]	; end of kernel heap, rounded up to 4K

	IF	CFG_MMUPresent

		GETPARAM	BPR_PageTableSpace, DefaultPTAlloc	; get reserved space for page tables

		ADD		r8, r8, r0						; add space for page tables

	IF	:LNOT: :DEF: CFG_MinimiseKernelHeap

		MVN		r1, #0

		ADD		r8, r8, r1, LSR #12

		BIC		r8, r8, r1, LSR #12				; round up to 1Mb to give limit

	ENDIF

	ENDIF

		STR		r8, [r10, #SSuperPageBase_iKernelLimit]

		DWORD	r8, "Kernel Limit"