64 SFullArmRegSet* iRegs; |
64 SFullArmRegSet* iRegs; |
65 }; |
65 }; |
66 TLinAddr iUndStackTop; // Top of UND stack for this CPU |
66 TLinAddr iUndStackTop; // Top of UND stack for this CPU |
67 TLinAddr iFiqStackTop; // Top of FIQ stack for this CPU |
67 TLinAddr iFiqStackTop; // Top of FIQ stack for this CPU |
68 TLinAddr iIrqStackTop; // Top of IRQ stack for this CPU |
68 TLinAddr iIrqStackTop; // Top of IRQ stack for this CPU |
69 volatile TUint32 iCpuFreqM; // CPU frequency / Max CPU frequency (mantissa, bit 31=1) f/fmax=mantissa/2^shift |
69 SRatioInv* volatile iNewCpuFreqRI; // set when CPU frequency has been changed |
70 volatile TInt iCpuFreqS; // CPU frequency / Max CPU frequency (shift) |
70 SRatioInv* volatile iNewTimerFreqRI; // set when CPU local timer frequency has been changed |
71 volatile TUint32 iCpuPeriodM; // Max CPU frequency / CPU frequency (mantissa, bit 31=1) fmax/f=mantissa/2^shift |
71 SRatioInv iCpuFreqRI; // Ratio of CPU frequency to maximum possible CPU frequency |
72 volatile TInt iCpuPeriodS; // Max CPU frequency / CPU frequency (shift) |
72 SRatioInv iTimerFreqRI; // Ratio of CPU local timer frequency to maximum possible |
73 volatile TUint32 iNTimerFreqM; // Nominal Timer frequency / Max Timer frequency (mantissa, bit 31=1) f/fmax=mantissa/2^shift |
73 |
74 volatile TInt iNTimerFreqS; // Nominal Timer frequency / Max Timer frequency (shift) |
74 TUint32 iSSXP2[36]; |
75 volatile TUint32 iNTimerPeriodM; // Nominal Max Timer frequency / Timer frequency (mantissa, bit 31=1) fmax/f=mantissa/2^shift |
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76 volatile TInt iNTimerPeriodS; // Nominal Max Timer frequency / Timer frequency (shift) |
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77 volatile TUint32 iTimerFreqM; // Timer frequency / Max Timer frequency (mantissa, bit 31=1) f/fmax=mantissa/2^shift |
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78 volatile TInt iTimerFreqS; // Timer frequency / Max Timer frequency (shift) |
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79 volatile TUint32 iTimerPeriodM; // Max Timer frequency / Timer frequency (mantissa, bit 31=1) fmax/f=mantissa/2^shift |
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80 volatile TInt iTimerPeriodS; // Max Timer frequency / Timer frequency (shift) |
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81 volatile TUint64 iLastSyncTime; // Timestamp at which last reference check occurred |
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82 volatile TUint32 iTicksSinceLastSync; // Local timer ticks between last ref. check and next zero crossing |
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83 volatile TUint32 iLastTimerSet; // Value last written to local timer counter |
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84 volatile TUint32 iGapEstimate; // 2^16 * estimated gap in ticks whenever local timer counter is read then written |
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85 volatile TUint32 iGapCount; // count of local timer counter RMW ops |
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86 volatile TUint32 iTotalTicks; // programmed ticks since last sync |
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87 volatile TUint32 iDitherer; // PRNG state for dither generation |
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88 volatile TInt iFreqErrorEstimate; // Current frequency offset between local timer and reference |
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89 volatile TInt iFreqErrorLimit; // Saturation level for frequency offset |
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90 volatile TInt64 iErrorIntegrator; // Accumulator to integrate time error measurements |
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91 volatile TUint64 iRefAtLastCorrection; // Value of reference timer at last correction |
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92 volatile TUint8 iM; // Value controlling loop bandwidth (larger->lower loop bandwidth) |
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93 volatile TUint8 iN; // Number of timer ticks between corrections = 2^iN |
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94 volatile TUint8 iD; // Value controlling loop damping |
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95 volatile TUint8 iSSXP1; |
|
96 |
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97 TUint32 iSSXP2[19]; |
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98 TUint64 iSSXP3; // one 64 bit value to guarantee alignment |
75 TUint64 iSSXP3; // one 64 bit value to guarantee alignment |
99 }; |
76 }; |
100 |
77 |
101 // TScheduler member data |
78 // TScheduler member data |
102 struct TSchedulerX |
79 struct TSchedulerX |
106 ArmGlobalTimer* iGlobalTimerAddr; // Address of global timer registers (also in TSubScheduler) |
83 ArmGlobalTimer* iGlobalTimerAddr; // Address of global timer registers (also in TSubScheduler) |
107 ArmScu* iScuAddr; // Address of SCU (also in TSubScheduler) |
84 ArmScu* iScuAddr; // Address of SCU (also in TSubScheduler) |
108 GicDistributor* iGicDistAddr; // Address of GIC Distributor (also in TSubScheduler) |
85 GicDistributor* iGicDistAddr; // Address of GIC Distributor (also in TSubScheduler) |
109 GicCpuIfc* iGicCpuIfcAddr; // Address of GIC CPU Interface (also in TSubScheduler) |
86 GicCpuIfc* iGicCpuIfcAddr; // Address of GIC CPU Interface (also in TSubScheduler) |
110 ArmLocalTimer* iLocalTimerAddr; // Address of local timer registers (also in TSubScheduler) |
87 ArmLocalTimer* iLocalTimerAddr; // Address of local timer registers (also in TSubScheduler) |
111 TUint32 iSXP2[8]; |
88 |
|
89 SRatioInv iGTimerFreqRI; // ratio of global timer frequency to maximum possible |
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90 TUint64 iCount0; // global timer count at last frequency change |
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91 TUint64 iTimestamp0; // timestamp at last frequency change |
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92 |
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93 TUint32 iSXP2[16]; |
112 }; |
94 }; |
113 |
95 |
114 |
96 |
115 #define RESCHED_IPI_VECTOR 0x00 |
97 #define RESCHED_IPI_VECTOR 0x00 |
116 #define GENERIC_IPI_VECTOR 0x01 |
98 #define GENERIC_IPI_VECTOR 0x01 |