78 E_ArmTmrWDD_1 =0x12345678u, // to disable watchdog, write this ... |
78 E_ArmTmrWDD_1 =0x12345678u, // to disable watchdog, write this ... |
79 E_ArmTmrWDD_2 =0x87654321u, // ... then this with no intervening writes |
79 E_ArmTmrWDD_2 =0x87654321u, // ... then this with no intervening writes |
80 }; |
80 }; |
81 |
81 |
82 |
82 |
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83 #ifdef __CPU_ARM_HAS_GLOBAL_TIMER_BLOCK |
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84 |
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85 // r1p0 and later A9s have an additional Global Timer |
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86 struct ArmGlobalTimer |
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87 { |
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88 volatile TUint32 iTimerCountLow; // 00 Timer counter low word |
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89 volatile TUint32 iTimerCountHigh; // 04 Timer counter high word |
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90 volatile TUint32 iTimerCtrl; // 08 Timer control register |
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91 volatile TUint32 iTimerStatus; // 0C Timer status register |
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92 volatile TUint32 iComparatorLow; // 10 Comparator value low word (per-CPU register) |
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93 volatile TUint32 iComparatorHigh; // 14 Comparator value high word (per-CPU register) |
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94 volatile TUint32 iComparatorInc; // 18 Comparator autoincrement value (per-CPU register) |
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95 volatile TUint32 i_Spare2[57]; // 1C unused |
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96 }; |
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97 |
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98 __ASSERT_COMPILE(sizeof(ArmGlobalTimer)==0x100); |
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99 |
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100 // Global Timer Control Register Bits |
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101 enum TArmGlobalTimerCtrl |
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102 { |
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103 E_ArmGTmrCtrl_TmrEnb =1u, // when set, timer counts up |
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104 E_ArmGTmrCtrl_CmpEnb =2u, // when set, comparator matching is enabled (per-CPU) |
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105 E_ArmGTmrCtrl_IntEn =4u, // when set enables comparator match interrupt (per-CPU) |
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106 E_ArmGTmrCtrl_AutoInc =8u, // when set enables comparator auto increment (per-CPU) |
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107 E_ArmGTmrCtrl_PrescaleShift =8u, |
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108 E_ArmGTmrCtrl_PrescaleMask =0xff00u, // bits 8-15 = prescale value - divides by (P+1) |
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109 // input to prescaler is PERIPHCLK (=CPUCLK/2 on NE1, CPUCLK/N in general, N>=2) |
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110 }; |
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111 |
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112 enum TArmGlobalTimerStatus |
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113 { |
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114 E_ArmGTmrStatus_Event =1u // set when timer count value matches comparator value (per-CPU) |
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115 }; |
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116 |
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117 #endif |
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118 |
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119 |
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120 |
83 |
121 |
84 #endif // __ARM_TMR_H__ |
122 #endif // __ARM_TMR_H__ |