|
1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
|
2 // All rights reserved. |
|
3 // This component and the accompanying materials are made available |
|
4 // under the terms of the License "Eclipse Public License v1.0" |
|
5 // which accompanies this distribution, and is available |
|
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
|
7 // |
|
8 // Initial Contributors: |
|
9 // Nokia Corporation - initial contribution. |
|
10 // |
|
11 // Contributors: |
|
12 // |
|
13 // Description: |
|
14 // e32\include\nkernsmp\arm\arm_tmr.h |
|
15 // |
|
16 // WARNING: This file contains some APIs which are internal and are subject |
|
17 // to change without notice. Such APIs should therefore not be used |
|
18 // outside the Kernel and Hardware Services package. |
|
19 // |
|
20 |
|
21 #ifndef __ARM_TMR_H__ |
|
22 #define __ARM_TMR_H__ |
|
23 #include <e32def.h> |
|
24 |
|
25 #ifdef __STANDALONE_NANOKERNEL__ |
|
26 #undef __IN_KERNEL__ |
|
27 #define __IN_KERNEL__ |
|
28 #endif |
|
29 |
|
30 #if !defined(__CPU_ARM11MP__) && !defined(__CPU_CORTEX_A9__) |
|
31 #error Unknown local timer |
|
32 #endif |
|
33 |
|
34 // Local timer looks the same on ARM11MP and Cortex A9 |
|
35 struct ArmLocalTimer |
|
36 { |
|
37 volatile TUint32 iTimerLoad; // 00 Timer reload value (write also writes counter) |
|
38 volatile TUint32 iTimerCount; // 04 Timer instantaneous count value |
|
39 volatile TUint32 iTimerCtrl; // 08 Timer control register |
|
40 volatile TUint32 iTimerIntStatus; // 0C Timer interrupt status register |
|
41 volatile TUint32 i_Spare1[4]; // 10 unused |
|
42 volatile TUint32 iWatchdogLoad; // 20 Watchdog reload value (write also writes counter) |
|
43 volatile TUint32 iWatchdogCount; // 24 Watchdog instantaneous count value |
|
44 volatile TUint32 iWatchdogCtrl; // 28 Watchdog control register |
|
45 volatile TUint32 iWatchdogIntStatus; // 2C Watchdog interrupt status register |
|
46 volatile TUint32 iWatchdogResetSent; // 30 Watchdog reset sent register |
|
47 volatile TUint32 iWatchdogDisable; // 34 Watchdog disable register |
|
48 volatile TUint32 i_Spare2[50]; // 38 unused |
|
49 }; |
|
50 |
|
51 __ASSERT_COMPILE(sizeof(ArmLocalTimer)==0x100); |
|
52 |
|
53 // These bits apply to both timer and watchdog control registers |
|
54 enum TArmTimerCtrl |
|
55 { |
|
56 E_ArmTmrCtrl_Enable =1u, // when set, timer counts down |
|
57 E_ArmTmrCtrl_Reload =2u, // when set, timer reloads on reaching zero |
|
58 E_ArmTmrCtrl_IntEn =4u, // when set enables timer interrupt |
|
59 E_ArmTmrCtrl_WD =8u, // set when in watchdog mode (watchdog only, can write to 1 but not 0) |
|
60 E_ArmTmrCtrl_PrescaleShift =8u, |
|
61 E_ArmTmrCtrl_PrescaleMask =0xff00u, // bits 8-15 = prescale value - divides by (P+1) |
|
62 // input to prescaler is PERIPHCLK (=CPUCLK/2 on NE1, CPUCLK/N in general, N>=2) |
|
63 E_ArmTmrCtrl_Prescale64 =0x3f00u, // value to prescale by 64 (matches cycle counter prescaler) |
|
64 }; |
|
65 |
|
66 enum TArmTimerIntStatus |
|
67 { |
|
68 E_ArmTmrIntStatus_Event =1u // set when timer counter reaches zero, write 1 to clear |
|
69 }; |
|
70 |
|
71 enum TArmTimerWRS |
|
72 { |
|
73 E_ArmTmrWRS_ResetSent =1u // set if the watchdog caused a reset, write 1 to clear |
|
74 }; |
|
75 |
|
76 enum TArmTimerWDDisable |
|
77 { |
|
78 E_ArmTmrWDD_1 =0x12345678u, // to disable watchdog, write this ... |
|
79 E_ArmTmrWDD_2 =0x87654321u, // ... then this with no intervening writes |
|
80 }; |
|
81 |
|
82 |
|
83 |
|
84 #endif // __ARM_TMR_H__ |