14 // include/drivers/dmadefs.h |
14 // include/drivers/dmadefs.h |
15 // DMA Framework - General class, enum, constant and type definitions. |
15 // DMA Framework - General class, enum, constant and type definitions. |
16 // |
16 // |
17 // |
17 // |
18 |
18 |
|
19 /** @file |
|
20 @publishedPartner |
|
21 */ |
|
22 |
19 #ifndef __DMADEFS_H__ |
23 #ifndef __DMADEFS_H__ |
20 #define __DMADEFS_H__ |
24 #define __DMADEFS_H__ |
21 |
25 |
22 |
26 |
23 #include <e32def.h> |
27 #include <e32def.h> |
24 |
28 |
25 |
29 |
26 /** The client request callback type */ |
30 /** The client request callback type. |
|
31 |
|
32 */ |
27 enum TDmaCallbackType |
33 enum TDmaCallbackType |
28 { |
34 { |
29 /** Transfer request completion callback */ |
35 /** Transfer request completion callback |
|
36 |
|
37 @released |
|
38 */ |
30 EDmaCallbackRequestCompletion = 0x01, |
39 EDmaCallbackRequestCompletion = 0x01, |
31 /** Transfer request completion callback - source side */ |
40 /** Transfer request completion callback - source side |
|
41 |
|
42 @prototype |
|
43 */ |
32 EDmaCallbackRequestCompletion_Src = 0x02, |
44 EDmaCallbackRequestCompletion_Src = 0x02, |
33 /** Transfer request completion callback - destination side */ |
45 /** Transfer request completion callback - destination side |
|
46 |
|
47 @prototype |
|
48 */ |
34 EDmaCallbackRequestCompletion_Dst = 0x04, |
49 EDmaCallbackRequestCompletion_Dst = 0x04, |
35 |
50 |
36 /** Descriptor completion callback */ |
51 /** Descriptor completion callback |
|
52 |
|
53 @prototype |
|
54 */ |
37 EDmaCallbackDescriptorCompletion = 0x08, |
55 EDmaCallbackDescriptorCompletion = 0x08, |
38 /** Descriptor completion callback - source side */ |
56 /** Descriptor completion callback - source side |
|
57 |
|
58 @prototype |
|
59 */ |
39 EDmaCallbackDescriptorCompletion_Src = 0x10, |
60 EDmaCallbackDescriptorCompletion_Src = 0x10, |
40 /** Descriptor completion callback - destination side */ |
61 /** Descriptor completion callback - destination side |
|
62 |
|
63 @prototype |
|
64 */ |
41 EDmaCallbackDescriptorCompletion_Dst = 0x20, |
65 EDmaCallbackDescriptorCompletion_Dst = 0x20, |
42 |
66 |
43 /** Frame completion callback */ |
67 /** Frame completion callback |
|
68 |
|
69 @prototype |
|
70 */ |
44 EDmaCallbackFrameCompletion = 0x40, |
71 EDmaCallbackFrameCompletion = 0x40, |
45 /** Frame completion callback - source side */ |
72 /** Frame completion callback - source side |
|
73 |
|
74 @prototype |
|
75 */ |
46 EDmaCallbackFrameCompletion_Src = 0x80, |
76 EDmaCallbackFrameCompletion_Src = 0x80, |
47 /** Frame completion callback - destination side */ |
77 /** Frame completion callback - destination side |
|
78 |
|
79 @prototype |
|
80 */ |
48 EDmaCallbackFrameCompletion_Dst = 0x100, |
81 EDmaCallbackFrameCompletion_Dst = 0x100, |
49 |
82 |
50 /** H/W descriptor pause event callback */ |
83 /** H/W descriptor pause event callback |
|
84 |
|
85 @prototype |
|
86 */ |
51 EDmaCallbackLinkedListPaused = 0x200, |
87 EDmaCallbackLinkedListPaused = 0x200, |
52 /** H/W descriptor pause event callback - source side */ |
88 /** H/W descriptor pause event callback - source side |
|
89 |
|
90 @prototype |
|
91 */ |
53 EDmaCallbackLinkedListPaused_Src = 0x400, |
92 EDmaCallbackLinkedListPaused_Src = 0x400, |
54 /** H/W descriptor pause event callback - destination side */ |
93 /** H/W descriptor pause event callback - destination side |
|
94 |
|
95 @prototype |
|
96 */ |
55 EDmaCallbackLinkedListPaused_Dst = 0x800 |
97 EDmaCallbackLinkedListPaused_Dst = 0x800 |
56 }; |
98 }; |
57 |
99 |
58 |
100 |
59 /** The outcome of the transfer request */ |
101 /** The outcome of the transfer request. |
|
102 |
|
103 @released |
|
104 */ |
60 enum TDmaResult |
105 enum TDmaResult |
61 { |
106 { |
62 /** Completed without error */ |
107 /** Completed without error */ |
63 EDmaResultOK = 0, |
108 EDmaResultOK = 0, |
64 /** There was an error */ |
109 /** There was an error */ |
65 EDmaResultError |
110 EDmaResultError |
66 }; |
111 }; |
67 |
112 |
68 |
113 |
69 |
|
70 /** To be used with address mode field of the DMA transfer config struct. |
114 /** To be used with address mode field of the DMA transfer config struct. |
71 |
115 |
72 @see TDmaTransferConfig::iAddrMode |
116 @see TDmaTransferConfig::iAddrMode |
73 */ |
117 */ |
74 enum TDmaAddrMode |
118 enum TDmaAddrMode |
75 { |
119 { |
76 /** Constant addressing. The address remains the same for consecutive |
120 /** Constant addressing. The address remains the same for consecutive |
77 accesses. |
121 accesses. |
|
122 |
|
123 @released |
78 */ |
124 */ |
79 KDmaAddrModeConstant, |
125 KDmaAddrModeConstant, |
80 /** Post-increment addressing. The address increases by the element size |
126 /** Post-increment addressing. The address increases by the element size |
81 after each access. |
127 after each access. |
|
128 |
|
129 @released |
82 */ |
130 */ |
83 KDmaAddrModePostIncrement, |
131 KDmaAddrModePostIncrement, |
84 /** Post-decrement addressing. The address decreases by the element size |
132 /** Post-decrement addressing. The address decreases by the element size |
85 after each access. |
133 after each access. |
|
134 |
|
135 @prototype |
86 */ |
136 */ |
87 KDmaAddrModePostDecrement, |
137 KDmaAddrModePostDecrement, |
88 /** 1D-index addressing. The address always increases by the element size |
138 /** 1D-index addressing. The address always increases by the element size |
89 plus the element skip value after each access. |
139 plus the element skip value after each access. |
|
140 |
|
141 @prototype |
90 */ |
142 */ |
91 KDmaAddrMode1DIndex, |
143 KDmaAddrMode1DIndex, |
92 /** 2D-index addressing. The address increases by the element size plus the |
144 /** 2D-index addressing. The address increases by the element size plus the |
93 element skip value - but only within a frame. Once a full frame has been |
145 element skip value - but only within a frame. Once a full frame has been |
94 transferred, the address increases by the element size plus the element |
146 transferred, the address increases by the element size plus the element |
95 skip value plus the frame skip value. |
147 skip value plus the frame skip value. |
|
148 |
|
149 @prototype |
96 */ |
150 */ |
97 KDmaAddrMode2DIndex |
151 KDmaAddrMode2DIndex |
98 }; |
152 }; |
99 |
153 |
100 |
154 |
101 /** To be used with the burst size field of the DMA transfer config struct. |
155 /** To be used with the burst size field of the DMA transfer config struct. |
102 |
156 |
103 @see SDmacCaps::iBurstTransactions |
157 @see SDmacCaps::iBurstTransactions |
104 @see TDmaTransferConfig::iBurstSize |
158 @see TDmaTransferConfig::iBurstSize |
|
159 |
|
160 @prototype |
105 */ |
161 */ |
106 enum TDmaBurstSize |
162 enum TDmaBurstSize |
107 { |
163 { |
108 /** Don't use burst transactions */ |
164 /** Don't use burst transactions */ |
109 KDmaNoBursts = -1, |
165 KDmaNoBursts = -1, |
130 */ |
186 */ |
131 enum TDmaTransferFlags |
187 enum TDmaTransferFlags |
132 { |
188 { |
133 /** Location is address of a memory buffer (as opposed to a peripheral or a |
189 /** Location is address of a memory buffer (as opposed to a peripheral or a |
134 register). |
190 register). |
|
191 |
|
192 @released |
135 */ |
193 */ |
136 KDmaMemAddr = 0x01, |
194 KDmaMemAddr = 0x01, |
137 /** Address is a physical address (as opposed to a linear one). |
195 /** Address is a physical address (as opposed to a linear one). |
|
196 |
138 If it is a memory address then KDmaMemIsContiguous will need to be set |
197 If it is a memory address then KDmaMemIsContiguous will need to be set |
139 as well. |
198 as well. |
|
199 |
|
200 @released |
140 */ |
201 */ |
141 KDmaPhysAddr = 0x02, |
202 KDmaPhysAddr = 0x02, |
142 /** Target memory is known to be physically contiguous, hence there is |
203 /** Target memory is known to be physically contiguous, hence there is |
143 no need for the framework to check for memory fragmentation. |
204 no need for the framework to check for memory fragmentation. |
|
205 |
|
206 @released |
144 */ |
207 */ |
145 KDmaMemIsContiguous = 0x04, |
208 KDmaMemIsContiguous = 0x04, |
146 /** Don't use packed access (if possible) */ |
209 /** Don't use packed access (if possible) |
|
210 |
|
211 @released |
|
212 */ |
147 KDmaDontUsePacked = 0x08, |
213 KDmaDontUsePacked = 0x08, |
148 /** Location is big endian (little endian if not set). |
214 /** Location is big endian (little endian if not set). |
149 |
215 |
150 To have any effect, this flag requires the DMAC to support endianness |
216 To have any effect, this flag requires the DMAC to support endianness |
151 conversion. |
217 conversion. |
152 |
218 |
153 @see SDmacCaps::iEndiannessConversion |
219 @see SDmacCaps::iEndiannessConversion |
|
220 |
|
221 @prototype |
154 */ |
222 */ |
155 KDmaBigEndian = 0x10, |
223 KDmaBigEndian = 0x10, |
156 /** Don't do endianness conversion even if applicable. |
224 /** Don't do endianness conversion even if applicable. |
157 |
225 |
158 To have any effect, this flag requires the DMAC to support endianness |
226 To have any effect, this flag requires the DMAC to support endianness |
159 conversion. |
227 conversion. |
160 |
228 |
161 @see SDmacCaps::iEndiannessConversion |
229 @see SDmacCaps::iEndiannessConversion |
|
230 |
|
231 @prototype |
162 */ |
232 */ |
163 KDmaLockEndian = 0x20, |
233 KDmaLockEndian = 0x20, |
164 /** Execute client request callback after each subtransfer (streaming / |
234 /** Execute client request callback after each subtransfer (streaming / |
165 loop case). |
235 loop case). |
166 |
236 |
181 asymmetric descriptor interrupts as well, this flag should not be set |
253 asymmetric descriptor interrupts as well, this flag should not be set |
182 on only one (source or destination) side. |
254 on only one (source or destination) side. |
183 |
255 |
184 @see SDmacCaps::iDescriptorInterrupt |
256 @see SDmacCaps::iDescriptorInterrupt |
185 @see SDmacCaps::iAsymDescriptorInterrupt |
257 @see SDmacCaps::iAsymDescriptorInterrupt |
|
258 |
|
259 @prototype |
186 */ |
260 */ |
187 KDmaCallbackAfterEveryDescriptor = 0x80, |
261 KDmaCallbackAfterEveryDescriptor = 0x80, |
188 /** Execute client request callback after each completed frame. |
262 /** Execute client request callback after each completed frame. |
189 |
263 |
190 Requires the DMAC to support this feature. Unless the DMAC supports |
264 Requires the DMAC to support this feature. Unless the DMAC supports |
191 asymmetric frame interrupts as well, this flag should not be set on |
265 asymmetric frame interrupts as well, this flag should not be set on |
192 only one (source or destination) side. |
266 only one (source or destination) side. |
193 |
267 |
194 @see SDmacCaps::iFrameInterrupt |
268 @see SDmacCaps::iFrameInterrupt |
195 @see SDmacCaps::iAsymFrameInterrupt |
269 @see SDmacCaps::iAsymFrameInterrupt |
|
270 |
|
271 @prototype |
196 */ |
272 */ |
197 KDmaCallbackAfterEveryFrame = 0x100 |
273 KDmaCallbackAfterEveryFrame = 0x100 |
198 }; |
274 }; |
199 |
275 |
200 |
276 |
201 /** To be used with the synchronization flags field of a DMA transfer |
277 /** To be used with the synchronization flags field of a DMA transfer |
202 config struct. |
278 config struct. |
203 |
279 |
204 @see SDmacCaps::iSynchronizationTypes |
280 @see SDmacCaps::iSynchronizationTypes |
205 @see TDmaTransferConfig::iSyncFlags |
281 @see TDmaTransferConfig::iSyncFlags |
|
282 |
|
283 @released |
206 */ |
284 */ |
207 enum TDmaTransferSyncFlags |
285 enum TDmaTransferSyncFlags |
208 { |
286 { |
209 /** Leave the decision on whether the transfer is hardware synchronized at |
287 /** Leave the decision on whether the transfer is hardware synchronized at |
210 this end (either source or destination) to the Framework. This is the |
288 this end (either source or destination) to the framework. This is the |
211 default. |
289 default. |
212 */ |
290 */ |
213 KDmaSyncAuto = 0x00, |
291 KDmaSyncAuto = 0x00, |
214 /** Transfer is not hardware synchronized at this end (either source or |
292 /** Transfer is not hardware synchronized at this end (either source or |
215 destination). |
293 destination). |
263 */ |
343 */ |
264 enum TDmaPILFlags |
344 enum TDmaPILFlags |
265 { |
345 { |
266 /** Request a different max transfer size (for instance for test |
346 /** Request a different max transfer size (for instance for test |
267 purposes). |
347 purposes). |
|
348 |
|
349 @released |
268 */ |
350 */ |
269 KDmaAltTransferLength = 0x01, |
351 KDmaAltTransferLength = 0x01, |
270 /** Execute client request callback in ISR context instead of from a |
352 /** Execute client request callback in ISR context instead of from a |
271 DFC. |
353 DFC. |
|
354 |
|
355 @released |
272 */ |
356 */ |
273 KDmaRequestCallbackFromIsr = 0x02, |
357 KDmaRequestCallbackFromIsr = 0x02, |
274 /** Execute descriptor completion callback in ISR context instead of |
358 /** Execute descriptor completion callback in ISR context instead of |
275 from a DFC. This option is to be used in conjunction with the |
359 from a DFC. This option is to be used in conjunction with the |
276 TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag. |
360 TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag. |
|
361 |
|
362 @prototype |
277 */ |
363 */ |
278 KDmaDescriptorCallbackFromIsr = 0x04, |
364 KDmaDescriptorCallbackFromIsr = 0x04, |
279 /** Execute frame completion callback in ISR context instead of |
365 /** Execute frame completion callback in ISR context instead of |
280 from a DFC. This option is to be used in conjunction with the |
366 from a DFC. This option is to be used in conjunction with the |
281 TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag. |
367 TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag. |
|
368 |
|
369 @prototype |
282 */ |
370 */ |
283 KDmaFrameCallbackFromIsr = 0x08, |
371 KDmaFrameCallbackFromIsr = 0x08, |
284 /** Execute the client request callback separately for source and |
372 /** Execute the client request callback separately for source and |
285 destination subtransfers. |
373 destination subtransfers. |
286 |
374 |
319 EDmaCallbackFrameCompletion. |
411 EDmaCallbackFrameCompletion. |
320 |
412 |
321 Requires the DMAC to support this feature. |
413 Requires the DMAC to support this feature. |
322 |
414 |
323 @see SDmacCaps::iAsymFrameInterrupt |
415 @see SDmacCaps::iAsymFrameInterrupt |
|
416 |
|
417 @prototype |
324 */ |
418 */ |
325 KDmaAsymFrameCallback = 0x40, |
419 KDmaAsymFrameCallback = 0x40, |
326 /** This transfer (only) should use the channel priority indicated by |
420 /** This transfer (only) should use the channel priority indicated by |
327 TDmaTransferArgs::iChannelPriority. |
421 TDmaTransferArgs::iChannelPriority. |
|
422 |
|
423 @prototype |
328 */ |
424 */ |
329 KDmaRequestChannelPriority = 0x80 |
425 KDmaRequestChannelPriority = 0x80 |
330 }; |
426 }; |
331 |
427 |
332 |
428 |
333 /** Values which can be used with the priority field when opening a channel |
429 /** Values which can be used with the priority field when opening a channel |
334 and/or when fragmenting a transfer request. |
430 and/or when fragmenting a transfer request. |
335 |
431 |
336 @see TDmaChannel::SCreateInfo::iPriority |
432 @see TDmaChannel::SCreateInfo::iPriority |
337 @see TDmaTransferArgs::iChannelPriority |
433 @see TDmaTransferArgs::iChannelPriority |
|
434 |
|
435 @prototype |
338 */ |
436 */ |
339 enum TDmaPriority |
437 enum TDmaPriority |
340 { |
438 { |
341 /** No transfer priority preference (don't care value) */ |
439 /** No transfer priority preference (don't care value) */ |
342 KDmaPriorityNone = 0x0, |
440 KDmaPriorityNone = 0x0, |
439 @see TDmaBurstSize |
544 @see TDmaBurstSize |
440 */ |
545 */ |
441 TInt iBurstSize; |
546 TInt iBurstSize; |
442 /** PIL src/dst config flags. |
547 /** PIL src/dst config flags. |
443 @see TDmaTransferFlags |
548 @see TDmaTransferFlags |
444 */ |
549 */ |
445 TUint32 iFlags; |
550 TUint32 iFlags; |
446 /** Transfer synchronization flags. |
551 /** Transfer synchronization flags. |
447 @see TDmaTransferSyncFlags |
552 @see TDmaTransferSyncFlags |
448 */ |
553 */ |
449 TUint32 iSyncFlags; |
554 TUint32 iSyncFlags; |
450 /** Information passed to the PSL */ |
555 /** Information passed to the PSL */ |
451 TUint iPslTargetInfo; |
556 TUint iPslTargetInfo; |
452 /** How often to repeat this (sub-)transfer: |
557 /** How often to repeat this (sub-)transfer: |
453 0 no repeat (the default) |
558 0 no repeat (the default) |
454 1..n once / n times |
559 1..n once / n times |
455 -1 endlessly. |
560 -1 endlessly. |
|
561 |
|
562 @prototype |
456 */ |
563 */ |
457 TInt iRepeatCount; |
564 TInt iRepeatCount; |
458 /** Structure contents delta vector (usage tbd) */ |
565 /** Structure contents delta vector. |
|
566 |
|
567 (usage tbd) |
|
568 |
|
569 @prototype |
|
570 */ |
459 TUint32 iDelta; |
571 TUint32 iDelta; |
460 /** Reserved for future use */ |
572 /** Reserved for future use */ |
461 TUint32 iReserved; |
573 TUint32 iReserved; |
462 |
574 |
463 private: |
575 private: |
464 /** Private constructor. Initializes fields with the values passed in by |
576 /** Private constructor. |
465 the legacy version of the DDmaRequest::Fragment() call. |
577 |
|
578 Initializes fields with the values passed in by the legacy version of |
|
579 the DDmaRequest::Fragment() call. |
466 */ |
580 */ |
467 TDmaTransferConfig(TUint32 aAddr, TUint aFlags, TBool aAddrInc); |
581 TDmaTransferConfig(TUint32 aAddr, TUint aFlags, TBool aAddrInc); |
468 }; |
582 }; |
469 |
583 |
470 |
584 |
473 |
587 |
474 Also used internally by the framework as a pseudo descriptor if the |
588 Also used internally by the framework as a pseudo descriptor if the |
475 controller doesn't support hardware descriptors (scatter/gather LLI). |
589 controller doesn't support hardware descriptors (scatter/gather LLI). |
476 |
590 |
477 @see DDmaRequest::Fragment |
591 @see DDmaRequest::Fragment |
|
592 |
|
593 @released |
478 */ |
594 */ |
479 struct TDmaTransferArgs |
595 struct TDmaTransferArgs |
480 { |
596 { |
481 friend class DDmaRequest; |
597 friend class DDmaRequest; |
482 friend class TDmaChannel; |
598 friend class TDmaChannel; |
483 friend class TDmac; |
599 friend class TDmac; |
484 friend class DmaChannelMgr; |
600 friend class DmaChannelMgr; |
485 |
601 |
486 /** Default constructor. Initializes all fields with meaningful default |
602 /** Default constructor. |
487 values. |
603 |
|
604 Initializes all fields with meaningful default values. |
488 */ |
605 */ |
489 #ifdef DMA_APIV2 |
606 #ifdef DMA_APIV2 |
490 KIMPORT_C |
607 KIMPORT_C |
491 #endif |
608 #endif |
492 TDmaTransferArgs(); |
609 TDmaTransferArgs(); |
493 |
610 |
494 /** For transfers where src and dst TDmaTransferConfig structs share some |
611 /** Alternate constructor. |
495 of the same options ie. iDmaTransferFlags, iAddrMode, iSyncFlags, |
612 |
496 iBurstSize, and iElementSize. |
613 Intended for transfers where src and dst TDmaTransferConfig structs |
|
614 share some of the same options, i.e. iDmaTransferFlags, iAddrMode, |
|
615 iSyncFlags, iBurstSize, and iElementSize. |
497 |
616 |
498 @param aSrcAddr |
617 @param aSrcAddr |
499 @param aDstAddr |
618 @param aDstAddr |
500 @param aCount Number of bytes to transfer |
619 @param aCount Number of bytes to transfer |
501 @param aDmaTransferFlags Bitmask of TDmaTransferFlags for src and dst |
620 @param aDmaTransferFlags Bitmask of TDmaTransferFlags for src and dst |
511 */ |
630 */ |
512 #ifdef DMA_APIV2 |
631 #ifdef DMA_APIV2 |
513 KIMPORT_C |
632 KIMPORT_C |
514 #endif |
633 #endif |
515 TDmaTransferArgs ( |
634 TDmaTransferArgs ( |
516 TUint aSrcAddr, TUint aDstAddr, TUint aCount, |
635 TUint aSrcAddr, |
517 TUint aDmaTransferFlags, TUint aDmaSyncFlags = KDmaSyncAuto, |
636 TUint aDstAddr, |
|
637 TUint aCount, |
|
638 TUint aDmaTransferFlags, |
|
639 TUint aDmaSyncFlags = KDmaSyncAuto, |
518 TUint aDmaPILFlags = 0, |
640 TUint aDmaPILFlags = 0, |
519 TDmaAddrMode aMode = KDmaAddrModePostIncrement, TUint aElementSize = 0, |
641 TDmaAddrMode aMode = KDmaAddrModePostIncrement, |
|
642 TUint aElementSize = 0, |
520 TUint aChannelPriority = KDmaPriorityNone, |
643 TUint aChannelPriority = KDmaPriorityNone, |
521 TDmaBurstSize aBurstSize = KDmaBurstSizeAny, TUint aPslRequestInfo = 0, |
644 TDmaBurstSize aBurstSize = KDmaBurstSizeAny, |
522 TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, TUint32 aColour = 0 |
645 TUint aPslRequestInfo = 0, |
|
646 TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, |
|
647 TUint32 aColour = 0 |
523 ); |
648 ); |
524 |
649 |
525 /** For transfers needing specific options for source and destination |
650 /** Alternate constructor. |
526 TDmaTransferConfig structs. |
651 |
|
652 Intended for transfers needing specific options for source and |
|
653 destination TDmaTransferConfig structs. |
527 |
654 |
528 @param aSrc Configuration values for the source |
655 @param aSrc Configuration values for the source |
529 @param aDst Configuration values for the destination |
656 @param aDst Configuration values for the destination |
530 @param aFlags @see TDmaPILFlags |
657 @param aFlags @see TDmaPILFlags |
531 @param aChannelPriority Use for this request (only) the indicated |
658 @param aChannelPriority Use for this request (only) the indicated |
532 channel priority. Requires KDmaRequestChannelPriority to be set in |
659 channel priority. Requires KDmaRequestChannelPriority to be set in |
533 iFlags as well. @see TDmaPriority |
660 iFlags as well. @see TDmaPriority |
534 |
|
535 @param aPslRequestInfo Info word passed to the PSL |
661 @param aPslRequestInfo Info word passed to the PSL |
536 @param aGraphicOp Graphics operation to be executed |
662 @param aGraphicOp Graphics operation to be executed |
537 @param aColour Colour value for graphics operation |
663 @param aColour Colour value for graphics operation |
538 */ |
664 */ |
539 #ifdef DMA_APIV2 |
665 #ifdef DMA_APIV2 |
578 @see TDmaPriority |
705 @see TDmaPriority |
579 */ |
706 */ |
580 TUint iChannelPriority; |
707 TUint iChannelPriority; |
581 /** Info word passed to the PSL */ |
708 /** Info word passed to the PSL */ |
582 TUint iPslRequestInfo; |
709 TUint iPslRequestInfo; |
583 |
710 /** Stores the PSL cookie returned by TDmaChannel::PslId() at request |
584 /** Structure contents delta vector (usage tbd) */ |
711 fragmentation time. |
|
712 |
|
713 The value PslId() is often (but not necessarily) identical with the |
|
714 client's TDmaChannel::SCreateInfo::iCookie, which gets passed by the |
|
715 PIL into DmaChannelMgr::Open() as 'aOpenId'. |
|
716 */ |
|
717 TUint32 iChannelCookie; |
|
718 /** Structure contents delta vector. |
|
719 |
|
720 (usage tbd) |
|
721 |
|
722 @prototype |
|
723 */ |
585 TUint32 iDelta; |
724 TUint32 iDelta; |
586 /** Reserved for future use */ |
725 /** Reserved for future use */ |
587 TUint32 iReserved1; |
726 TUint32 iReserved1; |
588 |
727 |
589 private: |
728 private: |
590 /** Private constructor. Initializes fields with the values passed in by |
729 /** Private constructor. |
591 the legacy version of the DDmaRequest::Fragment() call. |
730 |
|
731 Initializes fields with the values passed in by the legacy version of |
|
732 the DDmaRequest::Fragment() call. |
592 */ |
733 */ |
593 TDmaTransferArgs(TUint32 aSrcAddr, TUint32 aDstAddr, TInt aCount, |
734 TDmaTransferArgs(TUint32 aSrcAddr, TUint32 aDstAddr, TInt aCount, |
594 TUint aFlags, TUint32 aPslInfo); |
735 TUint aFlags, TUint32 aPslInfo); |
595 /** Stores the PSL cookie returned by TDmaChannel::PslId() at request |
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596 fragmentation time. |
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597 The value PslId() is often (but not necessarily) identical with the |
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598 client's TDmaChannel::SCreateInfo::iCookie, which gets passed by the |
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599 PIL into DmaChannelMgr::Open() as 'aOpenId'. |
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600 */ |
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601 TUint32 iChannelCookie; |
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602 /** Reserved for future use */ |
736 /** Reserved for future use */ |
603 TUint32 iReserved2; |
737 TUint32 iReserved2; |
604 }; |
738 }; |
605 |
739 |
606 |
740 |
607 /** DMAC capabilities info structure. |
741 /** DMAC capabilities info structure. |
608 |
742 |
609 Instances are to be filled in by the PSL and then linked to via TDmaChannel |
743 Instances are to be filled in by the PSL and then linked to via TDmaChannel |
610 objects after they have been opened. |
744 objects after they have been opened. |
611 |
745 |
612 The contents may vary even between channels on the same DMAC (but will |
746 The contents may vary even between channels on the same DMAC (but should |
613 remain constant for a given channel for the duration that it is open), |
747 remain constant for a given channel for the duration that it is open), |
614 depending on static or dynamic factors which only the PSL knows about. |
748 depending on static or dynamic factors which only the PSL knows about. |
615 |
749 |
616 @see TDmaChannel::Open |
750 @see TDmaChannel::Open |
617 @see TDmaChannel::DmacCaps |
751 @see TDmaChannel::DmacCaps |
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752 |
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753 @released |
618 */ |
754 */ |
619 struct SDmacCaps |
755 struct SDmacCaps |
620 { |
756 { |
621 /** DMAC supports n + 1 different channel priorities. */ |
757 /** DMAC supports n + 1 different channel priorities. |
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758 */ |
622 TUint iChannelPriorities; |
759 TUint iChannelPriorities; |
623 /** DMAC supports the pausing and resuming of channels. */ |
760 /** DMAC supports the pausing and resuming of channels. |
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761 */ |
624 TBool iChannelPauseAndResume; |
762 TBool iChannelPauseAndResume; |
625 /** DMA addresses must be aligned on an element size boundary. */ |
763 /** DMA addresses must be aligned on an element size boundary. |
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764 */ |
626 TBool iAddrAlignedToElementSize; |
765 TBool iAddrAlignedToElementSize; |
627 /** DMAC supports 1D (element) index addressing in hardware. */ |
766 /** DMAC supports 1D (element) index addressing in hardware. |
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767 */ |
628 TBool i1DIndexAddressing; |
768 TBool i1DIndexAddressing; |
629 /** DMAC supports 2D (frame) index addressing in hardware. */ |
769 /** DMAC supports 2D (frame) index addressing in hardware. |
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770 */ |
630 TBool i2DIndexAddressing; |
771 TBool i2DIndexAddressing; |
631 /** DMAC supports these transfer synchronization types (bitmap of values). |
772 /** DMAC supports these transfer synchronization types (bitmap of values). |
632 |
773 |
633 @see TDmaTransferSyncFlags |
774 @see TDmaTransferSyncFlags |
634 */ |
775 */ |
636 /** DMAC supports burst transactions with these sizes (bitmap of values). |
777 /** DMAC supports burst transactions with these sizes (bitmap of values). |
637 |
778 |
638 @see TDmaBurstSize |
779 @see TDmaBurstSize |
639 */ |
780 */ |
640 TUint iBurstTransactions; |
781 TUint iBurstTransactions; |
641 /** DMAC supports a 'h/w descriptor complete' interrupt. */ |
782 /** DMAC supports a 'h/w descriptor complete' interrupt. |
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783 */ |
642 TBool iDescriptorInterrupt; |
784 TBool iDescriptorInterrupt; |
643 /** DMAC supports a 'frame transfer complete' interrupt. */ |
785 /** DMAC supports a 'frame transfer complete' interrupt. |
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786 */ |
644 TBool iFrameInterrupt; |
787 TBool iFrameInterrupt; |
645 /** DMAC supports a 'linked-list pause event' interrupt. */ |
788 /** DMAC supports a 'linked-list pause event' interrupt. |
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789 */ |
646 TBool iLinkedListPausedInterrupt; |
790 TBool iLinkedListPausedInterrupt; |
647 /** DMAC supports endianness conversion. */ |
791 /** DMAC supports endianness conversion. |
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792 */ |
648 TBool iEndiannessConversion; |
793 TBool iEndiannessConversion; |
649 /** DMAC supports these graphics operations (bitmap of values). |
794 /** DMAC supports these graphics operations (bitmap of values). |
650 |
795 |
651 @see TDmaGraphicsOps |
796 @see TDmaGraphicsOps |
652 */ |
797 */ |
653 TUint iGraphicsOps; |
798 TUint iGraphicsOps; |
654 /** DMAC supports repeated transfers (loops). */ |
799 /** DMAC supports repeated transfers (loops). |
|
800 */ |
655 TBool iRepeatingTransfers; |
801 TBool iRepeatingTransfers; |
656 /** DMAC supports logical channel linking (chaining). */ |
802 /** DMAC supports logical channel linking (chaining). |
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803 */ |
657 TBool iChannelLinking; |
804 TBool iChannelLinking; |
658 /** DMAC supports scatter/gather mode (linked list items). */ |
805 /** DMAC supports scatter/gather mode (linked list items). |
|
806 */ |
659 TBool iHwDescriptors; |
807 TBool iHwDescriptors; |
660 /** DMAC supports asymmetric source and destination transfer |
808 /** DMAC supports asymmetric source and destination transfer |
661 parameters (such as element size). |
809 parameters (such as element size). |
662 */ |
810 */ |
663 TBool iSrcDstAsymmetry; |
811 TBool iSrcDstAsymmetry; |
710 /** Reserved for future use */ |
858 /** Reserved for future use */ |
711 TUint32 iReserved[5]; |
859 TUint32 iReserved[5]; |
712 }; |
860 }; |
713 |
861 |
714 |
862 |
|
863 ////////////////////////////////////////////////////////////////////////////// |
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864 // INTERFACE WITH TEST HARNESS |
|
865 ////////////////////////////////////////////////////////////////////////////// |
|
866 |
|
867 /** Set of information used by test harness. |
|
868 |
|
869 @deprecated |
|
870 */ |
|
871 #ifdef DMA_APIV2 |
|
872 struct TDmaTestInfo |
|
873 { |
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874 /** Maximum transfer size in bytes for all channels (ie. the minimum of all |
|
875 channels' maximum size) |
|
876 */ |
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877 TUint iMaxTransferSize; |
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878 /** 3->Memory buffers must be 4-byte aligned, 7->8-byte aligned, ... */ |
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879 TUint iMemAlignMask; |
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880 /** Cookie to pass to DDmaRequest::Fragment for memory-memory transfer */ |
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881 TUint32 iMemMemPslInfo; |
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882 /** Number of test single-buffer channels */ |
|
883 TInt iMaxSbChannels; |
|
884 /** Pointer to array containing single-buffer test channel ids */ |
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885 TUint32* iSbChannels; |
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886 /** Number of test double-buffer channels */ |
|
887 TInt iMaxDbChannels; |
|
888 /** Pointer to array containing double-buffer test channel ids */ |
|
889 TUint32* iDbChannels; |
|
890 /** Number of test scatter-gather channels */ |
|
891 TInt iMaxSgChannels; |
|
892 /** Pointer to array containing scatter-gather test channel ids */ |
|
893 TUint32* iSgChannels; |
|
894 }; |
|
895 #endif |
|
896 |
|
897 |
|
898 /** Set of information used by test harness. |
|
899 |
|
900 @released |
|
901 */ |
715 struct TDmaV2TestInfo |
902 struct TDmaV2TestInfo |
716 { |
903 { |
717 enum {KMaxChannels=32}; |
904 enum {KMaxChannels=32}; |
718 /** Maximum transfer size in bytes for all channels (ie. the minimum of all channels' maximum size)*/ |
905 /** Maximum transfer size in bytes for all channels (ie. the minimum of all |
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906 channels' maximum size) |
|
907 */ |
719 TUint iMaxTransferSize; |
908 TUint iMaxTransferSize; |
720 /** 3->Memory buffers must be 4-byte aligned, 7->8-byte aligned, ... */ |
909 /** 3->Memory buffers must be 4-byte aligned, 7->8-byte aligned, ... */ |
721 TUint iMemAlignMask; |
910 TUint iMemAlignMask; |
722 /** Cookie to pass to DDmaRequest::Fragment for memory-memory transfer */ |
911 /** Cookie to pass to DDmaRequest::Fragment for memory-memory transfer */ |
723 TUint32 iMemMemPslInfo; |
912 TUint32 iMemMemPslInfo; |