bsptemplate/asspandvariant/template_variant/variant.mmh
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     1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
       
     2 // All rights reserved.
       
     3 // This component and the accompanying materials are made available
       
     4 // under the terms of the License "Eclipse Public License v1.0"
       
     5 // which accompanies this distribution, and is available
       
     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
       
     7 //
       
     8 // Initial Contributors:
       
     9 // Nokia Corporation - initial contribution.
       
    10 //
       
    11 // Contributors:
       
    12 //
       
    13 // Description:
       
    14 // template/template_variant/variant.mmh
       
    15 // TO DO: (mandatory)
       
    16 // Add here a definition for your CPU (list in CONFIG.INC)
       
    17 // 
       
    18 //
       
    19 
       
    20 macro __CPU_ARM1176__
       
    21 
       
    22 // TO DO: (mandatory)
       
    23 //
       
    24 // Add here a definition for your Memory Model
       
    25 //
       
    26 #define MM_MULTIPLE
       
    27 
       
    28 // TO DO: (mandatory)
       
    29 //
       
    30 // Macro which generates the names for the binaries for this platform
       
    31 //
       
    32 #define VariantTarget(name,ext) _template_##name##.##ext
       
    33 #define VariantMediaDefIncludePath SYMBIAN_OS_LAYER_PLATFORM_EXPORT_PATH(template)
       
    34 
       
    35 //Include debug support. Some e32 tests require debug support
       
    36 macro __DEBUGGER_SUPPORT__
       
    37 
       
    38 //
       
    39 // TO DO: 
       
    40 //
       
    41 // If euser is built from the variant, uncomment the following line to build it
       
    42 // as ARM rather than Thumb
       
    43 // 
       
    44 // #define __BUILD_VARIANT_EUSER_AS_ARM__
       
    45 
       
    46 // TO DO: (optional)
       
    47 //
       
    48 // To replace some of the generic utility functions with variant specific
       
    49 // versions (eg to replace memcpy with a version optimised for the hardware),
       
    50 // uncomment the two lines below and edit the files in the replacementUtils
       
    51 // directory.
       
    52 //
       
    53 // #define REPLACE_GENERIC_UTILS
       
    54 // #define VariantReplacementUtilsPath template/template_variant/replacement_utils
       
    55 
       
    56 // TO DO: (optional)
       
    57 //
       
    58 // Enable BTrace support in release versions of the kernel by adding
       
    59 // the following BTRACE macro declarations
       
    60 //
       
    61 // macro BTRACE_KERNEL_ALL
       
    62 
       
    63 // TO DO:
       
    64 //
       
    65 // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor.
       
    66 // 
       
    67 // macro __CPU_ARM1136_IS_R1__
       
    68 
       
    69 // TO DO:
       
    70 //
       
    71 // Include the following line if default memory mapping should use shared memory.
       
    72 // Should be on for multicore (SMP) devices.
       
    73 //
       
    74 // macro	__CPU_USE_SHARED_MEMORY
       
    75 //
       
    76 
       
    77 // TO DO:
       
    78 //
       
    79 // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973
       
    80 // "CLREX instruction might be ignored during data cache line fill"
       
    81 // is fixed on this hardware.
       
    82 // 
       
    83 // macro __CPU_ARM1136_ERRATUM_406973_FIXED
       
    84 
       
    85 // Uncomment next line if:
       
    86 //	1) using the ARM1136 processor and ARM1136 Erratum 408022 "Cancelled write to CONTEXTID register might update ASID" 
       
    87 //	   is fixed on this hardware, or
       
    88 //	2) using the ARM1176 processor and ARM1176 Erratum 415047 "Cancelled write to CONTEXTID register might update ASID" 
       
    89 //	   is fixed on this hardware.
       
    90 //
       
    91 // macro __CPU_ARM1136_ERRATUM_408022_FIXED
       
    92 
       
    93 // Uncomment if:
       
    94 //	1)	using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
       
    95 //	  	operation might fail to invalidate some lines if coincident with linefill"
       
    96 //  	  	is fixed on this hardware, or
       
    97 //	2)	using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
       
    98 // 	  	operation might fail to invalidate some lines if coincident with linefill
       
    99 //	  	is fixed on this hardware.
       
   100 // Workaround:
       
   101 //	1)	Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
       
   102 //	2)	Replaces Invalidate ICache operation with the sequence defined in the errata document.
       
   103 // If this macro is enabled, it should be accompanied by:
       
   104 // 	"GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
       
   105 //
       
   106 // macro __CPU_ARM1136_ERRATUM_411920_FIXED
       
   107 
       
   108 // TO DO:
       
   109 //
       
   110 // Uncomment the next line if using the ARM1136 processor with L210/L220 cache and ARM1136
       
   111 // Erratum 317041:"TTBR0/TTBR1 bits[4:3] do not read back correctly"
       
   112 // is fixed on this hardware.
       
   113 // 
       
   114 // macro __CPU_ARM1136_ERRATUM_317041_FIXED
       
   115 
       
   116 // Uncomment the following line if Page Tables/Dirs have to be updated in main memory.
       
   117 // Standard platforms shouldn't have this feature switched on.
       
   118 // This must be accompanied by __ARM_L210_CACHE__ or __ARM_L220_CACHE__ macro.
       
   119 // Omission::  The solution doesn't update temporary mappings 
       
   120 // of inter-process communication (IPC) - aka aliasing.
       
   121 //
       
   122 // macro __FLUSH_PT_INTO_RAM__
       
   123 
       
   124 // Uncomment the following line if Symbian OS is running in TrustZone non-secure state and the
       
   125 // secure state has prevented code executing in non-secure state from being able to mask FIQs by
       
   126 // setting the SCR.FW bit in the secure configuration register.
       
   127 //
       
   128 // macro __FIQ_RESERVED_FOR_SECURE_STATE__
       
   129 
       
   130 // Various PlatSec configuration options cannot be disabled even by clearing the appropriate
       
   131 // bits in the kernel configuration flags - they are enforced at compile time.  Uncomment the
       
   132 // following to allow the clearing of bits in the kernel config flags to disable the relevant
       
   133 // options at run time.
       
   134 //
       
   135 //macro __PLATSEC_UNLOCKED__
       
   136 
       
   137 // If this macro is enabled then EMapAttrBufferedNC memory will be remapped as EMapAttrFullyBlocking
       
   138 //macro FAULTY_NONSHARED_DEVICE_MEMORY
       
   139 
       
   140 // Uncomment the following line if L210/20 cache is running in forced-WT mode.
       
   141 // (Forced_WT bit set in Debug Control Register of L210/20 cache controller.)
       
   142 // macro __ARM_L2_CACHE_WT_MODE
       
   143 
       
   144 // For the status of errata of L210 & L220 cache, see the header of source file:
       
   145 // e32\kernel\arm\cachel2.cpp
       
   146 
       
   147 #if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__)
       
   148 library	VariantTarget(katemplate,lib)
       
   149 #endif
       
   150 
       
   151 // Uncomment the following if IIC Controller is required
       
   152 library		iic.lib
       
   153