// Copyright (c) 2004-2010 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

//

#include <e32def.h>

#include <e32def_private.h>

#include <e32cmn.h>

#include <e32cmn_private.h>

#include <u32std.h>

#include <kernel/kernel.h>

#include <kernel/kern_priv.h>

#include <nk_trace.h>

#include <arm.h>

#include <kernel/cache.h>

#include <platform.h>

#include <nkern.h>

#include <u32hal.h>

#include <rm_debug_api.h>

#include "d_rmd_breakpoints.h"

#include "d_process_tracker.h"

#include "d_rmd_stepping.h"

#include "rm_debug_kerneldriver.h"	// needed to access DRM_DebugChannel

#include "rm_debug_driver.h"

#include "debug_utils.h"

#include "debug_logging.h"

using namespace Debug;

/* @internalTechnology

 *

 * Checks whether aAddress is correctly aligned for placing a breakpoint of

 * cpu architecture aMode.

 *

 * @param aAddress - Virtual memory address to check

 * @param aMode - The CPU architecture mode of the breakpoint to be placed at aAddress

 * @return ETrue if aAddress is suitably aligned, EFalse otherwise.

 */

TBool D_RMD_Breakpoints::Aligned(TUint32 aAddress, Debug::TArchitectureMode aMode)

	{

	switch(aMode)

		{

		case Debug::EArmMode:

			// ARM breakpoints must be 32-bit aligned (lower two bits must be zero)

			if (aAddress & 0x3)

			{

				// Not 32-bit aligned.

				return EFalse;

			}

			break;

		case Debug::EThumbMode:

			// Thumb breakpoints must be 16-bit aligned (low bit must be zero)

			if (aAddress & 0x1)

			{

				// Not 16-bit aligned

				return EFalse;

			}

			break;

		case Debug::EThumb2EEMode:

			// Thumb-EE instructions are half-word aligned. See ARM ARM DDI0406A, section A3.2 Alignment Support

			// Note that some instructions need to be word-aligned, but this function does not know which ones.

			// It may also depend on the System Control register U bit.

			if (aAddress & 0x1)

			{

				// Not 16-bit aligned

				return EFalse;

			}

			break;

		default:

			{

			// No idea

			return EFalse;

			}

		}

	// Must be OK

	return ETrue;

	};

/* @internalTechnology

 *

 * Returns the size of a breakpoint of architecture aMode in bytes

 * 

 * @param aMode - The architure of the breakpoint

 * @return The size of the breakpoints in bytes. 0 if un-recognised architecture.

 */

TInt D_RMD_Breakpoints::BreakSize(Debug::TArchitectureMode aMode)

	{

	switch(aMode)

		{

		case Debug::EArmMode:

			{

				return 4;

			}

		case Debug::EThumbMode:

			{

				return 2;

			}

		case Debug::EThumb2EEMode:

			{

			// Only needs to be two bytes in size.

			return 2;

			}

		default:

			{

				// No idea

				return 0;

			}

		}

	};

/* @internalTechnology

 *

 * Checks whether two TBreakEntrys overlap

 *

 * @param aFirst - A TBreakEntry with valid iAddress and iMode fields.

 * @param aSecond  - A TBreakEntry with valid iAddress and iMode fields.

 * @return ETrue if the aFirst and aSecond overlap or the overlap cannot be determined

 *         , EFalse otherwise

 */

TBool D_RMD_Breakpoints::BreakpointsOverlap(TBreakEntry& aFirst, TBreakEntry& aSecond)

	{

	TInt firstSize = BreakSize(aFirst.iMode);

	TInt secondSize = BreakSize(aSecond.iMode);

	// Do we know the size of each breakpoint?

	if ((firstSize <= 0) || (secondSize <= 0))

		{

		// We don't know the size of the breakpoint, so assume they overlap

		return ETrue;

		}

	TInt firstStartAddress = aFirst.iAddress;

	TInt secondStartAddress = aSecond.iAddress;

	TInt firstEndAddress = firstStartAddress + firstSize - 1;

	TInt secondEndAddress = secondStartAddress + secondSize - 1;

	// If second breakpoint is past the end of the first then we're ok

	if(firstEndAddress < secondStartAddress)

		{

		return EFalse;

		}

	// If first breakpoint is past the end of the second then we're ok

	if(secondEndAddress < firstStartAddress)

		{

		return EFalse;

		}

	// The breakpoints overlap

	return ETrue;

	}

/* @internalTechnology

 * 

 * Returns the breakpoint bitpattern to use for each architecture type

 *

 * @param aMode - the cpu architecture type

 * @return The bit-pattern to use for the specified architecture, or 0 if unsupported.

 */

TUint32 D_RMD_Breakpoints::BreakInst(Debug::TArchitectureMode aMode)

	{

	switch(aMode)

		{

		case Debug::EArmMode:

			{

				return KArmBreakPoint;

			}

		case Debug::EThumbMode:

			{

				return KThumbBreakPoint;

			}

		case Debug::EThumb2EEMode:

			{

			return KT2EEBreakPoint;

			}

		default:

			{

				// No idea what the breakpoint should be

				return 0;

			}

		}

	};

/**

Constructor. Initialises its internal list of empty breakpoints.

*/

D_RMD_Breakpoints::D_RMD_Breakpoints(DRM_DebugChannel* aChannel)

: iBreakPointList(NUMBER_OF_TEMP_BREAKPOINTS, 0),

  iNextBreakId(NUMBER_OF_TEMP_BREAKPOINTS),

  iChannel(aChannel),

  iInitialised(EFalse)

	{

	iBreakPointList.Reset();	

	TBreakEntry emptyTempBreak;

	for (TInt i = 0; i < NUMBER_OF_TEMP_BREAKPOINTS; i++)

		{

		emptyTempBreak.iBreakId = i;

		if (KErrNone != iBreakPointList.Append(emptyTempBreak))

			{

			LOG_MSG("D_RMD_Breakpoints::D_RMD_Breakpoints() - Error appending blank temp break entry");

			}

		}

	}

/**

Destructor. Clears all the breakpoints in the system, deletes its internal list of breakpoints,

and closes the exclusivity semaphore.

*/

D_RMD_Breakpoints::~D_RMD_Breakpoints()

	{

	ClearAllBreakPoints();

	// close the breakpoint list and free the memory associated with it

	iBreakPointList.Close();

	if (iLock)

		iLock->Close(NULL);

	}

/**

Initialises the breakpoint list exclusion semaphore. This should be called once immediately after

the constructor.

@return KErrNone if successful, one of the other system wide error codes otherwise.

*/

TInt D_RMD_Breakpoints::Init()

	{

	TInt err = KErrNone;

	// Only create a semaphore if we are not initialised

	if(!iInitialised)

		{

		// Initialise the semaphore ensuring exclusive access to the breakpoint list

		err = Kern::SemaphoreCreate(iLock, _L("RM_DebugBreakpointLock"), 1 /* Initial count */);

		if (err == KErrNone)

			{

			iInitialised = ETrue;

			}

		}

	else

		{

		err = KErrNone;

		}

	return err;

	}

/** 

Public member function which sets a thread-specific breakpoint in the specified thread

and returns an opaque handle to the caller.

Note 1:

This function ensures exclusive access to the breakpoint data structures

by using a semaphore to serialise access.

@see priv_DoSetBreak

Note 2:

As implied by Note 1, the caller must have previously called Init() or this

function will return KErrNotReady;

@param aBreakId - Reference to a TUint32 into which the function will return a unique breakpoint Id.

@param aThreadId - The thread Id in which to place the breakpoint

@param aAddress - Address to place the breakpoint

@param aMode - The cpu instruction set architecture type breakpoint (e.g. EArmMode or EThumbMode)

@return KErrNone if successful, otherwise one of the other system wide error codes.

*/

TInt D_RMD_Breakpoints::DoSetBreak(TInt32 &aBreakId, const TUint64 aId, const TBool aThreadSpecific, const TUint32 aAddress, const TArchitectureMode aMode)

	{

	// Ensure we have a valid semaphore

	if (!iInitialised || !iLock)

		{

		return KErrNotReady;

		}

	// Acquire the lock

	NKern::ThreadEnterCS();

	Kern::SemaphoreWait(*iLock);

	// Really do the work

	TInt err = priv_DoSetBreak(aBreakId, aId, aThreadSpecific, aAddress,aMode);

	// Release the lock

	Kern::SemaphoreSignal(*iLock);

	NKern::ThreadLeaveCS();

	return err;

	}

/**

Private member function which sets a thread-specific breakpoint in the specified thread

and returns an opaque handle to the caller.

@see DoSetBreak

@param aBreakId - Reference to a TUint32 into which the function will return a unique breakpoint Id.

@param aThreadId - The thread Id in which to place the breakpoint

@param aAddress - Address to place the breakpoint

@param aMode - The cpu instruction set architecture type breakpoint (e.g. EArmMode or EThumbMode)

@return KErrNone if successful, otherwise one of the other system wide error codes.

*/

TInt D_RMD_Breakpoints::priv_DoSetBreak(TInt32 &aBreakId, const TUint64 aId, const TBool aThreadSpecific, const TUint32 aAddress, const TArchitectureMode aMode)

	{

	LOG_MSG4("D_RMD_Breakpoints::priv_DoSetBreak(aThreadId = 0x%lx, aAddress = 0x%08x, aMode = %d)",aId,aAddress,aMode);

	// EThumb2EEMode breakpoints are not supported

	if (EThumb2EEMode == aMode)

		{

		LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - EThumb2EEMode breakpoints are not supported");

		return KErrNotSupported;

		}

	// Check how many breakpoints we have in existence

	if ((iBreakPointList.Count()+1) >= NUMBER_OF_MAX_BREAKPOINTS)

		{

		// Too many breakpoints are set!

		LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - Too many breakpoints set");

		return KErrOverflow;

		}

	// check the alignment of the breakpoint

	if (!Aligned(aAddress,aMode))

		{

		LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - Unaligned address");

		return KErrArgument;

		}

	// make sure there is not already a breakpoint at this address

	for (TInt i = NUMBER_OF_TEMP_BREAKPOINTS; i < iBreakPointList.Count(); i++)

		{

		/* We need to check if the breakpoint overlaps the address at all,

		 * and this depends upon the size of the two breakpoints as well as 

		 * their address.

		 */

		// newInstSize = size in bytes of new breakpoint

		TInt newInstSize = BreakSize(aMode);

		if (newInstSize == 0)

			{

			LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - Unknown architecture type for new breakpoint");

			return KErrNotSupported;

			}

		// oldInstSize = size in bytes of the existing breakpoint

		TInt oldInstSize = BreakSize(iBreakPointList[i].iMode);

		if (oldInstSize == 0)

			{

			LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - : Unknown architecture type of existing breakpoint");

			return KErrNotSupported;

			}

		// Overlap checking - temp is used as the new breakpoint description for checking purposes only

		TBreakEntry temp;

		temp.iAddress = aAddress;

		temp.iMode = aMode;

		// do they overlap?

		if ( BreakpointsOverlap(temp,iBreakPointList[i]) )

			{

			// Yes

			if(iBreakPointList[i].iThreadSpecific && aThreadSpecific)

				{

				if(aId == iBreakPointList[i].iId)

					{

					LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - New thread specific breakpoint overlaps an existing thread specific breakpoint");

					return KErrAlreadyExists;

					}

				}

			else if(!iBreakPointList[i].iThreadSpecific && aThreadSpecific)

				{

				NKern::ThreadEnterCS();

				DThread* thread = DebugUtils::OpenThreadHandle(aId);

				TInt err = KErrNone;

				if (!thread)

					{

					err = KErrNotFound;

					}

				if (!err && thread->iOwningProcess->iId == iBreakPointList[i].iId)

					{

					LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - New thread specific breakpoint overlaps an existing breakpoint");

					err = KErrAlreadyExists;

					}

				thread->Close(NULL);

				NKern::ThreadLeaveCS();

				if (err) return err;

				}

			else if(iBreakPointList[i].iThreadSpecific && !aThreadSpecific)

				{

				NKern::ThreadEnterCS();

				DThread* thread = DebugUtils::OpenThreadHandle(iBreakPointList[i].iId);

				TInt err = KErrNone;

				if (!thread)

					{

					err = KErrNotFound;

					}

				if (!err && thread->iOwningProcess->iId == aId)

					{

					LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - New breakpoint overlaps an existing thread specific breakpoint");

					err = KErrAlreadyExists;

					}

				if (thread) thread->Close(NULL);

				NKern::ThreadLeaveCS();

				if (err) return err;

				}

			else // !iBreakPointList[i].iThreadSpecific && !aThreadSpecific

				{

				if(iBreakPointList[i].iId == aId)

					{

					LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - New breakpoint overlaps an existing breakpoint");

					return KErrAlreadyExists;

					}

				}

			}

		}

	// increment the break id

	aBreakId = iNextBreakId++;	

	// create the new breakpoint entry

	TBreakEntry breakEntry(aBreakId, aId, aThreadSpecific, aAddress, aMode);

	TInt err = priv_DoEnableBreak(breakEntry, ETrue);

	if (KErrNone != err)

		{

		LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - Could not enable the breakpoint");

		return err;

		}

	err = iBreakPointList.Append(breakEntry);

	if (err != KErrNone)

		{

		LOG_MSG("D_RMD_Breakpoints::priv_DoSetBreak() - Failed to append breakpoint");

		}

	LOG_MSG2("D_RMD_Breakpoints::priv_DoSetBreak(breakId = 0x%08x) done",aBreakId);

	return err;

	}

/**

Public member function which enables a previously set breakpoint.

Note 1:

This function ensures exclusive access to the breakpoint data structures

by using a semaphore to serialise access.

@see priv_DoEnableBreak

Note 2:

As implied by Note 1, the caller must have previously called Init() or this

function will return KErrNotReady;

Note 3

Historically, this function accepted a reference to a TBreakEntry in the class' own

iBreakPointList. It now checks whether the reference is to an element of its own list,

or one invented by the caller.

@param aEntry reference to a TBreakEntry datastructure describing the breakpoint to be re-enabled.

@param aSaveOldInstruction ETrue preserves the instruction at the breakpoint address, EFalse otherwise.

@return KErrNone if successful, otherwise one of the other system wide error codes.

*/

TInt D_RMD_Breakpoints::DoEnableBreak(TBreakEntry &aEntry, TBool aSaveOldInstruction)

	{

	// Ensure we have a valid semaphore

	if (!iInitialised || !iLock)

		{

		return KErrNotReady;

		}

	// Acquire the lock

	NKern::ThreadEnterCS();

	Kern::SemaphoreWait(*iLock);

	// Really do the work

	TInt err = priv_DoEnableBreak(aEntry,aSaveOldInstruction);

	// Release the lock

	Kern::SemaphoreSignal(*iLock);

	NKern::ThreadLeaveCS();

	return err;

	}

/**

Private member function which enables a previously set breakpoint, as per DoEnableBreak, but

does not serialise access.

@see DoEnableBreak

@param aEntry reference to a TBreakEntry datastructure describing the breakpoint to be re-enabled.

@param aSaveOldInstruction ETrue preserves the instruction at the breakpoint address, EFalse otherwise.

@return KErrNone if successful, otherwise one of the other system wide error codes.

*/

TInt D_RMD_Breakpoints::priv_DoEnableBreak(TBreakEntry &aEntry, TBool aSaveOldInstruction)

	{

	LOG_MSG("D_RMD_Breakpoints::DoEnableBreak()");

	TUint32 inst = BreakInst(aEntry.iMode);	

	TInt instSize = BreakSize(aEntry.iMode);

	if (instSize == 0 || inst == 0)

		{

		// not supported

		LOG_MSG("D_RMD_Breakpoints::priv_DoEnableBreak - unsupported breakpoint architecture");

		return KErrNotSupported;

		}

	TInt err = KErrNone;

	// Get thread id

	TUint64 threadId = aEntry.iId + (aEntry.iThreadSpecific ? 0 : 1);

	NKern::ThreadEnterCS();

	DThread* threadObj = DebugUtils::OpenThreadHandle(threadId);