15 <section id="GUID-8A6A93C2-AA57-4ABB-A6E0-64F34D12E05C"><title>Introduction</title><p>When |
15 <section id="GUID-8A6A93C2-AA57-4ABB-A6E0-64F34D12E05C"><title>Introduction</title><p>When |
16 a thread is executed on a single CPU system, there is an order to the read/write |
16 a thread is executed on a single CPU system, there is an order to the read/write |
17 operations to shared memory and I/O. Since read and write operations cannot |
17 operations to shared memory and I/O. Since read and write operations cannot |
18 occur at the same time, the integrity of the data is maintained.</p><fig id="GUID-86081A73-848E-49A4-A663-77D681DC6784"> |
18 occur at the same time, the integrity of the data is maintained.</p><fig id="GUID-86081A73-848E-49A4-A663-77D681DC6784"> |
19 <title>Shared Memory and I/O on a Single CPU System.</title> |
19 <title>Shared Memory and I/O on a Single CPU System.</title> |
20 <image href="GUID-CFD41A5A-2FE2-47FE-8369-08E3C73CB9A5_d0e17025_href.png" placement="inline"/> |
20 <image href="GUID-CFD41A5A-2FE2-47FE-8369-08E3C73CB9A5_d0e18136_href.png" placement="inline"/> |
21 </fig><p>Figure 1 shows how shared memory and I/O is handled on a single CPU |
21 </fig><p>Figure 1 shows how shared memory and I/O is handled on a single CPU |
22 system. The CPU switches between threads (this is called a context switch). |
22 system. The CPU switches between threads (this is called a context switch). |
23 Because only one thread can be executed at once, read and write operations |
23 Because only one thread can be executed at once, read and write operations |
24 to shared memory and I/O cannot occur at the same time. Hence the integrity |
24 to shared memory and I/O cannot occur at the same time. Hence the integrity |
25 of the data can be maintained.</p><fig id="GUID-38C5602A-15EF-4162-962B-932B13CC8377"> |
25 of the data can be maintained.</p><fig id="GUID-38C5602A-15EF-4162-962B-932B13CC8377"> |
26 <title>Shared Memory and I/O on a Multi CPU System.</title> |
26 <title>Shared Memory and I/O on a Multi CPU System.</title> |
27 <image href="GUID-4AB3C821-25B5-4B5B-BC20-C8FA42D69802_d0e17034_href.png" placement="inline"/> |
27 <image href="GUID-4AB3C821-25B5-4B5B-BC20-C8FA42D69802_d0e18145_href.png" placement="inline"/> |
28 </fig><p>Figure 2 shows how shared memory and I/O is handled on a multi CPU |
28 </fig><p>Figure 2 shows how shared memory and I/O is handled on a multi CPU |
29 system. In this system, it is possible that the read/write order will not |
29 system. In this system, it is possible that the read/write order will not |
30 be the one expected. This is due performance decisions made by the hardware |
30 be the one expected. This is due performance decisions made by the hardware |
31 used to interface memory to the rest of the system. Without some form of synchronisation |
31 used to interface memory to the rest of the system. Without some form of synchronisation |
32 mechanism in place, data corruption will occur.</p><p>To safeguard the integrity |
32 mechanism in place, data corruption will occur.</p><p>To safeguard the integrity |