--- a/Symbian3/PDK/Source/GUID-9D93F895-B975-4F2D-A2A3-817033EA5C12.dita	Fri Jul 02 12:51:36 2010 +0100
+++ b/Symbian3/PDK/Source/GUID-9D93F895-B975-4F2D-A2A3-817033EA5C12.dita	Fri Jul 16 17:23:46 2010 +0100
@@ -17,14 +17,14 @@
 operations to shared memory and I/O. Since read and write operations cannot
 occur at the same time, the integrity of the data is maintained.</p><fig id="GUID-86081A73-848E-49A4-A663-77D681DC6784">
 <title>Shared Memory and I/O on a Single CPU System.</title>
-<image href="GUID-CFD41A5A-2FE2-47FE-8369-08E3C73CB9A5_d0e17025_href.png" placement="inline"/>
+<image href="GUID-CFD41A5A-2FE2-47FE-8369-08E3C73CB9A5_d0e18136_href.png" placement="inline"/>
 </fig><p>Figure 1 shows how shared memory and I/O is handled on a single CPU
 system. The CPU switches between threads (this is called a context switch).
 Because only one thread can be executed at once, read and write operations
 to shared memory and I/O cannot occur at the same time. Hence the integrity
 of the data can be maintained.</p><fig id="GUID-38C5602A-15EF-4162-962B-932B13CC8377">
 <title>Shared Memory and I/O on a Multi CPU System.</title>
-<image href="GUID-4AB3C821-25B5-4B5B-BC20-C8FA42D69802_d0e17034_href.png" placement="inline"/>
+<image href="GUID-4AB3C821-25B5-4B5B-BC20-C8FA42D69802_d0e18145_href.png" placement="inline"/>
 </fig><p>Figure 2 shows how shared memory and I/O is handled on a multi CPU
 system. In this system, it is possible that the read/write order will not
 be the one expected. This is due performance decisions made by the hardware