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    12 <concept id="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1" xml:lang="en"><title>Remapping

    13 Cache Attributes and Access Permissions on ARMv6K and ARMv7 Platforms</title><shortdesc>Describes the behavior change brought about by remapping the cache

    14 attributes and the access permissions on the ARMv6K (ARM1176 & ARM11MPCore),

    15 ARMv7 (Cortex-8N), and future platforms.</shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>

    16 <ul>

    17 <li id="GUID-50632F8E-91A0-597C-8176-9FE352A8B9ED-GENID-1-2-1-9-1-8-1-16-1-3-1-1"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-B8EA1997-C922-5E98-A32E-A77D641D11BC-GENID-1-2-1-9-1-8-1-16-1-3-2">Reduced set access permissions</xref>  </p> <ul>

    18 <li id="GUID-9225B023-192F-5D04-92BA-0278768872FF-GENID-1-2-1-9-1-8-1-16-1-3-1-1-2-1"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-ABBF3854-B8B8-52A0-B3F6-1DF44A37194A-GENID-1-2-1-9-1-8-1-16-1-3-2-3">Affected kernel interface</xref>  </p> </li>

    19 </ul> </li>

    20 <li id="GUID-9851FDDF-8F0E-5AF1-AF7F-9C6273E9B0A8-GENID-1-2-1-9-1-8-1-16-1-3-1-2"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-E137E4E9-AADA-5BCE-8FC8-504ACD486394-GENID-1-2-1-9-1-8-1-16-1-3-3">Remapping cache attributes</xref>  </p> <ul>

    21 <li id="GUID-6B59981E-754F-5E9B-80F1-99D53D464B70-GENID-1-2-1-9-1-8-1-16-1-3-1-2-2-1"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-EDFD1FE0-ACD7-54B4-9633-0149E3FDF551-GENID-1-2-1-9-1-8-1-16-1-3-3-6">Types of memory supported</xref>  </p> </li>

    22 <li id="GUID-057483C0-F40F-503D-82D7-B2CC199AC9F9-GENID-1-2-1-9-1-8-1-16-1-3-1-2-2-2"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-548E9689-F7AB-5F61-A8AE-EA2043E70D34-GENID-1-2-1-9-1-8-1-16-1-3-3-11">Mapping existing memory types</xref>  </p> </li>

    23 <li id="GUID-4D7899BC-B6AD-5C9F-9135-7E37F2CFC21E-GENID-1-2-1-9-1-8-1-16-1-3-1-2-2-3"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-F90E6B00-6492-5471-975F-3C078046627A-GENID-1-2-1-9-1-8-1-16-1-3-3-14">Mapping ARMv6K or ARMv7 onto TMappingAttributes</xref>. </p> </li>

    24 </ul> </li>

    25 </ul>

    26 <section id="GUID-B8EA1997-C922-5E98-A32E-A77D641D11BC-GENID-1-2-1-9-1-8-1-16-1-3-2"><title>Reduced set

    27 access permissions</title> <p>The ARMv6-style page table reserves three bits

    28 in the page/directory table for access permission, so eight possible values

    29 are available. The use of four possible access permissions is sufficient.

    30 Therefore, removing the surplus access permissions frees up one page table

    31 bit that is used by Symbian platform internally. </p> <p id="GUID-ABBF3854-B8B8-52A0-B3F6-1DF44A37194A-GENID-1-2-1-9-1-8-1-16-1-3-2-3"><b>Affected kernel interface</b> </p> <p>The

    32 shadow pages kernel interface is valid on all platforms except for the emulator.

    33 On ARMv6 and previous platforms, shadow pages are created using access permission <codeph>PrivilegedRW/UserRO</codeph>,

    34 this is not supported by the limited set of encoding. Shadow pages are now

    35 mapped as <codeph>PrivilegedRO/UserRO</codeph>, instead. </p> <codeblock id="GUID-9197EF7D-F549-5144-A322-4C04CD80CFCC-GENID-1-2-1-9-1-8-1-16-1-3-2-5" xml:space="preserve">class Epoc

    36     {

    37 public:

    38     ...

    39     IMPORT_C static TInt AllocShadowPage(TLinAddr aRomAddr);

    40     IMPORT_C static TInt FreeShadowPage(TLinAddr aRomAddr);

    41     IMPORT_C static TInt FreezeShadowPage(TLinAddr aRomAddr);

    42     ...

    43     };</codeblock> <p>This represents a serious behaviour break in the kernel

    44 interface. A device driver (running on ARMv7) that creates a shadow page and

    45 then attempts to alter the content of the page now panics. </p> <p>This is

    46 a common use case for run-mode debuggers. However, a debugging interface is

    47 already provided, see <xref href="GUID-E91A8060-77E3-35F0-A945-7081406C79CE.dita"><apiname>DebugSupport</apiname></xref> in <filepath>...\memmodel\epoc\platform.h</filepath>,

    48 where breakpoints are managed internally by the kernel. Therefore, it is believed

    49 that a run-time debugger that uses the <codeph>CodeModifier</codeph> implementation

    50 in the kernel should not be affected by this change. </p> <p>After a shadow

    51 page is created using <xref href="GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680.dita#GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680/GUID-4FA10D18-3BA2-3307-B2E1-77C9CD8D2B6B"><apiname>Epoc::AllocShadowPage()</apiname></xref>, the kernel

    52 allows the device driver to alter its content using <xref href="GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680.dita#GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680/GUID-5B889008-BC18-3127-89EF-B8EAB0834190"><apiname>Epoc::CopyToShadowMemory()</apiname></xref>. </p> <p><note> <xref href="GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680.dita#GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680/GUID-EF014DA2-EE35-3DBD-A325-C5648AD27C36"><apiname>Epoc::FreezeShadowPage()</apiname></xref> is obsolete for platforms that use the reduced set of access permissions,

    53 as the shadow memory is always in a “frozen” state, because it can only be

    54 changed through the kernel interface.</note> </p> </section>

    55 <section id="GUID-E137E4E9-AADA-5BCE-8FC8-504ACD486394-GENID-1-2-1-9-1-8-1-16-1-3-3"><title>Remapping cache

    56 attributes </title> <p>ARMv6 architecture uses a large number of bits in the

    57 page table to describe all of the options for inner and outer cachability.

    58 No applications use all of these options simultaneously so a smaller number

    59 of configurable options has been implemented to meet the needs of the system. </p> <p>This

    60 alternative cache mapping allows up to eight different mappings in page tables.

    61 The Symbian platform kernel and device drivers do not need more

    62 than four or five different cache mappings. </p> <p>Cache mapping cannot be

    63 altered during run-time. It must be configured before the MMU is initialised. </p> <p>See

    64 the Bootstrap <xref href="GUID-5EB03086-A87D-5588-8927-7A7F8DB38366.dita">Port

    65 Implementation Tutorial</xref>. </p> <p id="GUID-EDFD1FE0-ACD7-54B4-9633-0149E3FDF551-GENID-1-2-1-9-1-8-1-16-1-3-3-6"><b>Types of memory supported</b> </p> <p>The

    66 kernel supports the following types of memory: </p> <table id="GUID-23FAD8A6-579B-5E3D-A705-A53BA304D529-GENID-1-2-1-9-1-8-1-16-1-3-3-8">

    67 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>

    68 <tbody>

    69 <row>

    70 <entry><p> <b>Memory type</b>  </p> </entry>

    71 <entry><p> <b>Description</b>  </p> </entry>

    72 </row>

    73 <row>

    74 <entry><p> <codeph>EMemAttStronglyOrdered</codeph>  </p> </entry>

    75 <entry><p>Writes are not combined. The order of memory accesses is preserved.

    76 Serves as a memory barrier, which means: </p> <ul>

    77 <li id="GUID-800FC168-69E5-5A89-B5A4-F34AF25E7F9E-GENID-1-2-1-9-1-8-1-16-1-3-3-8-1-3-2-2-2-1"><p>previous accesses to

    78 any type of memory must complete before accesses to strongly ordered memory

    79 start </p> </li>

    80 <li id="GUID-75C9FA7F-3BCC-50FE-B053-A48DEF46A2D2-GENID-1-2-1-9-1-8-1-16-1-3-3-8-1-3-2-2-2-2"><p>accesses to strongly

    81 ordered memory must complete before any further access to any type of memory

    82 takes place. </p> </li>

    83 </ul> <p>This type is used for hardware mapping. </p> </entry>

    84 </row>

    85 <row>

    86 <entry><p> <codeph>EMemAttDevice</codeph>  </p> </entry>

    87 <entry><p>Writes are not combined. The order of memory accesses is preserved.

    88 This type is used for hardware mapping. </p> </entry>

    89 </row>

    90 <row>

    91 <entry><p> <codeph>EMemAttNormalUncached</codeph>  </p> </entry>

    92 <entry><p>Non cacheable memory: The order of accesses is not preserved. Writes

    93 may be combined. For example, this is used for video memory. </p> </entry>

    94 </row>

    95 <row>

    96 <entry><p> <codeph>EMemAttNormalCached</codeph>  </p> </entry>

    97 <entry><p>Write-back read/write allocate cached memory, inner and outer. Used

    98 for “ordinary” memory. </p> </entry>

    99 </row>

   100 </tbody>

   101 </tgroup>

   102 </table> <p> <note> Device memory and normal memory can be set as shared or

   103 non-shared, strongly ordered accesses are assumed to be shared. </note></p> <p>The

   104 complete set of memory types supported by Symbian platform are represented

   105 by the values of the <xref href="GUID-7CB34E6F-CBF7-3F04-8CB1-2D6C29C73992.dita"><apiname>TMemoryType</apiname></xref> enum. </p> <p id="GUID-548E9689-F7AB-5F61-A8AE-EA2043E70D34-GENID-1-2-1-9-1-8-1-16-1-3-3-11"><b>Mapping existing memory

   106 types</b> </p> <p>The <xref href="GUID-1CE7A793-6313-372C-AC1A-6D3F6C6F5042.dita"><apiname>TMappingAttributes</apiname></xref> constants allow

   107 the cache attributes to be manipulated. On remapped platforms, these map into <xref href="GUID-7CB34E6F-CBF7-3F04-8CB1-2D6C29C73992.dita"><apiname>TMemoryType</apiname></xref> as

   108 follows: </p> <table id="GUID-24B0E1CD-67D9-5FAD-8984-9E202975F7EA-GENID-1-2-1-9-1-8-1-16-1-3-3-13">

   109 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>

   110 <tbody>

   111 <row>

   112 <entry><p> <b> Memory type described by TMappingAttributes</b>  </p> </entry>

   113 <entry><p> <b>Memory type</b>  </p> </entry>

   114 </row>

   115 <row>

   116 <entry><p> <xref href="GUID-27DA5FEE-8F76-3D9E-8726-FA5CB808680A.dita"><apiname>EMapAttrFullyBlocking</apiname></xref>  </p> </entry>

   117 <entry><p> <xref href="GUID-F6F245E9-9DB7-3BEF-8F58-9A7F8E0F5D59.dita"><apiname>EMemAttStronglyOrdered</apiname></xref>  </p> </entry>

   118 </row>

   119 <row>

   120 <entry><p> <xref href="GUID-B8ACFB0F-B457-358F-96EF-94BFBA6FE4A5.dita"><apiname>EMapAttrBufferedNC</apiname></xref>  </p> <p> <xref href="GUID-468C3800-7AEE-3219-9EBB-9C52971B3E0E.dita"><apiname>EMapAttrBufferedC</apiname></xref>  </p> </entry>

   121 <entry><p> <xref href="GUID-922F4FB9-57C0-31BF-ADFB-CC6B8376A39B.dita"><apiname>EMemAttDevice</apiname></xref>  </p> </entry>

   122 </row>

   123 <row>

   124 <entry><p> <xref href="GUID-AE44E6A7-5CD2-31D9-A701-188B26CDEBB0.dita"><apiname>EMapAttrL1Uncached</apiname></xref>  </p> <p> <xref href="GUID-5ADA8BB4-A7B9-3347-B9A8-B50BE92F66BC.dita"><apiname>EMapAttrCachedWTRA</apiname></xref>  </p> <p> <xref href="GUID-54A8E3DA-996D-3317-A129-9AD12201E3C1.dita"><apiname>EMapAttrCachedWTWA</apiname></xref>  </p> </entry>

   125 <entry><p> <xref href="GUID-FD4404AF-192C-3D20-A4BC-AE1181A14E43.dita"><apiname> EMemAttNormalUncached</apiname></xref>  </p> </entry>

   126 </row>

   127 <row>

   128 <entry><p> <xref href="GUID-FA3DD609-9C88-38C9-8719-4AB28B8E84EA.dita"><apiname>EMapAttrCachedWBRA</apiname></xref>  </p> <p> <xref href="GUID-9B211A60-6B45-31D5-A096-2B7944E651A0.dita"><apiname>EMapAttrCachedWBWA</apiname></xref>  </p> <p> <xref href="GUID-BB620F1F-FD18-3FCB-B1FC-7C3555F471B6.dita"><apiname>EMapAttrL1CachedMax</apiname></xref>  </p> <p> <xref href="GUID-72222BDB-E369-3D03-B3EE-A04B125EB2A3.dita"><apiname>EmapAttrCachedMax</apiname></xref>  </p> </entry>

   129 <entry><p> <xref href="GUID-2191E3C7-5F22-38D1-BB16-BD78B44AE7AA.dita"><apiname>EMemAttNormalCached</apiname></xref>  </p> </entry>

   130 </row>

   131 <row>

   132 <entry><p> <xref href="GUID-A647726F-5569-3EAA-9E24-70FBEAF6F94B.dita"><apiname>EMapAttrAltCacheWTRA</apiname></xref>  </p> <p> <xref href="GUID-23C6459E-65F4-317E-B22D-6AB91A2F3462.dita"><apiname>EMapAttrAltCacheWTWA</apiname></xref>  </p> <p> <xref href="GUID-4F97DE5E-3031-3AB5-9646-996DD1EB9C15.dita"><apiname>EMapAttrAltCacheWBRA</apiname></xref>  </p> <p> <xref href="GUID-D34AE0F7-21A3-3B8C-B768-1A7840257780.dita"><apiname>EMapAttrAltCacheWBWA</apiname></xref>  </p> </entry>

   133 <entry><p>Return error </p> </entry>

   134 </row>

   135 <row>

   136 <entry><p> <xref href="GUID-1E6DD28F-F53C-34F0-B5A1-88263389ACF7.dita"><apiname>EMapAttrL2CachedWTRA</apiname></xref>  </p> <p> <xref href="GUID-1695C568-36F8-3860-8253-D25CC6F2100E.dita"><apiname>EMapAttrL2CachedWTWA</apiname></xref>  </p> <p> <xref href="GUID-E82A15FB-6A92-388F-A6F2-AA0DBAC720E8.dita"><apiname>EMapAttrL2CachedWBRA</apiname></xref>  </p> <p> <xref href="GUID-CAD3DE19-9508-319E-9C61-1E7910D30AC9.dita"><apiname>EMapAttrL2CachedWBWA</apiname></xref>  </p> <p> <xref href="GUID-CE3B3839-E9B5-3B8F-AB41-3F589CD3347C.dita"><apiname>EMapAttrL2CachedMax</apiname></xref>  </p> </entry>

   137 <entry><p>Takes no effect. Only the inner cache description matters. </p> <p>This

   138 policy is already in place on ARMv5 platforms with L210, where the page table

   139 does not support a separate description of the inner and outer cache attributes. </p> </entry>

   140 </row>

   141 </tbody>

   142 </tgroup>

   143 </table> <p id="GUID-F90E6B00-6492-5471-975F-3C078046627A-GENID-1-2-1-9-1-8-1-16-1-3-3-14"><b> Mapping ARMv6K or ARMv7

   144 onto TMappingAttributes</b> </p> <p>To describe memory on ARMv6K or ARMv7

   145 using the original <xref href="GUID-1CE7A793-6313-372C-AC1A-6D3F6C6F5042.dita"><apiname>TMappingAttributes</apiname></xref> bit mask, the device

   146 driver should use the following values: </p> <table id="GUID-C5D9F8B3-670A-5595-BE7A-288E34E077ED-GENID-1-2-1-9-1-8-1-16-1-3-3-16">

   147 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>

   148 <tbody>

   149 <row>

   150 <entry><p> <b>ARMv6K/v7 memory type TMemoryType</b>  </p> </entry>

   151 <entry><p> <b>TMappingAttributes mask to use</b>  </p> </entry>

   152 </row>

   153 <row>

   154 <entry><p> <codeph>EMemAttStronglyOrdered</codeph>  </p> </entry>

   155 <entry><p> <codeph>EMapAttrFullyBlocking</codeph>  </p> </entry>

   156 </row>

   157 <row>

   158 <entry><p> <codeph>EMemAttDevice</codeph>  </p> </entry>

   159 <entry><p> <codeph>EMapAttrBufferedNC</codeph>  </p> </entry>

   160 </row>

   161 <row>

   162 <entry><p> <codeph>EMemAttNormalUncached</codeph>  </p> </entry>

   163 <entry><p> <codeph>EMapAttrL1Uncached</codeph>  </p> </entry>

   164 </row>

   165 <row>

   166 <entry><p> <codeph>EMemAttNormalCached</codeph>  </p> </entry>

   167 <entry><p> <codeph>EmapAttrCachedMax</codeph>  </p> </entry>

   168 </row>

   169 </tbody>

   170 </tgroup>

   171 </table> </section>

   172 </conbody></concept>