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<concept id="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1" xml:lang="en"><title>Remapping
Cache Attributes and Access Permissions on ARMv6K and ARMv7 Platforms</title><shortdesc>Describes the behavior change brought about by remapping the cache
attributes and the access permissions on the ARMv6K (ARM1176 &amp; ARM11MPCore),
ARMv7 (Cortex-8N), and future platforms.</shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>
<ul>
<li id="GUID-50632F8E-91A0-597C-8176-9FE352A8B9ED-GENID-1-2-1-9-1-8-1-16-1-3-1-1"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-B8EA1997-C922-5E98-A32E-A77D641D11BC-GENID-1-2-1-9-1-8-1-16-1-3-2">Reduced set access permissions</xref>  </p> <ul>
<li id="GUID-9225B023-192F-5D04-92BA-0278768872FF-GENID-1-2-1-9-1-8-1-16-1-3-1-1-2-1"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-ABBF3854-B8B8-52A0-B3F6-1DF44A37194A-GENID-1-2-1-9-1-8-1-16-1-3-2-3">Affected kernel interface</xref>  </p> </li>
</ul> </li>
<li id="GUID-9851FDDF-8F0E-5AF1-AF7F-9C6273E9B0A8-GENID-1-2-1-9-1-8-1-16-1-3-1-2"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-E137E4E9-AADA-5BCE-8FC8-504ACD486394-GENID-1-2-1-9-1-8-1-16-1-3-3">Remapping cache attributes</xref>  </p> <ul>
<li id="GUID-6B59981E-754F-5E9B-80F1-99D53D464B70-GENID-1-2-1-9-1-8-1-16-1-3-1-2-2-1"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-EDFD1FE0-ACD7-54B4-9633-0149E3FDF551-GENID-1-2-1-9-1-8-1-16-1-3-3-6">Types of memory supported</xref>  </p> </li>
<li id="GUID-057483C0-F40F-503D-82D7-B2CC199AC9F9-GENID-1-2-1-9-1-8-1-16-1-3-1-2-2-2"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-548E9689-F7AB-5F61-A8AE-EA2043E70D34-GENID-1-2-1-9-1-8-1-16-1-3-3-11">Mapping existing memory types</xref>  </p> </li>
<li id="GUID-4D7899BC-B6AD-5C9F-9135-7E37F2CFC21E-GENID-1-2-1-9-1-8-1-16-1-3-1-2-2-3"><p> <xref href="GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1.dita#GUID-EC2D5CA5-538C-5375-B00D-3107CD87CFFC-GENID-1-2-1-9-1-8-1-16-1/GUID-F90E6B00-6492-5471-975F-3C078046627A-GENID-1-2-1-9-1-8-1-16-1-3-3-14">Mapping ARMv6K or ARMv7 onto TMappingAttributes</xref>. </p> </li>
</ul> </li>
</ul>
<section id="GUID-B8EA1997-C922-5E98-A32E-A77D641D11BC-GENID-1-2-1-9-1-8-1-16-1-3-2"><title>Reduced set
access permissions</title> <p>The ARMv6-style page table reserves three bits
in the page/directory table for access permission, so eight possible values
are available. The use of four possible access permissions is sufficient.
Therefore, removing the surplus access permissions frees up one page table
bit that is used by Symbian platform internally. </p> <p id="GUID-ABBF3854-B8B8-52A0-B3F6-1DF44A37194A-GENID-1-2-1-9-1-8-1-16-1-3-2-3"><b>Affected kernel interface</b> </p> <p>The
shadow pages kernel interface is valid on all platforms except for the emulator.
On ARMv6 and previous platforms, shadow pages are created using access permission <codeph>PrivilegedRW/UserRO</codeph>,
this is not supported by the limited set of encoding. Shadow pages are now
mapped as <codeph>PrivilegedRO/UserRO</codeph>, instead. </p> <codeblock id="GUID-9197EF7D-F549-5144-A322-4C04CD80CFCC-GENID-1-2-1-9-1-8-1-16-1-3-2-5" xml:space="preserve">class Epoc
    {
public:
    ...
    IMPORT_C static TInt AllocShadowPage(TLinAddr aRomAddr);
    IMPORT_C static TInt FreeShadowPage(TLinAddr aRomAddr);
    IMPORT_C static TInt FreezeShadowPage(TLinAddr aRomAddr);
    ...
    };</codeblock> <p>This represents a serious behaviour break in the kernel
interface. A device driver (running on ARMv7) that creates a shadow page and
then attempts to alter the content of the page now panics. </p> <p>This is
a common use case for run-mode debuggers. However, a debugging interface is
already provided, see <xref href="GUID-E91A8060-77E3-35F0-A945-7081406C79CE.dita"><apiname>DebugSupport</apiname></xref> in <filepath>...\memmodel\epoc\platform.h</filepath>,
where breakpoints are managed internally by the kernel. Therefore, it is believed
that a run-time debugger that uses the <codeph>CodeModifier</codeph> implementation
in the kernel should not be affected by this change. </p> <p>After a shadow
page is created using <xref href="GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680.dita#GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680/GUID-4FA10D18-3BA2-3307-B2E1-77C9CD8D2B6B"><apiname>Epoc::AllocShadowPage()</apiname></xref>, the kernel
allows the device driver to alter its content using <xref href="GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680.dita#GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680/GUID-5B889008-BC18-3127-89EF-B8EAB0834190"><apiname>Epoc::CopyToShadowMemory()</apiname></xref>. </p> <p><note> <xref href="GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680.dita#GUID-3DC7B5F2-512E-3FF3-BC08-945DDE2AE680/GUID-EF014DA2-EE35-3DBD-A325-C5648AD27C36"><apiname>Epoc::FreezeShadowPage()</apiname></xref> is obsolete for platforms that use the reduced set of access permissions,
as the shadow memory is always in a “frozen” state, because it can only be
changed through the kernel interface.</note> </p> </section>
<section id="GUID-E137E4E9-AADA-5BCE-8FC8-504ACD486394-GENID-1-2-1-9-1-8-1-16-1-3-3"><title>Remapping cache
attributes </title> <p>ARMv6 architecture uses a large number of bits in the
page table to describe all of the options for inner and outer cachability.
No applications use all of these options simultaneously so a smaller number
of configurable options has been implemented to meet the needs of the system. </p> <p>This
alternative cache mapping allows up to eight different mappings in page tables.
The Symbian platform kernel and device drivers do not need more
than four or five different cache mappings. </p> <p>Cache mapping cannot be
altered during run-time. It must be configured before the MMU is initialised. </p> <p>See
the Bootstrap <xref href="GUID-5EB03086-A87D-5588-8927-7A7F8DB38366.dita">Port
Implementation Tutorial</xref>. </p> <p id="GUID-EDFD1FE0-ACD7-54B4-9633-0149E3FDF551-GENID-1-2-1-9-1-8-1-16-1-3-3-6"><b>Types of memory supported</b> </p> <p>The
kernel supports the following types of memory: </p> <table id="GUID-23FAD8A6-579B-5E3D-A705-A53BA304D529-GENID-1-2-1-9-1-8-1-16-1-3-3-8">
<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>
<tbody>
<row>
<entry><p> <b>Memory type</b>  </p> </entry>
<entry><p> <b>Description</b>  </p> </entry>
</row>
<row>
<entry><p> <codeph>EMemAttStronglyOrdered</codeph>  </p> </entry>
<entry><p>Writes are not combined. The order of memory accesses is preserved.
Serves as a memory barrier, which means: </p> <ul>
<li id="GUID-800FC168-69E5-5A89-B5A4-F34AF25E7F9E-GENID-1-2-1-9-1-8-1-16-1-3-3-8-1-3-2-2-2-1"><p>previous accesses to
any type of memory must complete before accesses to strongly ordered memory
start </p> </li>
<li id="GUID-75C9FA7F-3BCC-50FE-B053-A48DEF46A2D2-GENID-1-2-1-9-1-8-1-16-1-3-3-8-1-3-2-2-2-2"><p>accesses to strongly
ordered memory must complete before any further access to any type of memory
takes place. </p> </li>
</ul> <p>This type is used for hardware mapping. </p> </entry>
</row>
<row>
<entry><p> <codeph>EMemAttDevice</codeph>  </p> </entry>
<entry><p>Writes are not combined. The order of memory accesses is preserved.
This type is used for hardware mapping. </p> </entry>
</row>
<row>
<entry><p> <codeph>EMemAttNormalUncached</codeph>  </p> </entry>
<entry><p>Non cacheable memory: The order of accesses is not preserved. Writes
may be combined. For example, this is used for video memory. </p> </entry>
</row>
<row>
<entry><p> <codeph>EMemAttNormalCached</codeph>  </p> </entry>
<entry><p>Write-back read/write allocate cached memory, inner and outer. Used
for “ordinary” memory. </p> </entry>
</row>
</tbody>
</tgroup>
</table> <p> <note> Device memory and normal memory can be set as shared or
non-shared, strongly ordered accesses are assumed to be shared. </note></p> <p>The
complete set of memory types supported by Symbian platform are represented
by the values of the <xref href="GUID-7CB34E6F-CBF7-3F04-8CB1-2D6C29C73992.dita"><apiname>TMemoryType</apiname></xref> enum. </p> <p id="GUID-548E9689-F7AB-5F61-A8AE-EA2043E70D34-GENID-1-2-1-9-1-8-1-16-1-3-3-11"><b>Mapping existing memory
types</b> </p> <p>The <xref href="GUID-1CE7A793-6313-372C-AC1A-6D3F6C6F5042.dita"><apiname>TMappingAttributes</apiname></xref> constants allow
the cache attributes to be manipulated. On remapped platforms, these map into <xref href="GUID-7CB34E6F-CBF7-3F04-8CB1-2D6C29C73992.dita"><apiname>TMemoryType</apiname></xref> as
follows: </p> <table id="GUID-24B0E1CD-67D9-5FAD-8984-9E202975F7EA-GENID-1-2-1-9-1-8-1-16-1-3-3-13">
<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>
<tbody>
<row>
<entry><p> <b> Memory type described by TMappingAttributes</b>  </p> </entry>
<entry><p> <b>Memory type</b>  </p> </entry>
</row>
<row>
<entry><p> <xref href="GUID-27DA5FEE-8F76-3D9E-8726-FA5CB808680A.dita"><apiname>EMapAttrFullyBlocking</apiname></xref>  </p> </entry>
<entry><p> <xref href="GUID-F6F245E9-9DB7-3BEF-8F58-9A7F8E0F5D59.dita"><apiname>EMemAttStronglyOrdered</apiname></xref>  </p> </entry>
</row>
<row>
<entry><p> <xref href="GUID-B8ACFB0F-B457-358F-96EF-94BFBA6FE4A5.dita"><apiname>EMapAttrBufferedNC</apiname></xref>  </p> <p> <xref href="GUID-468C3800-7AEE-3219-9EBB-9C52971B3E0E.dita"><apiname>EMapAttrBufferedC</apiname></xref>  </p> </entry>
<entry><p> <xref href="GUID-922F4FB9-57C0-31BF-ADFB-CC6B8376A39B.dita"><apiname>EMemAttDevice</apiname></xref>  </p> </entry>
</row>
<row>
<entry><p> <xref href="GUID-AE44E6A7-5CD2-31D9-A701-188B26CDEBB0.dita"><apiname>EMapAttrL1Uncached</apiname></xref>  </p> <p> <xref href="GUID-5ADA8BB4-A7B9-3347-B9A8-B50BE92F66BC.dita"><apiname>EMapAttrCachedWTRA</apiname></xref>  </p> <p> <xref href="GUID-54A8E3DA-996D-3317-A129-9AD12201E3C1.dita"><apiname>EMapAttrCachedWTWA</apiname></xref>  </p> </entry>
<entry><p> <xref href="GUID-FD4404AF-192C-3D20-A4BC-AE1181A14E43.dita"><apiname> EMemAttNormalUncached</apiname></xref>  </p> </entry>
</row>
<row>
<entry><p> <xref href="GUID-FA3DD609-9C88-38C9-8719-4AB28B8E84EA.dita"><apiname>EMapAttrCachedWBRA</apiname></xref>  </p> <p> <xref href="GUID-9B211A60-6B45-31D5-A096-2B7944E651A0.dita"><apiname>EMapAttrCachedWBWA</apiname></xref>  </p> <p> <xref href="GUID-BB620F1F-FD18-3FCB-B1FC-7C3555F471B6.dita"><apiname>EMapAttrL1CachedMax</apiname></xref>  </p> <p> <xref href="GUID-72222BDB-E369-3D03-B3EE-A04B125EB2A3.dita"><apiname>EmapAttrCachedMax</apiname></xref>  </p> </entry>
<entry><p> <xref href="GUID-2191E3C7-5F22-38D1-BB16-BD78B44AE7AA.dita"><apiname>EMemAttNormalCached</apiname></xref>  </p> </entry>
</row>
<row>
<entry><p> <xref href="GUID-A647726F-5569-3EAA-9E24-70FBEAF6F94B.dita"><apiname>EMapAttrAltCacheWTRA</apiname></xref>  </p> <p> <xref href="GUID-23C6459E-65F4-317E-B22D-6AB91A2F3462.dita"><apiname>EMapAttrAltCacheWTWA</apiname></xref>  </p> <p> <xref href="GUID-4F97DE5E-3031-3AB5-9646-996DD1EB9C15.dita"><apiname>EMapAttrAltCacheWBRA</apiname></xref>  </p> <p> <xref href="GUID-D34AE0F7-21A3-3B8C-B768-1A7840257780.dita"><apiname>EMapAttrAltCacheWBWA</apiname></xref>  </p> </entry>
<entry><p>Return error </p> </entry>
</row>
<row>
<entry><p> <xref href="GUID-1E6DD28F-F53C-34F0-B5A1-88263389ACF7.dita"><apiname>EMapAttrL2CachedWTRA</apiname></xref>  </p> <p> <xref href="GUID-1695C568-36F8-3860-8253-D25CC6F2100E.dita"><apiname>EMapAttrL2CachedWTWA</apiname></xref>  </p> <p> <xref href="GUID-E82A15FB-6A92-388F-A6F2-AA0DBAC720E8.dita"><apiname>EMapAttrL2CachedWBRA</apiname></xref>  </p> <p> <xref href="GUID-CAD3DE19-9508-319E-9C61-1E7910D30AC9.dita"><apiname>EMapAttrL2CachedWBWA</apiname></xref>  </p> <p> <xref href="GUID-CE3B3839-E9B5-3B8F-AB41-3F589CD3347C.dita"><apiname>EMapAttrL2CachedMax</apiname></xref>  </p> </entry>
<entry><p>Takes no effect. Only the inner cache description matters. </p> <p>This
policy is already in place on ARMv5 platforms with L210, where the page table
does not support a separate description of the inner and outer cache attributes. </p> </entry>
</row>
</tbody>
</tgroup>
</table> <p id="GUID-F90E6B00-6492-5471-975F-3C078046627A-GENID-1-2-1-9-1-8-1-16-1-3-3-14"><b> Mapping ARMv6K or ARMv7
onto TMappingAttributes</b> </p> <p>To describe memory on ARMv6K or ARMv7
using the original <xref href="GUID-1CE7A793-6313-372C-AC1A-6D3F6C6F5042.dita"><apiname>TMappingAttributes</apiname></xref> bit mask, the device
driver should use the following values: </p> <table id="GUID-C5D9F8B3-670A-5595-BE7A-288E34E077ED-GENID-1-2-1-9-1-8-1-16-1-3-3-16">
<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>
<tbody>
<row>
<entry><p> <b>ARMv6K/v7 memory type TMemoryType</b>  </p> </entry>
<entry><p> <b>TMappingAttributes mask to use</b>  </p> </entry>
</row>
<row>
<entry><p> <codeph>EMemAttStronglyOrdered</codeph>  </p> </entry>
<entry><p> <codeph>EMapAttrFullyBlocking</codeph>  </p> </entry>
</row>
<row>
<entry><p> <codeph>EMemAttDevice</codeph>  </p> </entry>
<entry><p> <codeph>EMapAttrBufferedNC</codeph>  </p> </entry>
</row>
<row>
<entry><p> <codeph>EMemAttNormalUncached</codeph>  </p> </entry>
<entry><p> <codeph>EMapAttrL1Uncached</codeph>  </p> </entry>
</row>
<row>
<entry><p> <codeph>EMemAttNormalCached</codeph>  </p> </entry>
<entry><p> <codeph>EmapAttrCachedMax</codeph>  </p> </entry>
</row>
</tbody>
</tgroup>
</table> </section>
</conbody></concept>