/*

 * These files from binutils are concatenated:

 * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c

 */

/* include/opcode/sparc.h */

/* Definitions for opcode table for the sparc.

   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,

   2003, 2005 Free Software Foundation, Inc.

   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and

   the GNU Binutils.

   GAS/GDB is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 2, or (at your option)

   any later version.

   GAS/GDB is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with GAS or GDB; see the file COPYING. If not, write to

   the Free Software Foundation, 51 Franklin Street - Fifth Floor,

   Boston, MA 02110-1301, USA.  */

#include <stdlib.h>

#include "dis-asm.h"

/* The SPARC opcode table (and other related data) is defined in

   the opcodes library in sparc-opc.c.  If you change anything here, make

   sure you fix up that file, and vice versa.  */

 /* FIXME-someday: perhaps the ,a's and such should be embedded in the

    instruction's name rather than the args.  This would make gas faster, pinsn

    slower, but would mess up some macros a bit.  xoxorich. */

/* List of instruction sets variations.

   These values are such that each element is either a superset of a

   preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P

   returns non-zero.

   The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.

   Don't change this without updating sparc-opc.c.  */

enum sparc_opcode_arch_val

{

  SPARC_OPCODE_ARCH_V6 = 0,

  SPARC_OPCODE_ARCH_V7,

  SPARC_OPCODE_ARCH_V8,

  SPARC_OPCODE_ARCH_SPARCLET,

  SPARC_OPCODE_ARCH_SPARCLITE,

  /* V9 variants must appear last.  */

  SPARC_OPCODE_ARCH_V9,

  SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions.  */

  SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions.  */

  SPARC_OPCODE_ARCH_BAD  /* Error return from sparc_opcode_lookup_arch.  */

};

/* The highest architecture in the table.  */

#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)

/* Given an enum sparc_opcode_arch_val, return the bitmask to use in

   insn encoding/decoding.  */

#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))

/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */

#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)

/* Table of cpu variants.  */

typedef struct sparc_opcode_arch

{

  const char *name;

  /* Mask of sparc_opcode_arch_val's supported.

     EG: For v7 this would be

     (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).

     These are short's because sparc_opcode.architecture is.  */

  short supported;

} sparc_opcode_arch;

static const struct sparc_opcode_arch sparc_opcode_archs[];

/* Return the bitmask of supported architectures for ARCH.  */

#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)

/* Non-zero if ARCH1 conflicts with ARCH2.

   IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */

#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \

 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \

   != SPARC_OPCODE_SUPPORTED (ARCH1)) \

  && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \

     != SPARC_OPCODE_SUPPORTED (ARCH2)))

/* Structure of an opcode table entry.  */

typedef struct sparc_opcode

{

  const char *name;

  unsigned long match;  /* Bits that must be set.  */

  unsigned long lose;   /* Bits that must not be set.  */

  const char *args;

  /* This was called "delayed" in versions before the flags.  */

  char flags;

  short architecture;   /* Bitmask of sparc_opcode_arch_val's.  */

} sparc_opcode;

#define F_DELAYED       1       /* Delayed branch.  */

#define F_ALIAS         2       /* Alias for a "real" instruction.  */

#define F_UNBR          4       /* Unconditional branch.  */

#define F_CONDBR        8       /* Conditional branch.  */

#define F_JSR           16      /* Subroutine call.  */

#define F_FLOAT         32      /* Floating point instruction (not a branch).  */

#define F_FBR           64      /* Floating point branch.  */

/* FIXME: Add F_ANACHRONISTIC flag for v9.  */

/* All sparc opcodes are 32 bits, except for the `set' instruction (really a

   macro), which is 64 bits. It is handled as a special case.

   The match component is a mask saying which bits must match a particular

   opcode in order for an instruction to be an instance of that opcode.

   The args component is a string containing one character for each operand of the

   instruction.

   Kinds of operands:

        #       Number used by optimizer.       It is ignored.

        1       rs1 register.

        2       rs2 register.

        d       rd register.

        e       frs1 floating point register.

        v       frs1 floating point register (double/even).

        V       frs1 floating point register (quad/multiple of 4).

        f       frs2 floating point register.

        B       frs2 floating point register (double/even).

        R       frs2 floating point register (quad/multiple of 4).

        g       frsd floating point register.

        H       frsd floating point register (double/even).

        J       frsd floating point register (quad/multiple of 4).

        b       crs1 coprocessor register

        c       crs2 coprocessor register

        D       crsd coprocessor register

        m       alternate space register (asr) in rd

        M       alternate space register (asr) in rs1

        h       22 high bits.

        X       5 bit unsigned immediate

        Y       6 bit unsigned immediate

        3       SIAM mode (3 bits). (v9b)

        K       MEMBAR mask (7 bits). (v9)

        j       10 bit Immediate. (v9)

        I       11 bit Immediate. (v9)

        i       13 bit Immediate.

        n       22 bit immediate.

        k       2+14 bit PC relative immediate. (v9)

        G       19 bit PC relative immediate. (v9)

        l       22 bit PC relative immediate.

        L       30 bit PC relative immediate.

        a       Annul.  The annul bit is set.

        A       Alternate address space. Stored as 8 bits.

        C       Coprocessor state register.

        F       floating point state register.

        p       Processor state register.

        N       Branch predict clear ",pn" (v9)

        T       Branch predict set ",pt" (v9)

        z       %icc. (v9)

        Z       %xcc. (v9)

        q       Floating point queue.

        r       Single register that is both rs1 and rd.

        O       Single register that is both rs2 and rd.

        Q       Coprocessor queue.

        S       Special case.

        t       Trap base register.

        w       Window invalid mask register.

        y       Y register.

        u       sparclet coprocessor registers in rd position

        U       sparclet coprocessor registers in rs1 position

        E       %ccr. (v9)

        s       %fprs. (v9)

        P       %pc.  (v9)

        W       %tick.  (v9)

        o       %asi. (v9)

        6       %fcc0. (v9)

        7       %fcc1. (v9)

        8       %fcc2. (v9)

        9       %fcc3. (v9)

        !       Privileged Register in rd (v9)

        ?       Privileged Register in rs1 (v9)

        *       Prefetch function constant. (v9)

        x       OPF field (v9 impdep).

        0       32/64 bit immediate for set or setx (v9) insns

        _       Ancillary state register in rd (v9a)

        /       Ancillary state register in rs1 (v9a)

  The following chars are unused: (note: ,[] are used as punctuation)

  [45].  */

#define OP2(x)          (((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */

#define OP3(x)          (((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */

#define OP(x)           ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns.  */

#define OPF(x)          (((x) & 0x1ff) << 5) /* Opf field of float insns.  */

#define OPF_LOW5(x)     OPF ((x) & 0x1f)     /* V9.  */

#define F3F(x, y, z)    (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */

#define F3I(x)          (((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */

#define F2(x, y)        (OP (x) | OP2(y))    /* Format 2 insns.  */

#define F3(x, y, z)     (OP (x) | OP3(y) | F3I(z)) /* Format3 insns.  */

#define F1(x)           (OP (x))

#define DISP30(x)       ((x) & 0x3fffffff)

#define ASI(x)          (((x) & 0xff) << 5)  /* Asi field of format3 insns.  */

#define RS2(x)          ((x) & 0x1f)         /* Rs2 field.  */

#define SIMM13(x)       ((x) & 0x1fff)       /* Simm13 field.  */

#define RD(x)           (((x) & 0x1f) << 25) /* Destination register field.  */

#define RS1(x)          (((x) & 0x1f) << 14) /* Rs1 field.  */

#define ASI_RS2(x)      (SIMM13 (x))

#define MEMBAR(x)       ((x) & 0x7f)

#define SLCPOP(x)       (((x) & 0x7f) << 6)  /* Sparclet cpop.  */

#define ANNUL   (1 << 29)

#define BPRED   (1 << 19)       /* V9.  */

#define IMMED   F3I (1)

#define RD_G0   RD (~0)

#define RS1_G0  RS1 (~0)

#define RS2_G0  RS2 (~0)

static const struct sparc_opcode sparc_opcodes[];

static const int sparc_num_opcodes;

static const char *sparc_decode_asi_v8 (int);

static const char *sparc_decode_asi_v9 (int);

static const char *sparc_decode_membar (int);

static const char *sparc_decode_prefetch (int);

static const char *sparc_decode_sparclet_cpreg (int);

/* Local Variables:

   fill-column: 131

   comment-column: 0

   End: */

/* opcodes/sparc-opc.c */

/* Table of opcodes for the sparc.

   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,

   2000, 2002, 2004, 2005

   Free Software Foundation, Inc.

   This file is part of the BFD library.

   BFD is free software; you can redistribute it and/or modify it under

   the terms of the GNU General Public License as published by the Free

   Software Foundation; either version 2, or (at your option) any later

   version.

   BFD is distributed in the hope that it will be useful, but WITHOUT ANY

   WARRANTY; without even the implied warranty of MERCHANTABILITY or

   FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

   for more details.

   You should have received a copy of the GNU General Public License

   along with this software; see the file COPYING.  If not, write to

   the Free Software Foundation, 51 Franklin Street - Fifth Floor,

   Boston, MA 02110-1301, USA.  */

/* FIXME-someday: perhaps the ,a's and such should be embedded in the

   instruction's name rather than the args.  This would make gas faster, pinsn

   slower, but would mess up some macros a bit.  xoxorich. */

/* Some defines to make life easy.  */

#define MASK_V6         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)

#define MASK_V7         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)

#define MASK_V8         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)

#define MASK_SPARCLET   SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)

#define MASK_SPARCLITE  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)

#define MASK_V9         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)

#define MASK_V9A        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)

#define MASK_V9B        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)

/* Bit masks of architectures supporting the insn.  */

#define v6              (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \

                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)

/* v6 insns not supported on the sparclet.  */

#define v6notlet        (MASK_V6 | MASK_V7 | MASK_V8 \

                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)

#define v7              (MASK_V7 | MASK_V8 | MASK_SPARCLET \

                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)

/* Although not all insns are implemented in hardware, sparclite is defined

   to be a superset of v8.  Unimplemented insns trap and are then theoretically

   implemented in software.

   It's not clear that the same is true for sparclet, although the docs

   suggest it is.  Rather than complicating things, the sparclet assembler

   recognizes all v8 insns.  */

#define v8              (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \

                         | MASK_V9 | MASK_V9A | MASK_V9B)

#define sparclet        (MASK_SPARCLET)

#define sparclite       (MASK_SPARCLITE)

#define v9              (MASK_V9 | MASK_V9A | MASK_V9B)

#define v9a             (MASK_V9A | MASK_V9B)

#define v9b             (MASK_V9B)

/* v6 insns not supported by v9.  */

#define v6notv9         (MASK_V6 | MASK_V7 | MASK_V8 \

                         | MASK_SPARCLET | MASK_SPARCLITE)

/* v9a instructions which would appear to be aliases to v9's impdep's

   otherwise.  */

#define v9notv9a        (MASK_V9)

/* Table of opcode architectures.

   The order is defined in opcode/sparc.h.  */

static const struct sparc_opcode_arch sparc_opcode_archs[] =

{

  { "v6", MASK_V6 },

  { "v7", MASK_V6 | MASK_V7 },

  { "v8", MASK_V6 | MASK_V7 | MASK_V8 },

  { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },

  { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },

  /* ??? Don't some v8 privileged insns conflict with v9?  */

  { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },

  /* v9 with ultrasparc additions */

  { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },

  /* v9 with cheetah additions */

  { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },

  { NULL, 0 }

};

/* Branch condition field.  */

#define COND(x)         (((x) & 0xf) << 25)

/* v9: Move (MOVcc and FMOVcc) condition field.  */

#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */

/* v9: Move register (MOVRcc and FMOVRcc) condition field.  */

#define RCOND(x)        (((x) & 0x7) << 10)     /* v9 */

#define CONDA   (COND (0x8))

#define CONDCC  (COND (0xd))

#define CONDCS  (COND (0x5))

#define CONDE   (COND (0x1))

#define CONDG   (COND (0xa))

#define CONDGE  (COND (0xb))

#define CONDGU  (COND (0xc))

#define CONDL   (COND (0x3))

#define CONDLE  (COND (0x2))

#define CONDLEU (COND (0x4))

#define CONDN   (COND (0x0))

#define CONDNE  (COND (0x9))

#define CONDNEG (COND (0x6))

#define CONDPOS (COND (0xe))

#define CONDVC  (COND (0xf))

#define CONDVS  (COND (0x7))

#define CONDNZ  CONDNE

#define CONDZ   CONDE

#define CONDGEU CONDCC

#define CONDLU  CONDCS

#define FCONDA          (COND (0x8))

#define FCONDE          (COND (0x9))

#define FCONDG          (COND (0x6))

#define FCONDGE         (COND (0xb))

#define FCONDL          (COND (0x4))

#define FCONDLE         (COND (0xd))

#define FCONDLG         (COND (0x2))

#define FCONDN          (COND (0x0))

#define FCONDNE         (COND (0x1))

#define FCONDO          (COND (0xf))

#define FCONDU          (COND (0x7))

#define FCONDUE         (COND (0xa))

#define FCONDUG         (COND (0x5))

#define FCONDUGE        (COND (0xc))

#define FCONDUL         (COND (0x3))

#define FCONDULE        (COND (0xe))

#define FCONDNZ FCONDNE

#define FCONDZ  FCONDE

#define ICC             (0)     /* v9 */

#define XCC             (1 << 12) /* v9 */

#define FCC(x)          (((x) & 0x3) << 11) /* v9 */

#define FBFCC(x)        (((x) & 0x3) << 20)     /* v9 */

/* The order of the opcodes in the table is significant:

        * The assembler requires that all instances of the same mnemonic must

        be consecutive. If they aren't, the assembler will bomb at runtime.

        * The disassembler should not care about the order of the opcodes.  */

/* Entries for commutative arithmetic operations.  */

/* ??? More entries can make use of this.  */

#define COMMUTEOP(opcode, op3, arch_mask) \

{ opcode,       F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),        "1,2,d", 0, arch_mask }, \

{ opcode,       F3(2, op3, 1), F3(~2, ~op3, ~1),                "1,i,d", 0, arch_mask }, \

{ opcode,       F3(2, op3, 1), F3(~2, ~op3, ~1),                "i,1,d", 0, arch_mask }

static const struct sparc_opcode sparc_opcodes[] = {

{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", 0, v6 },

{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", 0, v6 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", 0, v6 },

{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", 0, v6 },

{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", 0, v6 },

{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ld [rs1+0],d */

{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0),              "[1+2],g", 0, v6 },

{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0,       "[1],g", 0, v6 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[1+i],g", 0, v6 },

{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[i+1],g", 0, v6 },

{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,       "[i],g", 0, v6 },

{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),   "[1],g", 0, v6 }, /* ld [rs1+0],d */

{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0),       "[1+2],F", 0, v6 },

{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[1+i],F", 0, v6 },

{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[i+1],F", 0, v6 },

{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },

{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */

{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0),              "[1+2],D", 0, v6notv9 },

{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,       "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i],D", 0, v6notv9 },

{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1],D", 0, v6notv9 },

{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i],D", 0, v6notv9 },

{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),   "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */

{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0),              "[1+2],C", 0, v6notv9 },

{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0,       "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[1+i],C", 0, v6notv9 },

{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[i+1],C", 0, v6notv9 },

{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0,       "[i],C", 0, v6notv9 },

{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0),   "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */

/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the

   'ld' pseudo-op in v9.  */

{ "lduw",       F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", F_ALIAS, v9 },

{ "lduw",       F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */

{ "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", F_ALIAS, v9 },

{ "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", F_ALIAS, v9 },

{ "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", F_ALIAS, v9 },

{ "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */

{ "ldd",        F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", 0, v6 },

{ "ldd",        F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */

{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", 0, v6 },

{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", 0, v6 },

{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", 0, v6 },

{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldd [rs1+0],d */

{ "ldd",        F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),      "[1+2],H", 0, v6 },

{ "ldd",        F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),  "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */

{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[1+i],H", 0, v6 },

{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[i+1],H", 0, v6 },

{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,       "[i],H", 0, v6 },

{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),   "[1],H", 0, v6 }, /* ldd [rs1+0],d */

{ "ldd",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),      "[1+2],D", 0, v6notv9 },

{ "ldd",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),  "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */

{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i],D", 0, v6notv9 },

{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1],D", 0, v6notv9 },

{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i],D", 0, v6notv9 },

{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),   "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */

{ "ldq",        F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0),      "[1+2],J", 0, v9 },

{ "ldq",        F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0),  "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */

{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[1+i],J", 0, v9 },

{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[i+1],J", 0, v9 },

{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0,       "[i],J", 0, v9 },

{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0),   "[1],J", 0, v9 }, /* ldd [rs1+0],d */

{ "ldsb",       F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0),      "[1+2],d", 0, v6 },

{ "ldsb",       F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */

{ "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[1+i],d", 0, v6 },

{ "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[i+1],d", 0, v6 },

{ "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0,       "[i],d", 0, v6 },

{ "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldsb [rs1+0],d */

{ "ldsh",       F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */

{ "ldsh",       F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0),      "[1+2],d", 0, v6 },

{ "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[1+i],d", 0, v6 },

{ "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[i+1],d", 0, v6 },

{ "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0,       "[i],d", 0, v6 },

{ "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldsh [rs1+0],d */

{ "ldstub",     F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0),      "[1+2],d", 0, v6 },

{ "ldstub",     F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */

{ "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[1+i],d", 0, v6 },

{ "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[i+1],d", 0, v6 },

{ "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0,       "[i],d", 0, v6 },

{ "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldstub [rs1+0],d */

{ "ldsw",       F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0),      "[1+2],d", 0, v9 },

{ "ldsw",       F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0),  "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */

{ "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[1+i],d", 0, v9 },

{ "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[i+1],d", 0, v9 },

{ "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0,       "[i],d", 0, v9 },

{ "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0),   "[1],d", 0, v9 }, /* ldsw [rs1+0],d */

{ "ldub",       F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0),      "[1+2],d", 0, v6 },

{ "ldub",       F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */

{ "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[1+i],d", 0, v6 },

{ "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[i+1],d", 0, v6 },

{ "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0,       "[i],d", 0, v6 },

{ "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldub [rs1+0],d */

{ "lduh",       F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0),      "[1+2],d", 0, v6 },

{ "lduh",       F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */

{ "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[1+i],d", 0, v6 },

{ "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[i+1],d", 0, v6 },

{ "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,       "[i],d", 0, v6 },

{ "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* lduh [rs1+0],d */

{ "ldx",        F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0),      "[1+2],d", 0, v9 },

{ "ldx",        F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0),  "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */

{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[1+i],d", 0, v9 },

{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[i+1],d", 0, v9 },

{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0,       "[i],d", 0, v9 },

{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0),   "[1],d", 0, v9 }, /* ldx [rs1+0],d */

{ "ldx",        F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 },

{ "ldx",        F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1),  "[1],F", 0, v9 }, /* ld [rs1+%g0],d */

{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 },

{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 },

{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1),  "[i],F", 0, v9 },

{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */

{ "lda",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0),              "[1+2]A,d", 0, v6 },

{ "lda",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */

{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[1+i]o,d", 0, v9 },

{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[i+1]o,d", 0, v9 },

{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,       "[i]o,d", 0, v9 },

{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */

{ "lda",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0),              "[1+2]A,g", 0, v9 },