/*

 * Tiny Code Generator for QEMU

 *

 * Copyright (c) 2008 Fabrice Bellard

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

static uint8_t *tb_ret_addr;

#ifdef __APPLE__

#define LINKAGE_AREA_SIZE 24

#define LR_OFFSET 8

#elif defined _AIX

#define LINKAGE_AREA_SIZE 52

#define LR_OFFSET 8

#else

#define LINKAGE_AREA_SIZE 8

#define LR_OFFSET 4

#endif

#define FAST_PATH

#if TARGET_PHYS_ADDR_BITS <= 32

#define ADDEND_OFFSET 0

#else

#define ADDEND_OFFSET 4

#endif

#ifndef NDEBUG

static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {

    "r0",

    "r1",

    "rp",

    "r3",

    "r4",

    "r5",

    "r6",

    "r7",

    "r8",

    "r9",

    "r10",

    "r11",

    "r12",

    "r13",

    "r14",

    "r15",

    "r16",

    "r17",

    "r18",

    "r19",

    "r20",

    "r21",

    "r22",

    "r23",

    "r24",

    "r25",

    "r26",

    "r27",

    "r28",

    "r29",

    "r30",

    "r31"

};

#endif

static const int tcg_target_reg_alloc_order[] = {

    TCG_REG_R14,

    TCG_REG_R15,

    TCG_REG_R16,

    TCG_REG_R17,

    TCG_REG_R18,

    TCG_REG_R19,

    TCG_REG_R20,

    TCG_REG_R21,

    TCG_REG_R22,

    TCG_REG_R23,

    TCG_REG_R28,

    TCG_REG_R29,

    TCG_REG_R30,

    TCG_REG_R31,

#ifdef __APPLE__

    TCG_REG_R2,

#endif

    TCG_REG_R3,

    TCG_REG_R4,

    TCG_REG_R5,

    TCG_REG_R6,

    TCG_REG_R7,

    TCG_REG_R8,

    TCG_REG_R9,

    TCG_REG_R10,

#ifndef __APPLE__

    TCG_REG_R11,

#endif

    TCG_REG_R12,

    TCG_REG_R13,

    TCG_REG_R0,

    TCG_REG_R1,

    TCG_REG_R2,

    TCG_REG_R24,

    TCG_REG_R25,

    TCG_REG_R26,

    TCG_REG_R27

};

static const int tcg_target_call_iarg_regs[] = {

    TCG_REG_R3,

    TCG_REG_R4,

    TCG_REG_R5,

    TCG_REG_R6,

    TCG_REG_R7,

    TCG_REG_R8,

    TCG_REG_R9,

    TCG_REG_R10

};

static const int tcg_target_call_oarg_regs[2] = {

    TCG_REG_R3,

    TCG_REG_R4

};

static const int tcg_target_callee_save_regs[] = {

#ifdef __APPLE__

    TCG_REG_R11,

    TCG_REG_R13,

#endif

#ifdef _AIX

    TCG_REG_R13,

#endif

    TCG_REG_R14,

    TCG_REG_R15,

    TCG_REG_R16,

    TCG_REG_R17,

    TCG_REG_R18,

    TCG_REG_R19,

    TCG_REG_R20,

    TCG_REG_R21,

    TCG_REG_R22,

    TCG_REG_R23,

    TCG_REG_R28,

    TCG_REG_R29,

    TCG_REG_R30,

    TCG_REG_R31

};

static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)

{

    tcg_target_long disp;

    disp = target - (tcg_target_long) pc;

    if ((disp << 6) >> 6 != disp)

        tcg_abort ();

    return disp & 0x3fffffc;

}

static void reloc_pc24 (void *pc, tcg_target_long target)

{

    *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)

        | reloc_pc24_val (pc, target);

}

static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)

{

    tcg_target_long disp;

    disp = target - (tcg_target_long) pc;

    if (disp != (int16_t) disp)

        tcg_abort ();

    return disp & 0xfffc;

}

static void reloc_pc14 (void *pc, tcg_target_long target)

{

    *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)

        | reloc_pc14_val (pc, target);

}

static void patch_reloc(uint8_t *code_ptr, int type,

                        tcg_target_long value, tcg_target_long addend)

{

    value += addend;

    switch (type) {

    case R_PPC_REL14:

        reloc_pc14 (code_ptr, value);

        break;

    case R_PPC_REL24:

        reloc_pc24 (code_ptr, value);

        break;

    default:

        tcg_abort();

    }

}

/* maximum number of register used for input function arguments */

static int tcg_target_get_call_iarg_regs_count(int flags)

{

    return ARRAY_SIZE (tcg_target_call_iarg_regs);

}

/* parse target specific constraints */

static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)

{

    const char *ct_str;

    ct_str = *pct_str;

    switch (ct_str[0]) {

    case 'A': case 'B': case 'C': case 'D':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');

        break;

    case 'r':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);

        break;

#ifdef CONFIG_SOFTMMU

    case 'L':                   /* qemu_ld constraint */

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);

        break;

    case 'K':                   /* qemu_st[8..32] constraint */

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);

#if TARGET_LONG_BITS == 64

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);

#endif

        break;

    case 'M':                   /* qemu_st64 constraint */

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);

        break;

#else

    case 'L':

    case 'K':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);

        break;

    case 'M':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);

        break;

#endif

    default:

        return -1;

    }

    ct_str++;

    *pct_str = ct_str;

    return 0;

}

/* test if a constant matches the constraint */

static int tcg_target_const_match(tcg_target_long val,

                                  const TCGArgConstraint *arg_ct)

{

    int ct;

    ct = arg_ct->ct;

    if (ct & TCG_CT_CONST)

        return 1;

    return 0;

}

#define OPCD(opc) ((opc)<<26)

#define XO31(opc) (OPCD(31)|((opc)<<1))

#define XO19(opc) (OPCD(19)|((opc)<<1))

#define B      OPCD(18)

#define BC     OPCD(16)

#define LBZ    OPCD(34)

#define LHZ    OPCD(40)

#define LHA    OPCD(42)

#define LWZ    OPCD(32)

#define STB    OPCD(38)

#define STH    OPCD(44)

#define STW    OPCD(36)

#define ADDI   OPCD(14)

#define ADDIS  OPCD(15)

#define ORI    OPCD(24)

#define ORIS   OPCD(25)

#define XORI   OPCD(26)

#define XORIS  OPCD(27)

#define ANDI   OPCD(28)

#define ANDIS  OPCD(29)

#define MULLI  OPCD( 7)

#define CMPLI  OPCD(10)

#define CMPI   OPCD(11)

#define LWZU   OPCD(33)

#define STWU   OPCD(37)

#define RLWINM OPCD(21)

#define BCLR   XO19( 16)

#define BCCTR  XO19(528)

#define CRAND  XO19(257)

#define CRANDC XO19(129)

#define CRNAND XO19(225)

#define CROR   XO19(449)

#define EXTSB  XO31(954)

#define EXTSH  XO31(922)

#define ADD    XO31(266)

#define ADDE   XO31(138)

#define ADDC   XO31( 10)

#define AND    XO31( 28)

#define SUBF   XO31( 40)

#define SUBFC  XO31(  8)

#define SUBFE  XO31(136)

#define OR     XO31(444)

#define XOR    XO31(316)

#define MULLW  XO31(235)

#define MULHWU XO31( 11)

#define DIVW   XO31(491)

#define DIVWU  XO31(459)

#define CMP    XO31(  0)

#define CMPL   XO31( 32)

#define LHBRX  XO31(790)

#define LWBRX  XO31(534)

#define STHBRX XO31(918)

#define STWBRX XO31(662)

#define MFSPR  XO31(339)

#define MTSPR  XO31(467)

#define SRAWI  XO31(824)

#define NEG    XO31(104)

#define LBZX   XO31( 87)

#define LHZX   XO31(276)

#define LHAX   XO31(343)

#define LWZX   XO31( 23)

#define STBX   XO31(215)

#define STHX   XO31(407)

#define STWX   XO31(151)

#define SPR(a,b) ((((a)<<5)|(b))<<11)

#define LR     SPR(8, 0)

#define CTR    SPR(9, 0)

#define SLW    XO31( 24)

#define SRW    XO31(536)

#define SRAW   XO31(792)

#define LMW    OPCD(46)

#define STMW   OPCD(47)

#define TW     XO31(4)

#define TRAP   (TW | TO (31))

#define RT(r) ((r)<<21)

#define RS(r) ((r)<<21)

#define RA(r) ((r)<<16)

#define RB(r) ((r)<<11)

#define TO(t) ((t)<<21)

#define SH(s) ((s)<<11)

#define MB(b) ((b)<<6)

#define ME(e) ((e)<<1)

#define BO(o) ((o)<<21)

#define LK    1

#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))

#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))

#define BF(n)    ((n)<<23)

#define BI(n, c) (((c)+((n)*4))<<16)

#define BT(n, c) (((c)+((n)*4))<<21)

#define BA(n, c) (((c)+((n)*4))<<16)

#define BB(n, c) (((c)+((n)*4))<<11)

#define BO_COND_TRUE  BO (12)

#define BO_COND_FALSE BO (4)

#define BO_ALWAYS     BO (20)

enum {

    CR_LT,

    CR_GT,

    CR_EQ,

    CR_SO

};

static const uint32_t tcg_to_bc[10] = {

    [TCG_COND_EQ]  = BC | BI (7, CR_EQ) | BO_COND_TRUE,

    [TCG_COND_NE]  = BC | BI (7, CR_EQ) | BO_COND_FALSE,

    [TCG_COND_LT]  = BC | BI (7, CR_LT) | BO_COND_TRUE,

    [TCG_COND_GE]  = BC | BI (7, CR_LT) | BO_COND_FALSE,

    [TCG_COND_LE]  = BC | BI (7, CR_GT) | BO_COND_FALSE,

    [TCG_COND_GT]  = BC | BI (7, CR_GT) | BO_COND_TRUE,

    [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,

    [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,

    [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,

    [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,

};

static void tcg_out_mov(TCGContext *s, int ret, int arg)

{

    tcg_out32 (s, OR | SAB (arg, ret, arg));

}

static void tcg_out_movi(TCGContext *s, TCGType type,

                         int ret, tcg_target_long arg)

{

    if (arg == (int16_t) arg)

        tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));

    else {

        tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));

        if (arg & 0xffff)

            tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));

    }

}

static void tcg_out_ldst (TCGContext *s, int ret, int addr,

                          int offset, int op1, int op2)

{

    if (offset == (int16_t) offset)

        tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));

    else {

        tcg_out_movi (s, TCG_TYPE_I32, 0, offset);

        tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));

    }

}

static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)

{

    tcg_target_long disp;

    disp = target - (tcg_target_long) s->code_ptr;

    if ((disp << 6) >> 6 == disp)

        tcg_out32 (s, B | (disp & 0x3fffffc) | mask);

    else {

        tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);

        tcg_out32 (s, MTSPR | RS (0) | CTR);

        tcg_out32 (s, BCCTR | BO_ALWAYS | mask);

    }

}

#ifdef _AIX

static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)

{

    int reg;

    if (const_arg) {

        reg = 2;

        tcg_out_movi (s, TCG_TYPE_I32, reg, arg);

    }

    else reg = arg;

    tcg_out32 (s, LWZ | RT (0) | RA (reg));

    tcg_out32 (s, MTSPR | RA (0) | CTR);

    tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);

    tcg_out32 (s, BCCTR | BO_ALWAYS | LK);

}

#endif

#if defined(CONFIG_SOFTMMU)

#include "../../softmmu_defs.h"

static void *qemu_ld_helpers[4] = {

    __ldb_mmu,

    __ldw_mmu,

    __ldl_mmu,

    __ldq_mmu,

};

static void *qemu_st_helpers[4] = {

    __stb_mmu,

    __stw_mmu,

    __stl_mmu,

    __stq_mmu,

};

#endif

static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)

{

    int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;

#ifdef CONFIG_SOFTMMU

    int r2;

    void *label1_ptr, *label2_ptr;

#endif

#if TARGET_LONG_BITS == 64

    int addr_reg2;

#endif

    data_reg = *args++;

    if (opc == 3)

        data_reg2 = *args++;

    else

        data_reg2 = 0;

    addr_reg = *args++;

#if TARGET_LONG_BITS == 64

    addr_reg2 = *args++;

#endif

    mem_index = *args;

    s_bits = opc & 3;

#ifdef CONFIG_SOFTMMU

    r0 = 3;

    r1 = 4;

    r2 = 0;

    tcg_out32 (s, (RLWINM