| author | Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com> |
| Wed, 31 Mar 2010 23:38:45 +0300 | |
| branch | RCL_3 |
| changeset 22 | 2f92ad2dc5db |
| parent 8 | 538db54a451d |
| child 43 | c1f20ce4abcf |
| permissions | -rw-r--r-- |
| 0 | 1 |
// Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies). |
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// All rights reserved. |
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// This component and the accompanying materials are made available |
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// under the terms of the License "Eclipse Public License v1.0" |
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// which accompanies this distribution, and is available |
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// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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// |
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// Initial Contributors: |
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// Nokia Corporation - initial contribution. |
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// |
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// Contributors: |
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// |
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// Description: |
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// e32\memmodel\epoc\moving\arm\xmmu.cpp |
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// |
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// |
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#include "arm_mem.h" |
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#include <mmubase.inl> |
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#include <ramcache.h> |
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#include <demand_paging.h> |
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#include "execs.h" |
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#include <defrag.h> |
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#include "cache_maintenance.h" |
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extern void FlushTLBs(); |
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#if defined(__CPU_SA1__) |
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const TPde KRomSectionPermissions = SECTION_PDE(KArmV45PermRORO, KArmV45MemAttWB, EDomainClient); |
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const TPde KShadowPdePerm = PT_PDE(EDomainClient); |
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const TPte KPtPtePerm = SP_PTE(KArmV45PermRWNO, KArmV45MemAttBuf); // page tables not cached |
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const TPte KRomPtePermissions = SP_PTE(KArmV45PermRORO, KArmV45MemAttWB); // ROM is cached, read-only for everyone |
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const TPte KShadowPtePerm = SP_PTE(KArmV45PermRWRO, KArmV45MemAttWB); // shadowed ROM is cached, supervisor writeable |
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#elif defined(__CPU_ARM710T__) || defined(__CPU_ARM720T__) |
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const TPde KRomSectionPermissions = SECTION_PDE(KArmV45PermRORO, KArmV45MemAttWB, EDomainClient); |
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const TPde KShadowPdePerm = PT_PDE(EDomainClient); |
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const TPte KPtPtePerm = SP_PTE(KArmV45PermRWNO, KArmV45MemAttWB); // page tables cached (write-through) |
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const TPte KRomPtePermissions = SP_PTE(KArmV45PermRORO, KArmV45MemAttWB); // ROM is cached, read-only for everyone |
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const TPte KShadowPtePerm = SP_PTE(KArmV45PermRWRO, KArmV45MemAttWB); // shadowed ROM is cached, supervisor writeable |
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#elif defined(__CPU_ARM920T__) || defined(__CPU_ARM925T__) || defined(__CPU_ARM926J__) |
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const TPde KRomSectionPermissions = SECTION_PDE(KArmV45PermRORO, KArmV45MemAttWT, EDomainClient); |
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const TPde KShadowPdePerm = PT_PDE(EDomainClient); |
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const TPte KPtPtePerm = SP_PTE(KArmV45PermRWNO, KArmV45MemAttWT); // page tables cached write through |
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const TPte KRomPtePermissions = SP_PTE(KArmV45PermRORO, KArmV45MemAttWT); // ROM is cached, read-only for everyone |
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const TPte KShadowPtePerm = SP_PTE(KArmV45PermRWRO, KArmV45MemAttWT); // shadowed ROM is cached, supervisor writeable |
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#elif defined(__CPU_XSCALE__) |
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#ifdef __CPU_XSCALE_MANZANO__ |
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const TPde KRomSectionPermissions = SECTION_PDE(KArmV45PermRORO, KXScaleMemAttWTRA_WBWA, EDomainClient); |
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const TPde KShadowPdePerm = PT_PDE(EDomainClient); |
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const TPte KPtPtePerm = SP_PTE(KArmV45PermRWNO, KXScaleMemAttWTRA_WBWA); // page tables write-through cached |
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const TPte KRomPtePermissions = SP_PTE(KArmV45PermRORO, KXScaleMemAttWTRA_WBWA); // ROM is cached, read-only for everyone |
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const TPte KShadowPtePerm = SP_PTE(KArmV45PermRWRO, KXScaleMemAttWTRA_WBWA); // shadowed ROM is cached, supervisor writeable |
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#else |
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const TPde KRomSectionPermissions = SECTION_PDE(KArmV45PermRORO, KXScaleMemAttWTRA, EDomainClient); |
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const TPde KShadowPdePerm = PT_PDE(EDomainClient); |
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const TPte KPtPtePerm = SP_PTE(KArmV45PermRWNO, KXScaleMemAttWTRA); // page tables write-through cached |
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const TPte KRomPtePermissions = SP_PTE(KArmV45PermRORO, KXScaleMemAttWTRA); // ROM is cached, read-only for everyone |
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const TPte KShadowPtePerm = SP_PTE(KArmV45PermRWRO, KXScaleMemAttWTRA); // shadowed ROM is cached, supervisor writeable |
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#endif |
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#endif |
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const TPte KPtInfoPtePerm = KPtPtePerm; |
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const TPde KPtPdePerm = PT_PDE(EDomainClient); |
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// Permissions for each chunk type |
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enum TPTEProperties |
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{
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ESupRo = SP_PTE(KArmV45PermRORO, KDefaultCaching), |
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ESupRw = SP_PTE(KArmV45PermRWNO, KDefaultCaching), |
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EUserRo = SP_PTE(KArmV45PermRWRO, KDefaultCaching), |
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EUserRw = SP_PTE(KArmV45PermRWRW, KDefaultCaching) |
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}; |
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LOCAL_D const TPde ChunkPdePermissions[ENumChunkTypes] = |
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{
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PT_PDE(EDomainClient), // EKernelData |
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PT_PDE(EDomainClient), // EKernelStack |
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PT_PDE(EDomainClient), // EKernelCode |
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PT_PDE(EDomainClient), // EDll |
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PT_PDE(EDomainClient), // EUserCode - user/ro & sup/rw everywhere |
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PT_PDE(EDomainClient), // ERamDrive - sup/rw accessed by domain change |
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// user data or self modifying code is sup/rw, user no access at home. It's user/rw & sup/rw when running |
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// note ARM MMU architecture prevents implementation of user read-only data |
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PT_PDE(EDomainClient), // EUserData |
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PT_PDE(EDomainClient), // EDllData |
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PT_PDE(EDomainClient), // EUserSelfModCode |
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PT_PDE(EDomainClient), // ESharedKernelSingle |
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PT_PDE(EDomainClient), // ESharedKernelMultiple |
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PT_PDE(EDomainClient), // ESharedIo |
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PT_PDE(EDomainClient), // ESharedKernelMirror (unused in this memory model) |
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PT_PDE(EDomainClient), // EKernelMessage |
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}; |
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const TPde KUserDataRunningPermissions = PT_PDE(EDomainVarUserRun); |
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LOCAL_D const TPte ChunkPtePermissions[ENumChunkTypes] = |
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{
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ESupRw, // EKernelData |
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ESupRw, // EKernelStack |
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ESupRw, // EKernelCode |
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EUserRo, // EDll |
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EUserRo, // EUserCode |
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ESupRw, // ERamDrive |
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ESupRw, // EUserData |
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ESupRw, // EDllData |
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ESupRw, // EUserSelfModCode |
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ESupRw, // ESharedKernelSingle |
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ESupRw, // ESharedKernelMultiple |
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ESupRw, // ESharedIo |
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ESupRw, // ESharedKernelMirror (unused in this memory model) |
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ESupRw, // EKernelMessage |
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}; |
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const TPte KUserCodeLoadPte = (TPte)EUserRo; |
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const TPte KKernelCodeRunPte = (TPte)ESupRw; |
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// Inline functions for simple transformations |
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inline TLinAddr PageTableLinAddr(TInt aId) |
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{
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return KPageTableBase + (aId<<KPageTableShift); |
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} |
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inline TPte* PageTable(TInt aId) |
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{
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return (TPte*)(KPageTableBase+(aId<<KPageTableShift)); |
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} |
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inline TPde* PageDirectoryEntry(TLinAddr aLinAddr) |
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{
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return PageDirectory + (aLinAddr>>KChunkShift); |
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} |
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inline TBool IsPageTable(TPde aPde) |
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{
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return ((aPde&KPdeTypeMask)==KArmV45PdePageTable); |
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} |
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inline TBool IsSectionDescriptor(TPde aPde) |
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{
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return ((aPde&KPdeTypeMask)==KArmV45PdeSection); |
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} |
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inline TBool IsPresent(TPte aPte) |
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{
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return (aPte&KPtePresentMask); |
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} |
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inline TPhysAddr PageTablePhysAddr(TPde aPde) |
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{
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return aPde & KPdePageTableAddrMask; |
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} |
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inline TPhysAddr PhysAddrFromSectionDescriptor(TPde aPde) |
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{
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return aPde & KPdeSectionAddrMask; |
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} |
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extern void InvalidateTLBForPage(TLinAddr /*aLinAddr*/); |
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void Mmu::SetupInitialPageInfo(SPageInfo* aPageInfo, TLinAddr aChunkAddr, TInt aPdeIndex) |
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{
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__ASSERT_ALWAYS(aChunkAddr==0 || aChunkAddr>=KRamDriveEndAddress, Panic(EBadInitialPageAddr)); |
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TLinAddr addr = aChunkAddr + (aPdeIndex<<KPageShift); |
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if (aPageInfo->Type()!=SPageInfo::EUnused) |
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return; // already set (page table) |
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if (addr == KPageTableInfoBase) |
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{
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aPageInfo->SetPtInfo(0); |
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aPageInfo->Lock(); |
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} |
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else if (addr>=KPageDirectoryBase && addr<(KPageDirectoryBase+KPageDirectorySize)) |
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{
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aPageInfo->SetPageDir(0,aPdeIndex); |
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aPageInfo->Lock(); |
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} |
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else |
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aPageInfo->SetFixed(); |
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} |
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void Mmu::SetupInitialPageTableInfo(TInt aId, TLinAddr aChunkAddr, TInt aNumPtes) |
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{
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__ASSERT_ALWAYS(aChunkAddr==0 || aChunkAddr>=KRamDriveEndAddress, Panic(EBadInitialPageAddr)); |
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SPageTableInfo& pti=PtInfo(aId); |
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pti.iCount=aNumPtes; |
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pti.SetGlobal(aChunkAddr>>KChunkShift); |
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} |
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TInt Mmu::GetPageTableId(TLinAddr aAddr) |
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{
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TInt id=-1; |
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__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::PageTableId(%08x)",aAddr));
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TInt pdeIndex=aAddr>>KChunkShift; |
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TPde pde = PageDirectory[pdeIndex]; |
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if (IsPageTable(pde)) |
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{
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SPageInfo* pi = SPageInfo::SafeFromPhysAddr(pde); |
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if (pi) |
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id = (pi->Offset()<<KPtClusterShift) | ((pde>>KPageTableShift)&KPtClusterMask); |
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} |
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__KTRACE_OPT(KMMU,Kern::Printf("ID=%d",id));
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return id; |
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} |
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// Used only during boot for recovery of RAM drive |
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TInt ArmMmu::BootPageTableId(TLinAddr aAddr, TPhysAddr& aPtPhys) |
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{
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TInt id=KErrNotFound; |
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__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu:BootPageTableId(%08x,&)",aAddr));
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TInt pdeIndex=aAddr>>KChunkShift; |
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TPde pde = PageDirectory[pdeIndex]; |
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if (IsPageTable(pde)) |
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{
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aPtPhys = pde & KPdePageTableAddrMask; |
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SPageInfo* pi = SPageInfo::SafeFromPhysAddr(pde); |
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if (pi) |
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{
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SPageInfo::TType type = pi->Type(); |
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if (type == SPageInfo::EPageTable) |
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id = (pi->Offset()<<KPtClusterShift) | ((pde>>KPageTableShift)&KPtClusterMask); |
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else if (type == SPageInfo::EUnused) |
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id = KErrUnknown; |
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} |
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} |
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__KTRACE_OPT(KMMU,Kern::Printf("ID=%d",id));
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return id; |
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} |
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TBool ArmMmu::PteIsPresent(TPte aPte) |
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{
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return aPte & KPtePresentMask; |
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} |
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TPhysAddr ArmMmu::PtePhysAddr(TPte aPte, TInt aPteIndex) |
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{
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TUint pte_type = aPte & KPteTypeMask; |
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if (pte_type == KArmV45PteLargePage) |
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return (aPte & KPteLargePageAddrMask) + (TPhysAddr(aPteIndex << KPageShift) & KLargePageMask); |
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else if (pte_type != 0) |
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return aPte & KPteSmallPageAddrMask; |
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return KPhysAddrInvalid; |
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} |
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TPhysAddr ArmMmu::PdePhysAddr(TLinAddr aAddr) |
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{
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TPde pde = PageDirectory[aAddr>>KChunkShift]; |
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if (IsSectionDescriptor(pde)) |
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return PhysAddrFromSectionDescriptor(pde); |
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return KPhysAddrInvalid; |
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} |
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TPte* SafePageTableFromPde(TPde aPde) |
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{
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if((aPde&KPdeTypeMask)==KArmV45PdePageTable) |
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{
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SPageInfo* pi = SPageInfo::SafeFromPhysAddr(aPde); |
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if(pi) |
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{
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TInt id = (pi->Offset()<<KPtClusterShift) | ((aPde>>KPageTableShift)&KPtClusterMask); |
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return PageTable(id); |
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} |
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} |
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return 0; |
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} |
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TPte* SafePtePtrFromLinAddr(TLinAddr aAddress) |
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{
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TPde pde = PageDirectory[aAddress>>KChunkShift]; |
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TPte* pt = SafePageTableFromPde(pde); |
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if(pt) |
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pt += (aAddress>>KPageShift)&(KChunkMask>>KPageShift); |
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return pt; |
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} |
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#ifdef __ARMCC__ |
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__forceinline /* RVCT ignores normal inline qualifier :-( */ |
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#else |
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inline |
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#endif |
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TPte* PtePtrFromLinAddr(TLinAddr aAddress) |
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{
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TPde pde = PageDirectory[aAddress>>KChunkShift]; |
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SPageInfo* pi = SPageInfo::FromPhysAddr(pde); |
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TInt id = (pi->Offset()<<KPtClusterShift) | ((pde>>KPageTableShift)&KPtClusterMask); |
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TPte* pt = PageTable(id); |
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pt += (aAddress>>KPageShift)&(KChunkMask>>KPageShift); |
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return pt; |
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} |
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TInt ArmMmu::LinearToPhysical(TLinAddr aLinAddr, TInt aSize, TPhysAddr& aPhysicalAddress, TPhysAddr* aPhysicalPageList) |
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{
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TPhysAddr physStart = ArmMmu::LinearToPhysical(aLinAddr); |
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TPhysAddr nextPhys = physStart&~KPageMask; |
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TUint32* pageList = aPhysicalPageList; |
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TInt pageIndex = aLinAddr>>KPageShift; |
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TInt pagesLeft = ((aLinAddr+aSize-1)>>KPageShift)+1 - pageIndex; |
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TPde* pdePtr = &PageDirectory[aLinAddr>>KChunkShift]; |
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while(pagesLeft) |
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{
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pageIndex &= KChunkMask>>KPageShift; |
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TInt pagesLeftInChunk = (1<<(KChunkShift-KPageShift))-pageIndex; |
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if(pagesLeftInChunk>pagesLeft) |
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pagesLeftInChunk = pagesLeft; |
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pagesLeft -= pagesLeftInChunk; |
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TPhysAddr phys; |
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TPde pde = *pdePtr++; |
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TUint pdeType = pde&KPdeTypeMask; |
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if(pdeType==KArmV45PdeSection) |
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{
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phys = (pde & KPdeSectionAddrMask) + (pageIndex*KPageSize); |
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__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::LinearToPhysical Section phys=%8x",phys));
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TInt n=pagesLeftInChunk; |
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phys==nextPhys ? nextPhys+=n*KPageSize : nextPhys=KPhysAddrInvalid; |
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if(pageList) |
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{
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TUint32* pageEnd = pageList+n; |
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do |
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{
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*pageList++ = phys; |
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phys+=KPageSize; |
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} |
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while(pageList<pageEnd); |
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} |
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} |
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else |
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{
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TPte* pt = SafePageTableFromPde(pde); |
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if(!pt) |
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{
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__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::LinearToPhysical missing page table: PDE=%8x",pde));
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return KErrNotFound; |
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} |
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pt += pageIndex; |
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for(;;) |
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{
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TPte pte = *pt++; |
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TUint pte_type = pte & KPteTypeMask; |
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if (pte_type >= KArmV45PteSmallPage) |
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{
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phys = (pte & KPteSmallPageAddrMask); |
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__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::LinearToPhysical Small Page phys=%8x",phys));
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phys==nextPhys ? nextPhys+=KPageSize : nextPhys=KPhysAddrInvalid; |
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if(pageList) |
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*pageList++ = phys; |
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if(--pagesLeftInChunk) |
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continue; |
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break; |
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} |
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if (pte_type == KArmV45PteLargePage) |
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{
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--pt; // back up ptr |
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TUint pageOffset = ((TUint)pt>>2)&(KLargeSmallPageRatio-1); |
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phys = (pte & KPteLargePageAddrMask) + pageOffset*KPageSize; |
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__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::LinearToPhysical Large Page phys=%8x",phys));
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TInt n=KLargeSmallPageRatio-pageOffset; |
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if(n>pagesLeftInChunk) |
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n = pagesLeftInChunk; |
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phys==nextPhys ? nextPhys+=n*KPageSize : nextPhys=KPhysAddrInvalid; |
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if(pageList) |
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{
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TUint32* pageEnd = pageList+n; |
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do |
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{
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*pageList++ = phys; |
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phys+=KPageSize; |
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} |
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while(pageList<pageEnd); |
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} |
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pt += n; |
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if(pagesLeftInChunk-=n) |
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continue; |
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break; |
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} |
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__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::LinearToPhysical bad PTE %8x",pte));
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return KErrNotFound; |
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} |
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} |
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if(!pageList && nextPhys==KPhysAddrInvalid) |
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{
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__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::LinearToPhysical not contiguous"));
|
|
390 |
return KErrNotFound; |
|
391 |
} |
|
392 |
pageIndex = 0; |
|
393 |
} |
|
394 |
||
395 |
if(nextPhys==KPhysAddrInvalid) |
|
396 |
{
|
|
397 |
// Memory is discontiguous... |
|
398 |
aPhysicalAddress = KPhysAddrInvalid; |
|
399 |
return 1; |
|
400 |
} |
|
401 |
else |
|
402 |
{
|
|
403 |
// Memory is contiguous... |
|
404 |
aPhysicalAddress = physStart; |
|
405 |
return KErrNone; |
|
406 |
} |
|
407 |
} |
|
408 |
||
409 |
TPhysAddr ArmMmu::LinearToPhysical(TLinAddr aLinAddr) |
|
410 |
{
|
|
411 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::LinearToPhysical(%08x)",aLinAddr));
|
|
412 |
TPhysAddr phys = KPhysAddrInvalid; |
|
413 |
TPde pde = PageDirectory[aLinAddr>>KChunkShift]; |
|
414 |
if (IsPageTable(pde)) |
|
415 |
{
|
|
416 |
SPageInfo* pi = SPageInfo::SafeFromPhysAddr(pde); |
|
417 |
if (pi) |
|
418 |
{
|
|
419 |
TInt id = (pi->Offset()<<KPtClusterShift) | ((pde>>KPageTableShift)&KPtClusterMask); |
|
420 |
TInt pteIndex = (aLinAddr & KChunkMask)>>KPageShift; |
|
421 |
TPte pte = PageTable(id)[pteIndex]; |
|
422 |
TUint pte_type = pte & KPteTypeMask; |
|
423 |
if (pte_type == KArmV45PteLargePage) |
|
424 |
{
|
|
425 |
phys = (pte & KPteLargePageAddrMask) + (aLinAddr & KLargePageMask); |
|
426 |
__KTRACE_OPT(KMMU,Kern::Printf("Mapped with 64K page - returning %08x", phys));
|
|
427 |
} |
|
428 |
else if (pte_type != 0) |
|
429 |
{
|
|
430 |
phys = (pte & KPteSmallPageAddrMask) + (aLinAddr & KPageMask); |
|
431 |
__KTRACE_OPT(KMMU,Kern::Printf("Mapped with 4K page - returning %08x", phys));
|
|
432 |
} |
|
433 |
} |
|
434 |
} |
|
435 |
else if (IsSectionDescriptor(pde)) |
|
436 |
{
|
|
437 |
phys = (pde & KPdeSectionAddrMask) + (aLinAddr & KChunkMask); |
|
438 |
__KTRACE_OPT(KMMU,Kern::Printf("Mapped with section - returning %08x", phys));
|
|
439 |
} |
|
440 |
else |
|
441 |
{
|
|
442 |
__KTRACE_OPT(KMMU,Kern::Printf("Address invalid"));
|
|
443 |
} |
|
444 |
return phys; |
|
445 |
} |
|
446 |
||
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
447 |
|
| 0 | 448 |
TInt ArmMmu::PreparePagesForDMA(TLinAddr aLinAddr, TInt aSize, TPhysAddr* aPhysicalPageList) |
449 |
//Returns the list of physical pages belonging to the specified memory space. |
|
450 |
//Checks these pages belong to a chunk marked as being trusted. |
|
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
451 |
//Locks these pages so they can not be moved by e.g. ram defragmentation. |
| 0 | 452 |
{
|
453 |
SPageInfo* pi = NULL; |
|
454 |
DChunk* chunk = NULL; |
|
455 |
TInt err = KErrNone; |
|
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
456 |
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
457 |
__NK_ASSERT_DEBUG(MM::MaxPagesInOneGo == 32); // Needs to be a power of 2. |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
458 |
TUint flashMask = MM::MaxPagesInOneGo - 1; |
| 0 | 459 |
|
460 |
__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::PreparePagesForDMA %08x+%08x, asid=%d",aLinAddr,aSize));
|
|
461 |
||
462 |
TUint32* pageList = aPhysicalPageList; |
|
463 |
TInt pagesInList = 0; //The number of pages we put in the list so far |
|
464 |
||
465 |
TInt pageIndex = (aLinAddr & KChunkMask) >> KPageShift; // Index of the page within the section |
|
466 |
TInt pagesLeft = ((aLinAddr & KPageMask) + aSize + KPageMask) >> KPageShift; |
|
467 |
||
468 |
MmuBase::Wait(); // RamAlloc Mutex for accessing page/directory tables. |
|
469 |
NKern::LockSystem();// SystemlLock for accessing SPageInfo objects. |
|
470 |
||
471 |
TPde* pdePtr = PageDirectory + (aLinAddr>>KChunkShift); |
|
472 |
||
473 |
while(pagesLeft) |
|
474 |
{
|
|
475 |
TInt pagesLeftInChunk = (1<<(KChunkShift-KPageShift))-pageIndex; |
|
476 |
if(pagesLeftInChunk>pagesLeft) |
|
477 |
pagesLeftInChunk = pagesLeft; |
|
478 |
||
479 |
pagesLeft -= pagesLeftInChunk; |
|
480 |
||
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
481 |
TPte* pPte = SafePageTableFromPde(*pdePtr++); |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
482 |
if(!pPte) |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
483 |
{// Cannot get page table.
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
484 |
err = KErrNotFound; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
485 |
goto fail; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
486 |
} |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
487 |
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
488 |
pPte += pageIndex; |
| 0 | 489 |
|
490 |
for(;pagesLeftInChunk--;) |
|
491 |
{
|
|
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
492 |
TPhysAddr phys = (*pPte++ & KPteSmallPageAddrMask); |
| 0 | 493 |
pi = SPageInfo::SafeFromPhysAddr(phys); |
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
494 |
if(!pi) |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
495 |
{// Invalid address
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
496 |
err = KErrNotFound; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
497 |
goto fail; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
498 |
} |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
499 |
|
| 0 | 500 |
__KTRACE_OPT(KMMU2,Kern::Printf("PageInfo: PA:%x T:%x S:%x O:%x C:%x",phys, pi->Type(), pi->State(), pi->Owner(), pi->LockCount()));
|
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
501 |
if (chunk == NULL) |
| 0 | 502 |
{//This is the first page. Check 'trusted' bit.
|
503 |
if (pi->Type()!= SPageInfo::EChunk) |
|
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
504 |
{// The first page does not belong to a chunk.
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
505 |
err = KErrAccessDenied; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
506 |
goto fail; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
507 |
} |
| 0 | 508 |
|
509 |
chunk = (DChunk*)pi->Owner(); |
|
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
510 |
if ((chunk == NULL) || ((chunk->iAttributes & DChunk::ETrustedChunk) == 0)) |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
511 |
{// Not a trusted chunk
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
512 |
err = KErrAccessDenied; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
513 |
goto fail; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
514 |
} |
| 0 | 515 |
} |
516 |
pi->Lock(); |
|
517 |
||
518 |
*pageList++ = phys; |
|
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
519 |
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
520 |
if(!(++pagesInList & flashMask)) |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
521 |
{
|
| 0 | 522 |
NKern::FlashSystem(); |
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
523 |
} |
| 0 | 524 |
} |
525 |
pageIndex = 0; |
|
526 |
} |
|
527 |
||
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
528 |
if (pi->Type() != SPageInfo::EChunk) |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
529 |
{// The last page does not belong to a chunk.
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
530 |
err = KErrAccessDenied; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
531 |
goto fail; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
532 |
} |
| 0 | 533 |
|
534 |
if (chunk && (chunk != (DChunk*)pi->Owner())) |
|
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
535 |
{//The first & the last page do not belong to the same chunk.
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
536 |
err = KErrArgument; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
537 |
goto fail; |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
538 |
} |
| 0 | 539 |
|
540 |
NKern::UnlockSystem(); |
|
541 |
MmuBase::Signal(); |
|
542 |
return KErrNone; |
|
543 |
||
544 |
fail: |
|
545 |
__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::PreparePagesForDMA failed"));
|
|
546 |
NKern::UnlockSystem(); |
|
547 |
MmuBase::Signal(); |
|
548 |
ReleasePagesFromDMA(aPhysicalPageList, pagesInList); |
|
549 |
return err; |
|
550 |
} |
|
551 |
||
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
552 |
|
| 0 | 553 |
TInt ArmMmu::ReleasePagesFromDMA(TPhysAddr* aPhysicalPageList, TInt aPageCount) |
554 |
// Unlocks physical pages. |
|
555 |
// @param aPhysicalPageList - points to the list of physical pages that should be released. |
|
556 |
// @param aPageCount - the number of physical pages in the list. |
|
557 |
{
|
|
558 |
NKern::LockSystem(); |
|
559 |
__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::ReleasePagesFromDMA count:%d",aPageCount));
|
|
560 |
||
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
561 |
TUint flashMask = MM::MaxPagesInOneGo - 1; |
| 0 | 562 |
while (aPageCount--) |
563 |
{
|
|
564 |
SPageInfo* pi = SPageInfo::SafeFromPhysAddr(*aPhysicalPageList++); |
|
565 |
if(!pi) |
|
566 |
{
|
|
567 |
NKern::UnlockSystem(); |
|
568 |
return KErrArgument; |
|
569 |
} |
|
570 |
__KTRACE_OPT(KMMU2,Kern::Printf("PageInfo: T:%x S:%x O:%x C:%x",pi->Type(), pi->State(), pi->Owner(), pi->LockCount()));
|
|
571 |
pi->Unlock(); |
|
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
572 |
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
573 |
if(!(aPageCount & flashMask)) |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
574 |
{
|
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
575 |
NKern::FlashSystem(); |
|
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
576 |
} |
| 0 | 577 |
} |
578 |
NKern::UnlockSystem(); |
|
579 |
return KErrNone; |
|
580 |
} |
|
581 |
||
582 |
||
|
22
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
8
diff
changeset
|
583 |
|
| 0 | 584 |
void ArmMmu::Init1() |
585 |
{
|
|
586 |
__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("ArmMmu::Init1"));
|
|
587 |
||
588 |
// MmuBase data |
|
589 |
iPageSize=KPageSize; |
|
590 |
iPageMask=KPageMask; |
|
591 |
iPageShift=KPageShift; |
|
592 |
iChunkSize=KChunkSize; |
|
593 |
iChunkMask=KChunkMask; |
|
594 |
iChunkShift=KChunkShift; |
|
595 |
iPageTableSize=KPageTableSize; |
|
596 |
iPageTableMask=KPageTableMask; |
|
597 |
iPageTableShift=KPageTableShift; |
|
598 |
iPtClusterSize=KPtClusterSize; |
|
599 |
iPtClusterMask=KPtClusterMask; |
|
600 |
iPtClusterShift=KPtClusterShift; |
|
601 |
iPtBlockSize=KPtBlockSize; |
|
602 |
iPtBlockMask=KPtBlockMask; |
|
603 |
iPtBlockShift=KPtBlockShift; |
|
604 |
iPtGroupSize=KChunkSize/KPageTableSize; |
|
605 |
iPtGroupMask=iPtGroupSize-1; |
|
606 |
iPtGroupShift=iChunkShift-iPageTableShift; |
|
607 |
//TInt* iPtBlockCount; // dynamically allocated - Init2 |
|
608 |
//TInt* iPtGroupCount; // dynamically allocated - Init2 |
|
609 |
iPtInfo=(SPageTableInfo*)KPageTableInfoBase; |
|
610 |
iPageTableLinBase=KPageTableBase; |
|
611 |
//iRamPageAllocator; // dynamically allocated - Init2 |
|
612 |
//iAsyncFreeList; // dynamically allocated - Init2 |
|
613 |
//iPageTableAllocator; // dynamically allocated - Init2 |
|
614 |
//iPageTableLinearAllocator;// dynamically allocated - Init2 |
|
615 |
iPtInfoPtePerm=KPtInfoPtePerm; |
|
616 |
iPtPtePerm=KPtPtePerm; |
|
617 |
iPtPdePerm=KPtPdePerm; |
|
618 |
iTempAddr=KTempAddr; |
|
619 |
iSecondTempAddr=KSecondTempAddr; |
|
620 |
iMapSizes=KPageSize|KLargePageSize|KChunkSize; |
|
621 |
iRomLinearBase = ::RomHeaderAddress; |
|
622 |
iRomLinearEnd = KRomLinearEnd; |
|
623 |
iShadowPtePerm = KShadowPtePerm; |
|
624 |
iShadowPdePerm = KShadowPdePerm; |
|
625 |
||
626 |
// Mmu data |
|
627 |
TInt total_ram=TheSuperPage().iTotalRamSize; |
|
628 |
||
629 |
#if defined(__HAS_EXTERNAL_CACHE__) |
|
630 |
//L2 cache on ARMv5 is always in write-back mode => must be always purged |
|
631 |
iDecommitThreshold = CacheMaintenance::SyncAllPerformanceThresholdPages(); |
|
632 |
#else |
|
633 |
iDecommitThreshold = 0; ///no cache consistency issues on decommit |
|
634 |
#endif |
|
635 |
||
636 |
iDataSectionBase = KDataSectionBase; |
|
637 |
iDataSectionEnd = KDataSectionEnd; |
|
638 |
iMaxDllDataSize=Min(total_ram/2, 0x08000000); // phys RAM/2 up to 128Mb |
|
639 |
iMaxDllDataSize=(iMaxDllDataSize+iChunkMask)&~iChunkMask; // round up to chunk size |
|
640 |
iMaxUserCodeSize=Min(total_ram, 0x10000000); // phys RAM up to 256Mb |
|
641 |
iMaxUserCodeSize=(iMaxUserCodeSize+iChunkMask)&~iChunkMask; // round up to chunk size |
|
642 |
iMaxKernelCodeSize=Min(total_ram/2, 0x04000000); // phys RAM/2 up to 64Mb |
|
643 |
iMaxKernelCodeSize=(iMaxKernelCodeSize+iChunkMask)&~iChunkMask; // round up to chunk size |
|
644 |
iPdeBase=KPageDirectoryBase; |
|
645 |
iUserCodeLoadPtePerm=KUserCodeLoadPte; |
|
646 |
iKernelCodePtePerm=KKernelCodeRunPte; |
|
647 |
iDllDataBase = KDataSectionEnd - iMaxDllDataSize; |
|
648 |
iUserCodeBase = KPageInfoLinearBase - iMaxUserCodeSize; |
|
649 |
iKernelCodeBase = iUserCodeBase - iMaxKernelCodeSize; |
|
650 |
||
651 |
__KTRACE_OPT(KMMU,Kern::Printf("DDS %08x UCS %08x KCS %08x", iMaxDllDataSize, iMaxUserCodeSize, iMaxKernelCodeSize));
|
|
652 |
__KTRACE_OPT(KMMU,Kern::Printf("DDB %08x KCB %08x UCB %08x RLB %08x", iDllDataBase, iKernelCodeBase, iUserCodeBase, iRomLinearBase));
|
|
653 |
||
654 |
// ArmMmu data |
|
655 |
||
656 |
// other |
|
657 |
PP::MaxUserThreadStack=0x14000; // 80K - STDLIB asks for 64K for PosixServer!!!! |
|
658 |
PP::UserThreadStackGuard=0x2000; // 8K |
|
659 |
PP::MaxStackSpacePerProcess=0x200000; // 2Mb |
|
660 |
K::SupervisorThreadStackSize=0x1000; // 4K |
|
661 |
PP::SupervisorThreadStackGuard=0x1000; // 4K |
|
662 |
K::MachineConfig=(TMachineConfig*)KMachineConfigLinAddr; |
|
663 |
PP::RamDriveStartAddress=KRamDriveStartAddress; |
|
664 |
PP::RamDriveRange=KRamDriveMaxSize; |
|
665 |
PP::RamDriveMaxSize=KRamDriveMaxSize; // may be reduced later |
|
666 |
||
667 |
__KTRACE_OPT(KBOOT,Kern::Printf("K::MaxMemCopyInOneGo=0x%x",K::MaxMemCopyInOneGo));
|
|
668 |
K::MemModelAttributes=EMemModelTypeMoving|EMemModelAttrNonExProt|EMemModelAttrKernProt|EMemModelAttrWriteProt| |
|
669 |
EMemModelAttrVA|EMemModelAttrProcessProt|EMemModelAttrSameVA|EMemModelAttrSupportFixed| |
|
670 |
EMemModelAttrSvKernProt|EMemModelAttrIPCKernProt; |
|
671 |
||
672 |
Arm::DefaultDomainAccess=KDefaultDomainAccess; |
|
673 |
||
674 |
// Domains 0-3 are preallocated |
|
675 |
// 0=Variable user running, 1=Client, 2=Page tables, 3=RAM drive |
|
676 |
Domains=(~(0xffffffffu<<ENumDomains))&0xfffffff0u; |
|
677 |
||
678 |
iMaxPageTables = 1<<(32-KChunkShift); // possibly reduced when RAM size known |
|
679 |
||
680 |
Mmu::Init1(); |
|
681 |
} |
|
682 |
||
683 |
void ArmMmu::DoInit2() |
|
684 |
{
|
|
685 |
__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("ArmMmu::DoInit2"));
|
|
686 |
iTempPte=PageTable(GetPageTableId(iTempAddr))+((iTempAddr&KChunkMask)>>KPageShift); |
|
687 |
iSecondTempPte=PageTable(GetPageTableId(iSecondTempAddr))+((iSecondTempAddr&KChunkMask)>>KPageShift); |
|
688 |
__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("iTempAddr=%08x, iTempPte=%08x, iSecondTempAddr=%08x, iSecondTempPte=%08x", iTempAddr, iTempPte, iSecondTempAddr, iSecondTempPte));
|
|
689 |
CreateKernelSection(iKernelCodeBase, KPageShift); |
|
690 |
iHomePdeMap=(TUint32*)Kern::AllocZ(-KSuperPageLinAddr>>KChunkShift<<2); |
|
691 |
iHomePdeMap=(TUint32*)((TUint32)iHomePdeMap-(KSuperPageLinAddr>>KChunkShift<<2)); //adjust the pointer so it's indexed by address>>20 |
|
692 |
#if defined(__CPU_WRITE_BACK_CACHE) |
|
693 |
#if defined(__CPU_HAS_SINGLE_ENTRY_DCACHE_FLUSH) |
|
694 |
if (InternalCache::Info[KCacheInfoD].iLineLength == 32) |
|
695 |
iCopyPageFn = &::CopyPageForRemap32; |
|
696 |
else if (InternalCache::Info[KCacheInfoD].iLineLength == 16) |
|
697 |
iCopyPageFn = &::CopyPageForRemap16; |
|
698 |
else |
|
699 |
Panic(ENoCopyPageFunction); |
|
700 |
#else |
|
701 |
#error Write-back cache without single entry dcache flush is not supported |
|
702 |
#endif |
|
703 |
#else // !__CPU_HAS_WRITE_BACK_CACHE |
|
704 |
iCopyPageFn = &::CopyPageForRemapWT; |
|
705 |
#endif |
|
706 |
Mmu::DoInit2(); |
|
707 |
} |
|
708 |
||
709 |
#ifndef __MMU_MACHINE_CODED__ |
|
710 |
void ArmMmu::MapRamPages(TInt aId, SPageInfo::TType aType, TAny* aPtr, TUint32 aOffset, const TPhysAddr* aPageList, TInt aNumPages, TPte aPtePerm) |
|
711 |
// |
|
712 |
// Map a list of physical RAM pages into a specified page table with specified PTE permissions. |
|
713 |
// Update the page information array. |
|
714 |
// Call this with the system locked. |
|
715 |
// |
|
716 |
{
|
|
717 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::MapRamPages() id=%d type=%d ptr=%08x off=%08x n=%d perm=%08x",
|
|
718 |
aId, aType, aPtr, aOffset, aNumPages, aPtePerm)); |
|
719 |
||
720 |
SPageTableInfo& ptinfo=iPtInfo[aId]; |
|
721 |
ptinfo.iCount+=aNumPages; |
|
722 |
aOffset>>=KPageShift; |
|
723 |
TInt ptOffset=aOffset & KPagesInPDEMask; // entry number in page table |
|
724 |
TPte* pPte=PageTable(aId)+ptOffset; // address of first PTE |
|
725 |
while(aNumPages--) |
|
726 |
{
|
|
727 |
TPhysAddr pa = *aPageList++; |
|
728 |
*pPte++ = pa | aPtePerm; // insert PTE |
|
729 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PTE %08x to %08x",pPte[-1],pPte-1));
|
|
730 |
if (aType!=SPageInfo::EInvalid) |
|
731 |
{
|
|
732 |
SPageInfo* pi = SPageInfo::SafeFromPhysAddr(pa); |
|
733 |
if(pi) |
|
734 |
{
|
|
735 |
pi->Set(aType,aPtr,aOffset); |
|
736 |
__KTRACE_OPT(KMMU,Kern::Printf("I: %d %08x %08x",aType,aPtr,aOffset));
|
|
737 |
++aOffset; // increment offset for next page |
|
738 |
} |
|
739 |
} |
|
740 |
} |
|
741 |
__DRAIN_WRITE_BUFFER; |
|
742 |
} |
|
743 |
||
744 |
void ArmMmu::MapPhysicalPages(TInt aId, SPageInfo::TType aType, TAny* aPtr, TUint32 aOffset, TPhysAddr aPhysAddr, TInt aNumPages, TPte aPtePerm) |
|
745 |
// |
|
746 |
// Map consecutive physical pages into a specified page table with specified PTE permissions. |
|
747 |
// Update the page information array if RAM pages are being mapped. |
|
748 |
// Call this with the system locked. |
|
749 |
// |
|
750 |
{
|
|
751 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::MapPhysicalPages() id=%d type=%d ptr=%08x off=%08x phys=%08x n=%d perm=%08x",
|
|
752 |
aId, aType, aPtr, aOffset, aPhysAddr, aNumPages, aPtePerm)); |
|
753 |
SPageTableInfo& ptinfo=iPtInfo[aId]; |
|
754 |
ptinfo.iCount+=aNumPages; |
|
755 |
aOffset>>=KPageShift; |
|
756 |
TInt ptOffset=aOffset & KPagesInPDEMask; // entry number in page table |
|
757 |
TPte* pPte=PageTable(aId)+ptOffset; // address of first PTE |
|
758 |
SPageInfo* pi; |
|
759 |
if(aType==SPageInfo::EInvalid) |
|
760 |
pi = NULL; |
|
761 |
else |
|
762 |
pi = SPageInfo::SafeFromPhysAddr(aPhysAddr); |
|
763 |
while(aNumPages--) |
|
764 |
{
|
|
765 |
*pPte++ = aPhysAddr|aPtePerm; // insert PTE |
|
766 |
aPhysAddr+=KPageSize; |
|
767 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PTE %08x to %08x",pPte[-1],pPte-1));
|
|
768 |
if (pi) |
|
769 |
{
|
|
770 |
pi->Set(aType,aPtr,aOffset); |
|
771 |
__KTRACE_OPT(KMMU,Kern::Printf("I: %d %08x %08x",aType,aPtr,aOffset));
|
|
772 |
++aOffset; // increment offset for next page |
|
773 |
++pi; |
|
774 |
} |
|
775 |
} |
|
776 |
__DRAIN_WRITE_BUFFER; |
|
777 |
} |
|
778 |
||
779 |
void ArmMmu::MapVirtual(TInt aId, TInt aNumPages) |
|
780 |
// |
|
781 |
// Called in place of MapRamPages or MapPhysicalPages to update mmu data structures when committing |
|
782 |
// virtual address space to a chunk. No pages are mapped. |
|
783 |
// Call this with the system locked. |
|
784 |
// |
|
785 |
{
|
|
786 |
SPageTableInfo& ptinfo=iPtInfo[aId]; |
|
787 |
ptinfo.iCount+=aNumPages; |
|
788 |
} |
|
789 |
||
790 |
void ArmMmu::RemapPage(TInt aId, TUint32 aAddr, TPhysAddr aOldAddr, TPhysAddr aNewAddr, TPte aPtePerm, DProcess* /*aProcess*/) |
|
791 |
// |
|
792 |
// Replace the mapping at address aAddr in page table aId. |
|
793 |
// Update the page information array for both the old and new pages. |
|
794 |
// Call this with the system locked. |
|
795 |
// |
|
796 |
{
|
|
|
8
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
797 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::RemapPage() id=%d addr=%08x old=%08x new=%08x perm=%08x", aId, aAddr, aOldAddr, aNewAddr, aPtePerm));
|
| 0 | 798 |
|
799 |
TInt ptOffset=(aAddr&KChunkMask)>>KPageShift; // entry number in page table |
|
800 |
TPte* pPte=PageTable(aId)+ptOffset; // address of PTE |
|
801 |
TPte pte=*pPte; |
|
802 |
||
803 |
TUint pageType = (pte & KPteTypeMask); |
|
804 |
if (pageType == KArmPteSmallPage || pageType == 0) |
|
805 |
{
|
|
806 |
__ASSERT_ALWAYS((pte & KPteSmallPageAddrMask) == aOldAddr || pte==KPteNotPresentEntry, Panic(ERemapPageFailed)); |
|
807 |
SPageInfo* oldpi = SPageInfo::FromPhysAddr(aOldAddr); |
|
808 |
__ASSERT_DEBUG(oldpi->LockCount()==0,Panic(ERemapPageFailed)); |
|
809 |
||
810 |
// remap page |
|
811 |
*pPte = aNewAddr | aPtePerm; // overwrite PTE |
|
812 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PTE %08x to %08x",*pPte,pPte));
|
|
813 |
__DRAIN_WRITE_BUFFER; |
|
814 |
InvalidateTLBForPage(aAddr); // flush any corresponding TLB entry |
|
815 |
||
816 |
// update new pageinfo, clear old |
|
817 |
SPageInfo* pi = SPageInfo::FromPhysAddr(aNewAddr); |
|
818 |
pi->Set(oldpi->Type(),oldpi->Owner(),oldpi->Offset()); |
|
819 |
oldpi->SetUnused(); |
|
820 |
} |
|
821 |
else |
|
822 |
{
|
|
|
8
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
823 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::RemapPage() called on a non-4K page!"));
|
| 0 | 824 |
Panic(ERemapPageFailed); |
825 |
} |
|
826 |
} |
|
827 |
||
828 |
void ArmMmu::RemapKernelPage(TInt aId, TLinAddr aSrc, TLinAddr aDest, TPhysAddr aNewPhys, TPte aPtePerm) |
|
829 |
// |
|
830 |
// Replace the mapping at address aAddr in page table aId. |
|
831 |
// Called with the system locked. |
|
832 |
// MUST NOT INVOKE ANY TRACING - or do anything else that might touch the kernel heap |
|
833 |
// We are depending on this not reintroducing any of the cache lines we previously |
|
834 |
// invalidated. |
|
835 |
// |
|
836 |
{
|
|
837 |
TInt ptOffset=(aSrc&KChunkMask)>>KPageShift; // entry number in page table |
|
838 |
TPte* pPte=PageTable(aId)+ptOffset; // address of PTE |
|
839 |
||
840 |
TInt irq = NKern::DisableAllInterrupts(); |
|
841 |
CopyPageForRemap(aDest, aSrc); |
|
842 |
*pPte = aNewPhys | aPtePerm; // overwrite PTE |
|
843 |
__DRAIN_WRITE_BUFFER; |
|
844 |
InvalidateTLBForPage(aSrc); // flush any corresponding TLB entry |
|
845 |
NKern::RestoreInterrupts(irq); |
|
846 |
} |
|
847 |
||
848 |
TInt ArmMmu::UnmapPages(TInt aId, TUint32 aAddr, TInt aNumPages, TPhysAddr* aPageList, TBool aSetPagesFree, TInt& aNumPtes, TInt& aNumFree, DProcess*) |
|
849 |
// |
|
850 |
// Unmap a specified area at address aAddr in page table aId. Place physical addresses of unmapped |
|
851 |
// pages into aPageList, and count of unmapped pages into aNumPtes. |
|
852 |
// Return number of pages still mapped using this page table. |
|
853 |
// Call this with the system locked. |
|
854 |
// @param aId Identifies Page Table to unmap PTEs(Page Table Entries) from. |
|
855 |
// @param aAddr Base Base Virtual Address of the region to unmap. It (indirectly) specifies the first PTE in this Page Table to unmap. |
|
856 |
// @param aNumPages The number of consecutive PTEs to unmap. |
|
857 |
// @param aPageList Points to pre-allocated array. On return, it is filled in with the list of physical addresses of the unmapped 4K |
|
858 |
// memory blocks. |
|
859 |
// @param aSetPagesFree If true, pages a placed in the free state and only mapped pages are added |
|
860 |
// to aPageList. |
|
861 |
// @param aNumPtes On return, indicates how many PTEs are unmapped. |
|
862 |
// @param aNumFree On return, holds the number are freed 4K memory blocks. Not updated if aSetPagesFree is false. |
|
863 |
// @return The number of PTEs still mapped in this Page Table (aId). |
|
864 |
{
|
|
865 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::UnmapPages() id=%d addr=%08x n=%d pl=%08x set-free=%d",aId,aAddr,aNumPages,aPageList,aSetPagesFree));
|
|
866 |
TInt ptOffset=(aAddr&KChunkMask)>>KPageShift; // entry number in page table |
|
867 |
TPte* pPte=PageTable(aId)+ptOffset; // address of first PTE |
|
868 |
TInt np=0; |
|
869 |
TInt nf=0; |
|
870 |
while(aNumPages--) |
|
871 |
{
|
|
872 |
TPte pte=*pPte; // get original PTE |
|
873 |
*pPte++=0; // clear PTE |
|
874 |
TUint pageType = (pte & KPteTypeMask); |
|
875 |
if (pageType == KArmPteSmallPage) |
|
876 |
InvalidateTLBForPage(aAddr); // flush any corresponding TLB entry |
|
877 |
if (pageType == KArmPteSmallPage || (pageType == 0 && pte != KPteNotPresentEntry)) |
|
878 |
{
|
|
879 |
++np; // count unmapped pages |
|
880 |
TPhysAddr pa=pte & KPteSmallPageAddrMask; // physical address of unmapped page |
|
881 |
if (aSetPagesFree) |
|
882 |
{
|
|
883 |
SPageInfo* pi = SPageInfo::FromPhysAddr(pa); |
|
884 |
__NK_ASSERT_DEBUG(pageType == KArmPteSmallPage || |
|
885 |
(pi->Type()==SPageInfo::EPagedCode && pi->State()==SPageInfo::EStatePagedOld)); |
|
886 |
if(iRamCache->PageUnmapped(pi)) |
|
887 |
{
|
|
888 |
pi->SetUnused(); // mark page as unused |
|
889 |
if (pi->LockCount()==0) |
|
890 |
{
|
|
891 |
*aPageList++=pa; // store in page list |
|
892 |
++nf; // count free pages |
|
893 |
} |
|
894 |
} |
|
895 |
} |
|
896 |
else |
|
897 |
*aPageList++=pa; // store in page list |
|
898 |
} |
|
899 |
aAddr+=KPageSize; |
|
900 |
} |
|
901 |
aNumPtes=np; |
|
902 |
aNumFree=nf; |
|
903 |
SPageTableInfo& ptinfo=iPtInfo[aId]; |
|
904 |
TInt r=(ptinfo.iCount-=np); |
|
905 |
__DRAIN_WRITE_BUFFER; |
|
906 |
__KTRACE_OPT(KMMU,Kern::Printf("Unmapped %d; Freed: %d; Return %08x",np,nf,r));
|
|
907 |
return r; // return number of pages remaining in this page table |
|
908 |
} |
|
909 |
#endif |
|
910 |
||
911 |
TInt ArmMmu::UnmapVirtual(TInt aId, TUint32 aAddr, TInt aNumPages, TPhysAddr* aPageList, TBool aSetPagesFree, TInt& aNumPtes, TInt& aNumFree, DProcess* aProcess) |
|
912 |
// |
|
913 |
// Unmap a specified area at address aAddr in page table aId. Place physical addresses of unmapped |
|
914 |
// pages into aPageList, and count of unmapped pages into aNumPtes. |
|
915 |
// Adjust the page table reference count as if aNumPages pages were unmapped. |
|
916 |
// Return number of pages still mapped using this page table. |
|
917 |
// Call this with the system locked. |
|
918 |
// |
|
919 |
{
|
|
920 |
SPageTableInfo& ptinfo=iPtInfo[aId]; |
|
921 |
TInt newCount = ptinfo.iCount - aNumPages; |
|
922 |
UnmapPages(aId, aAddr, aNumPages, aPageList, aSetPagesFree, aNumPtes, aNumFree, aProcess); |
|
923 |
ptinfo.iCount = newCount; |
|
924 |
aNumPtes = aNumPages; |
|
925 |
return newCount; |
|
926 |
} |
|
927 |
||
928 |
||
929 |
#ifndef __MMU_MACHINE_CODED__ |
|
930 |
void ArmMmu::DoAssignPageTable(TInt aId, TLinAddr aAddr, TPde aPdePerm) |
|
931 |
// |
|
932 |
// Assign an allocated page table to map a given linear address with specified permissions. |
|
933 |
// This should be called with the system locked and the MMU mutex held. |
|
934 |
// |
|
935 |
{
|
|
936 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::DoAssignPageTable %d to %08x perm %08x",aId,aAddr,aPdePerm));
|
|
937 |
TLinAddr ptLin=PageTableLinAddr(aId); |
|
938 |
TPhysAddr ptPhys=LinearToPhysical(ptLin); |
|
939 |
TInt pdeIndex=TInt(aAddr>>KChunkShift); |
|
940 |
PageDirectory[pdeIndex]=ptPhys|aPdePerm; |
|
941 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PDE %08x to %08x", ptPhys|aPdePerm, PageDirectory+pdeIndex));
|
|
942 |
__DRAIN_WRITE_BUFFER; |
|
943 |
} |
|
944 |
||
945 |
void ArmMmu::RemapPageTable(TPhysAddr aOld, TPhysAddr aNew, TLinAddr aAddr) |
|
946 |
// |
|
947 |
// Replace a page table mapping the specified linear address. |
|
948 |
// This should be called with the system locked and the MMU mutex held. |
|
949 |
// |
|
950 |
{
|
|
951 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::RemapPageTable %08x to %08x at %08x",aOld,aNew,aAddr));
|
|
952 |
TInt pdeIndex=TInt(aAddr>>KChunkShift); |
|
953 |
TPde pde=PageDirectory[pdeIndex]; |
|
954 |
__ASSERT_ALWAYS((pde & KPdePageTableAddrMask) == aOld, Panic(ERemapPageTableFailed)); |
|
955 |
TPde newPde=aNew|(pde&~KPdePageTableAddrMask); |
|
956 |
PageDirectory[pdeIndex]=newPde; |
|
957 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PDE %08x to %08x", newPde, PageDirectory+pdeIndex));
|
|
958 |
__DRAIN_WRITE_BUFFER; |
|
959 |
} |
|
960 |
||
961 |
void ArmMmu::DoUnassignPageTable(TLinAddr aAddr) |
|
962 |
// |
|
963 |
// Unassign a now-empty page table currently mapping the specified linear address. |
|
964 |
// We assume that TLB and/or cache flushing has been done when any RAM pages were unmapped. |
|
965 |
// This should be called with the system locked and the MMU mutex held. |
|
966 |
// |
|
967 |
{
|
|
968 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::DoUnassignPageTable at %08x",aAddr));
|
|
969 |
TInt pdeIndex=TInt(aAddr>>KChunkShift); |
|
970 |
PageDirectory[pdeIndex]=0; |
|
971 |
__KTRACE_OPT(KMMU,Kern::Printf("Clearing PDE at %08x", PageDirectory+pdeIndex));
|
|
972 |
__DRAIN_WRITE_BUFFER; |
|
973 |
} |
|
974 |
#endif |
|
975 |
||
976 |
// Initialise page table at physical address aXptPhys to be used as page table aXptId |
|
977 |
// to expand the virtual address range used for mapping page tables. Map the page table |
|
978 |
// at aPhysAddr as page table aId using the expanded range. |
|
979 |
// Assign aXptPhys to kernel's Page Directory. |
|
980 |
// Called with system unlocked and MMU mutex held. |
|
981 |
void ArmMmu::BootstrapPageTable(TInt aXptId, TPhysAddr aXptPhys, TInt aId, TPhysAddr aPhysAddr) |
|
982 |
{
|
|
983 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::BootstrapPageTable xptid=%04x, xptphys=%08x, id=%04x, phys=%08x",
|
|
984 |
aXptId, aXptPhys, aId, aPhysAddr)); |
|
985 |
||
986 |
// put in a temporary mapping for aXptPhys |
|
987 |
// make it noncacheable |
|
988 |
TPhysAddr pa=aXptPhys&~KPageMask; |
|
989 |
*iTempPte = pa | SP_PTE(KArmV45PermRWNO, KMemAttNC); |
|
990 |
__DRAIN_WRITE_BUFFER; |
|
991 |
||
992 |
// clear XPT |
|
993 |
TPte* xpt=(TPte*)(iTempAddr+(aXptPhys&KPageMask)); |
|
994 |
memclr(xpt, KPageTableSize); |
|
995 |
||
996 |
// must in fact have aXptPhys and aPhysAddr in same physical page |
|
997 |
__ASSERT_ALWAYS( TUint32(aXptPhys^aPhysAddr)<TUint32(KPageSize), MM::Panic(MM::EBootstrapPageTableBadAddr)); |
|
998 |
||
999 |
// so only need one mapping |
|
1000 |
xpt[(aXptId>>KPtClusterShift)&KPagesInPDEMask] = pa | KPtPtePerm; |
|
1001 |
||
1002 |
// remove temporary mapping |
|
1003 |
*iTempPte=0; |
|
1004 |
__DRAIN_WRITE_BUFFER; |
|
1005 |
InvalidateTLBForPage(iTempAddr); |
|
1006 |
||
1007 |
// initialise PtInfo... |
|
1008 |
TLinAddr xptAddr = PageTableLinAddr(aXptId); |
|
1009 |
iPtInfo[aXptId].SetGlobal(xptAddr>>KChunkShift); |
|
1010 |
||
1011 |
// map xpt... |
|
1012 |
TInt pdeIndex=TInt(xptAddr>>KChunkShift); |
|
1013 |
NKern::LockSystem(); |
|
1014 |
PageDirectory[pdeIndex]=aXptPhys|KPtPdePerm; |
|
1015 |
__DRAIN_WRITE_BUFFER; |
|
1016 |
NKern::UnlockSystem(); |
|
1017 |
} |
|
1018 |
||
1019 |
// Edit the self-mapping entry in page table aId, mapped at aTempMap, to |
|
1020 |
// change the physical address from aOld to aNew. Used when moving page |
|
1021 |
// tables which were created by BootstrapPageTable. |
|
1022 |
// Called with system locked and MMU mutex held. |
|
1023 |
void ArmMmu::FixupXPageTable(TInt aId, TLinAddr aTempMap, TPhysAddr aOld, TPhysAddr aNew) |
|
1024 |
{
|
|
1025 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::FixupXPageTable id=%04x, tempmap=%08x, old=%08x, new=%08x",
|
|
1026 |
aId, aTempMap, aOld, aNew)); |
|
1027 |
||
1028 |
// find correct page table inside the page |
|
1029 |
TPte* xpt=(TPte*)(aTempMap + ((aId & KPtClusterMask) << KPageTableShift)); |
|
1030 |
// find the pte in that page table |
|
1031 |
xpt += (aId>>KPtClusterShift)&KPagesInPDEMask; |
|
1032 |
||
1033 |
// switch the mapping |
|
1034 |
__ASSERT_ALWAYS((*xpt&~KPageMask)==aOld, Panic(EFixupXPTFailed)); |
|
1035 |
*xpt = aNew | KPtPtePerm; |
|
1036 |
||
1037 |
// invalidate the TLB entry for the self-mapping page table |
|
1038 |
// the PDE has not yet been changed, but since we hold the |
|
1039 |
// system lock, nothing should bring this back into the TLB. |
|
1040 |
InvalidateTLBForPage(PageTableLinAddr(aId)); |
|
1041 |
} |
|
1042 |
||
1043 |
// Set up a page table (specified by aId) to map a 1Mb section of ROM containing aRomAddr |
|
1044 |
// using ROM at aOrigPhys. |
|
1045 |
void ArmMmu::InitShadowPageTable(TInt aId, TLinAddr aRomAddr, TPhysAddr aOrigPhys) |
|
1046 |
{
|
|
1047 |
__KTRACE_OPT(KMMU, Kern::Printf("ArmMmu:InitShadowPageTable id=%04x aRomAddr=%08x aOrigPhys=%08x",
|
|
1048 |
aId, aRomAddr, aOrigPhys)); |
|
1049 |
TPte* ppte = PageTable(aId); |
|
1050 |
TPte* ppte_End = ppte + KChunkSize/KPageSize; |
|
1051 |
TPhysAddr phys = aOrigPhys - (aRomAddr & KChunkMask); |
|
1052 |
for (; ppte<ppte_End; ++ppte, phys+=KPageSize) |
|
1053 |
*ppte = phys | KRomPtePermissions; |
|
1054 |
__DRAIN_WRITE_BUFFER; |
|
1055 |
} |
|
1056 |
||
1057 |
// Copy the contents of ROM at aRomAddr to a shadow page at physical address aShadowPhys |
|
1058 |
void ArmMmu::InitShadowPage(TPhysAddr aShadowPhys, TLinAddr aRomAddr) |
|
1059 |
{
|
|
1060 |
__KTRACE_OPT(KMMU, Kern::Printf("ArmMmu:InitShadowPage aShadowPhys=%08x aRomAddr=%08x",
|
|
1061 |
aShadowPhys, aRomAddr)); |
|
1062 |
||
1063 |
// put in a temporary mapping for aShadowPhys |
|
1064 |
// make it noncacheable |
|
1065 |
*iTempPte = aShadowPhys | SP_PTE(KArmV45PermRWNO, KMemAttNC); |
|
1066 |
__DRAIN_WRITE_BUFFER; |
|
1067 |
||
1068 |
// copy contents of ROM |
|
1069 |
wordmove( (TAny*)iTempAddr, (const TAny*)aRomAddr, KPageSize ); |
|
1070 |
__DRAIN_WRITE_BUFFER; // make sure contents are written to memory |
|
1071 |
||
1072 |
// remove temporary mapping |
|
1073 |
*iTempPte=0; |
|
1074 |
__DRAIN_WRITE_BUFFER; |
|
1075 |
InvalidateTLBForPage(iTempAddr); |
|
1076 |
} |
|
1077 |
||
1078 |
// Assign a shadow page table to replace a ROM section mapping |
|
1079 |
// Enter and return with system locked |
|
1080 |
void ArmMmu::AssignShadowPageTable(TInt aId, TLinAddr aRomAddr) |
|
1081 |
{
|
|
1082 |
__KTRACE_OPT(KMMU, Kern::Printf("ArmMmu:AssignShadowPageTable aId=%04x aRomAddr=%08x",
|
|
1083 |
aId, aRomAddr)); |
|
1084 |
TLinAddr ptLin=PageTableLinAddr(aId); |
|
1085 |
TPhysAddr ptPhys=LinearToPhysical(ptLin); |
|
1086 |
TPde* ppde = PageDirectory + (aRomAddr>>KChunkShift); |
|
1087 |
TPde newpde = ptPhys | KShadowPdePerm; |
|
1088 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PDE %08x to %08x", newpde, ppde));
|
|
1089 |
TInt irq=NKern::DisableAllInterrupts(); |
|
1090 |
*ppde = newpde; // map in the page table |
|
1091 |
__DRAIN_WRITE_BUFFER; // make sure new PDE written to main memory |
|
1092 |
FlushTLBs(); // flush both TLBs (no need to flush cache yet) |
|
1093 |
NKern::RestoreInterrupts(irq); |
|
1094 |
} |
|
1095 |
||
1096 |
void ArmMmu::DoUnmapShadowPage(TInt aId, TLinAddr aRomAddr, TPhysAddr aOrigPhys) |
|
1097 |
{
|
|
1098 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu:DoUnmapShadowPage, id=%04x lin=%08x origphys=%08x", aId, aRomAddr, aOrigPhys));
|
|
1099 |
TPte* ppte = PageTable(aId) + ((aRomAddr & KChunkMask)>>KPageShift); |
|
1100 |
TPte newpte = aOrigPhys | KRomPtePermissions; |
|
1101 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PTE %08x to %08x", newpte, ppte));
|
|
1102 |
TInt irq=NKern::DisableAllInterrupts(); |
|
1103 |
*ppte = newpte; |
|
1104 |
__DRAIN_WRITE_BUFFER; |
|
1105 |
InvalidateTLBForPage(aRomAddr); |
|
1106 |
SyncCodeMappings(); |
|
1107 |
CacheMaintenance::CodeChanged(aRomAddr, KPageSize, CacheMaintenance::EMemoryRemap); |
|
1108 |
CacheMaintenance::PageToReuse(aRomAddr, EMemAttNormalCached, KPhysAddrInvalid); |
|
1109 |
NKern::RestoreInterrupts(irq); |
|
1110 |
} |
|
1111 |
||
1112 |
TInt ArmMmu::UnassignShadowPageTable(TLinAddr aRomAddr, TPhysAddr aOrigPhys) |
|
1113 |
{
|
|
1114 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu:UnassignShadowPageTable, lin=%08x origphys=%08x", aRomAddr, aOrigPhys));
|
|
1115 |
TPde* ppde = PageDirectory + (aRomAddr>>KChunkShift); |
|
1116 |
TPde newpde = (aOrigPhys &~ KChunkMask) | KRomSectionPermissions; |
|
1117 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PDE %08x to %08x", newpde, ppde));
|
|
1118 |
TInt irq=NKern::DisableAllInterrupts(); |
|
1119 |
*ppde = newpde; // revert to section mapping |
|
1120 |
__DRAIN_WRITE_BUFFER; // make sure new PDE written to main memory |
|
1121 |
FlushTLBs(); // flush both TLBs |
|
1122 |
NKern::RestoreInterrupts(irq); |
|
1123 |
return KErrNone; |
|
1124 |
} |
|
1125 |
||
1126 |
void ArmMmu::DoFreezeShadowPage(TInt aId, TLinAddr aRomAddr) |
|
1127 |
{
|
|
1128 |
__KTRACE_OPT(KMMU, Kern::Printf("ArmMmu:DoFreezeShadowPage aId=%04x aRomAddr=%08x",
|
|
1129 |
aId, aRomAddr)); |
|
1130 |
TPte* ppte = PageTable(aId) + ((aRomAddr & KChunkMask)>>KPageShift); |
|
1131 |
TPte newpte = (*ppte & KPteSmallPageAddrMask) | KRomPtePermissions; |
|
1132 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PTE %08x to %08x", newpte, ppte));
|
|
1133 |
*ppte = newpte; |
|
1134 |
__DRAIN_WRITE_BUFFER; |
|
1135 |
InvalidateTLBForPage(aRomAddr); |
|
1136 |
} |
|
1137 |
||
1138 |
void ArmMmu::Pagify(TInt aId, TLinAddr aLinAddr) |
|
1139 |
{
|
|
1140 |
__KTRACE_OPT(KMMU, Kern::Printf("ArmMmu:Pagify aId=%04x aLinAddr=%08x", aId, aLinAddr));
|
|
1141 |
||
1142 |
TInt pteIndex = (aLinAddr & KChunkMask)>>KPageShift; |
|
1143 |
TPte* pte = PageTable(aId); |
|
1144 |
if ((pte[pteIndex] & KPteTypeMask) == KArmV45PteLargePage) |
|
1145 |
{
|
|
1146 |
__KTRACE_OPT(KMMU,Kern::Printf("Converting 64K page to 4K pages"));
|
|
1147 |
pteIndex &= ~0xf; |
|
1148 |
TPte source = pte[pteIndex]; |
|
1149 |
source = (source & KPteLargePageAddrMask) | SP_PTE_FROM_LP_PTE(source); |
|
1150 |
pte += pteIndex; |
|
1151 |
for (TInt entry=0; entry<16; entry++) |
|
1152 |
{
|
|
1153 |
pte[entry] = source | (entry<<12); |
|
1154 |
} |
|
1155 |
FlushTLBs(); |
|
1156 |
} |
|
1157 |
} |
|
1158 |
||
1159 |
void ArmMmu::FlushShadow(TLinAddr aRomAddr) |
|
1160 |
{
|
|
1161 |
CacheMaintenance::CodeChanged(aRomAddr, KPageSize, CacheMaintenance::EMemoryRemap); |
|
1162 |
CacheMaintenance::PageToReuse(aRomAddr, EMemAttNormalCached, KPhysAddrInvalid); |
|
1163 |
InvalidateTLBForPage(aRomAddr); // remove all TLB references to original ROM page |
|
1164 |
SyncCodeMappings(); |
|
1165 |
} |
|
1166 |
||
1167 |
||
1168 |
inline void ZeroPdes(TLinAddr aBase, TLinAddr aEnd) |
|
1169 |
{
|
|
1170 |
memclr(PageDirectory+(aBase>>KChunkShift), ((aEnd-aBase)>>KChunkShift)*sizeof(TPde)); |
|
1171 |
} |
|
1172 |
||
1173 |
void ArmMmu::ClearPageTable(TInt aId, TInt aFirstIndex) |
|
1174 |
{
|
|
1175 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::ClearPageTable(%d,%d)",aId,aFirstIndex));
|
|
1176 |
TPte* pte=PageTable(aId); |
|
1177 |
memclr(pte+aFirstIndex, KPageTableSize-aFirstIndex*sizeof(TPte)); |
|
1178 |
__DRAIN_WRITE_BUFFER; |
|
1179 |
} |
|
1180 |
||
1181 |
void ArmMmu::ClearRamDrive(TLinAddr aStart) |
|
1182 |
{
|
|
1183 |
// clear the page directory entries corresponding to the RAM drive |
|
1184 |
ZeroPdes(aStart, KRamDriveEndAddress); |
|
1185 |
__DRAIN_WRITE_BUFFER; |
|
1186 |
} |
|
1187 |
||
1188 |
void ArmMmu::ApplyTopLevelPermissions(TLinAddr aAddr, TUint aChunkSize, TPde aPdePerm) |
|
1189 |
{
|
|
1190 |
__KTRACE_OPT(KMMU,Kern::Printf("ApplyTopLevelPermissions at %x",aAddr));
|
|
1191 |
TInt pdeIndex=aAddr>>KChunkShift; |
|
1192 |
TInt numPdes=(aChunkSize+KChunkMask)>>KChunkShift; |
|
1193 |
TPde* pPde=PageDirectory+pdeIndex; |
|
1194 |
while(numPdes--) |
|
1195 |
{
|
|
1196 |
*pPde=(*pPde)?((*pPde & KPdePageTableAddrMask)|aPdePerm):0; |
|
1197 |
pPde++; |
|
1198 |
} |
|
1199 |
__DRAIN_WRITE_BUFFER; |
|
1200 |
} |
|
1201 |
||
1202 |
void ArmMmu::ApplyPagePermissions(TInt aId, TInt aPageOffset, TInt aNumPages, TPte aPtePerm) |
|
1203 |
{
|
|
1204 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::ApplyPagePermissions %04x:%03x+%03x perm %08x",
|
|
1205 |
aId, aPageOffset, aNumPages, aPtePerm)); |
|
1206 |
TPte* pPte=PageTable(aId)+aPageOffset; |
|
1207 |
TPde* pPteEnd=pPte+aNumPages; |
|
1208 |
NKern::LockSystem(); |
|
1209 |
for (; pPte<pPteEnd; ++pPte) |
|
1210 |
{
|
|
1211 |
TPte pte=*pPte; |
|
1212 |
if (pte) |
|
1213 |
*pPte = (pte&KPteSmallPageAddrMask)|aPtePerm; |
|
1214 |
} |
|
1215 |
NKern::UnlockSystem(); |
|
1216 |
FlushTLBs(); |
|
1217 |
__DRAIN_WRITE_BUFFER; |
|
1218 |
} |
|
1219 |
||
1220 |
void ArmMmu::MoveChunk(TLinAddr aInitAddr, TUint aSize, TLinAddr aFinalAddr, TPde aPdePerm) |
|
1221 |
{
|
|
1222 |
__KTRACE_OPT(KMMU,Kern::Printf("MoveChunk at %08x to %08x size %08x PdePerm %08x",
|
|
1223 |
aInitAddr, aFinalAddr, aSize, aPdePerm)); |
|
1224 |
TInt numPdes=(aSize+KChunkMask)>>KChunkShift; |
|
1225 |
TInt iS=aInitAddr>>KChunkShift; |
|
1226 |
TInt iD=aFinalAddr>>KChunkShift; |
|
1227 |
TPde* pS=PageDirectory+iS; |
|
1228 |
TPde* pD=PageDirectory+iD; |
|
1229 |
while(numPdes--) |
|
1230 |
{
|
|
1231 |
*pD++=(*pS)?((*pS & KPdePageTableAddrMask)|aPdePerm):0; |
|
1232 |
*pS++=KPdeNotPresentEntry; |
|
1233 |
} |
|
1234 |
__DRAIN_WRITE_BUFFER; |
|
1235 |
} |
|
1236 |
||
1237 |
void ArmMmu::MoveChunk(TLinAddr aInitAddr, TLinAddr aFinalAddr, TInt aNumPdes) |
|
1238 |
// |
|
1239 |
// Move a block of PDEs without changing permissions. Must work with overlapping initial and final |
|
1240 |
// regions. Call this with kernel locked. |
|
1241 |
// |
|
1242 |
{
|
|
1243 |
__KTRACE_OPT(KMMU,Kern::Printf("MoveChunk at %08x to %08x numPdes %d", aInitAddr, aFinalAddr, aNumPdes));
|
|
1244 |
if (aInitAddr==aFinalAddr || aNumPdes==0) |
|
1245 |
return; |
|
1246 |
TInt iS=aInitAddr>>KChunkShift; |
|
1247 |
TInt iD=aFinalAddr>>KChunkShift; |
|
1248 |
TBool forwardOverlap=(iS<iD && iD-iS<aNumPdes); |
|
1249 |
TBool backwardOverlap=(iS>iD && iS-iD<aNumPdes); |
|
1250 |
TInt iC=backwardOverlap?(iD+aNumPdes):iS; // first index to clear |
|
1251 |
TInt iZ=forwardOverlap?iD:(iS+aNumPdes); // last index to clear + 1 |
|
1252 |
TPde* pS=PageDirectory+iS; |
|
1253 |
TPde* pD=PageDirectory+iD; |
|
1254 |
__KTRACE_OPT(KMMU,Kern::Printf("backwardOverlap=%d, forwardOverlap=%d",backwardOverlap,forwardOverlap));
|
|
1255 |
__KTRACE_OPT(KMMU,Kern::Printf("first clear %03x, last clear %03x",iC,iZ));
|
|
1256 |
wordmove(pD,pS,aNumPdes<<2); // move PDEs |
|
1257 |
pD=PageDirectory+iC; // pointer to first PDE to clear |
|
1258 |
iZ-=iC; // number of PDEs to clear |
|
1259 |
memclr(pD, iZ<<2); // clear PDEs |
|
1260 |
__DRAIN_WRITE_BUFFER; |
|
1261 |
} |
|
1262 |
||
1263 |
TPde ArmMmu::PdePermissions(TChunkType aChunkType, TInt aChunkState) |
|
1264 |
{
|
|
1265 |
if ((aChunkType==EUserData || aChunkType==EDllData || aChunkType==EUserSelfModCode |
|
1266 |
|| aChunkType==ESharedKernelSingle || aChunkType==ESharedKernelMultiple || aChunkType==ESharedIo) |
|
1267 |
&& aChunkState!=0) |
|
1268 |
return KUserDataRunningPermissions; |
|
1269 |
return ChunkPdePermissions[aChunkType]; |
|
1270 |
} |
|
1271 |
||
1272 |
TPte ArmMmu::PtePermissions(TChunkType aChunkType) |
|
1273 |
{
|
|
1274 |
return ChunkPtePermissions[aChunkType]; |
|
1275 |
} |
|
1276 |
||
1277 |
const TUint FBLK=(EMapAttrFullyBlocking>>12); |
|
1278 |
const TUint BFNC=(EMapAttrBufferedNC>>12); |
|
1279 |
const TUint BUFC=(EMapAttrBufferedC>>12); |
|
1280 |
const TUint L1UN=(EMapAttrL1Uncached>>12); |
|
1281 |
const TUint WTRA=(EMapAttrCachedWTRA>>12); |
|
1282 |
const TUint WTWA=(EMapAttrCachedWTWA>>12); |
|
1283 |
const TUint WBRA=(EMapAttrCachedWBRA>>12); |
|
1284 |
const TUint WBWA=(EMapAttrCachedWBWA>>12); |
|
1285 |
const TUint AWTR=(EMapAttrAltCacheWTRA>>12); |
|
1286 |
const TUint AWTW=(EMapAttrAltCacheWTWA>>12); |
|
1287 |
const TUint AWBR=(EMapAttrAltCacheWBRA>>12); |
|
1288 |
const TUint AWBW=(EMapAttrAltCacheWBWA>>12); |
|
1289 |
const TUint MAXC=(EMapAttrL1CachedMax>>12); |
|
1290 |
||
1291 |
const TUint L2UN=(EMapAttrL2Uncached>>12); |
|
1292 |
||
1293 |
const TUint16 UNS=0xffffu; // Unsupported attribute |
|
1294 |
const TUint16 SPE=0xfffeu; // Special processing required |
|
1295 |
||
1296 |
#if defined(__CPU_ARM710T__) || defined(__CPU_ARM720T__) |
|
1297 |
// Original definition of C B |
|
1298 |
static const TUint16 CacheBuffAttributes[16]= |
|
1299 |
{0x00,0x00,0x04,0x04,0x0C,0x0C,0x0C,0x0C, UNS, UNS, UNS, UNS, UNS, UNS, UNS,0x0C};
|
|
1300 |
static const TUint8 CacheBuffActual[16]= |
|
1301 |
{FBLK,FBLK,BUFC,BUFC,WTRA,WTRA,WTRA,WTRA,FBLK,FBLK,FBLK,FBLK,FBLK,FBLK,FBLK,WTRA};
|
|
1302 |
||
1303 |
#elif defined(__CPU_ARM920T__) || defined(__CPU_ARM925T__) || defined(__CPU_ARM926J__) |
|
1304 |
// Newer definition of C B |
|
1305 |
static const TUint16 CacheBuffAttributes[16]= |
|
1306 |
{0x00,0x00,0x04,0x04,0x08,0x08,0x0C,0x0C, UNS, UNS, UNS, UNS, UNS, UNS, UNS,0x0C};
|
|
1307 |
static const TUint8 CacheBuffActual[16]= |
|
1308 |
{FBLK,FBLK,BUFC,BUFC,WTRA,WTRA,WBRA,WBRA,FBLK,FBLK,FBLK,FBLK,FBLK,FBLK,FBLK,WBRA};
|
|
1309 |
||
1310 |
#elif defined(__CPU_SA1__) |
|
1311 |
// Special definition of C B |
|
1312 |
static const TUint16 CacheBuffAttributes[16]= |
|
1313 |
{0x00,0x00,0x04,0x04,0x04,0x04,0x0C,0x0C,0x04,0x04,0x08,0x08, UNS, UNS, UNS,0x0C};
|
|
1314 |
static const TUint8 CacheBuffActual[16]= |
|
1315 |
{FBLK,FBLK,BUFC,BUFC,BUFC,BUFC,WBRA,WBRA,FBLK,FBLK,AWBR,AWBR,FBLK,FBLK,FBLK,WBRA};
|
|
1316 |
||
1317 |
#elif defined(__CPU_XSCALE__) |
|
1318 |
#ifdef __CPU_XSCALE_MANZANO__ |
|
1319 |
#ifdef __HAS_EXTERNAL_CACHE__ |
|
1320 |
// ***MANZANO with L2 cache****** // |
|
1321 |
||
1322 |
//Specifies TEX::CB bits for different L1/L2 cache attributes |
|
1323 |
// ...876543201 |
|
1324 |
// ...TEX..CB.. |
|
1325 |
static const TUint16 CacheBuffAttributes[80]= |
|
1326 |
{ // L1CACHE:
|
|
1327 |
// FBLK BFNC BUFC L1UN WTRA WTWA WBRA WBWA AWTR AWTW AWBR AWBT UNS UNS UNS MAX L2CACHE: |
|
1328 |
0x00, 0x44, 0x40, 0x40, 0x108, 0x108, 0x10c, 0x10c, SPE, SPE, SPE, SPE, UNS,UNS,UNS,0x10c, //NC |
|
1329 |
0x00, 0x44, 0x40, 0x40, 0x108, 0x108, 0x10c, 0x10c, SPE, SPE, SPE, SPE, UNS,UNS,UNS,0x10c, //WTRA |
|
1330 |
0x00, 0x44, 0x40, 0x40, 0x108, 0x108, 0x10c, 0x10c, SPE, SPE, SPE, SPE, UNS,UNS,UNS,0x10c, //WTWA |
|
1331 |
0x00, 0x44, 0x40, 0x140, 0x148, 0x148, 0x14c, 0x14c, SPE, SPE, SPE, SPE, UNS,UNS,UNS,0x14c, //WBRA |
|
1332 |
0x00, 0x44, 0x40, 0x140, 0x148, 0x148, 0x14c, 0x14c, SPE, SPE, SPE, SPE, UNS,UNS,UNS,0x14c, //WBWA |
|
1333 |
}; |
|
1334 |
||
1335 |
extern TUint MiniCacheConfig(); |
|
1336 |
//Converts page table attributes(TEX:CB) into appropriate cache attributes. |
|
1337 |
TInt CacheAttributesActual(TUint& cacheL1, TUint& cacheL2, TUint cbatt) |
|
1338 |
{
|
|
1339 |
switch (cbatt) |
|
1340 |
{
|
|
1341 |
case 0: cacheL1 = FBLK; cacheL2 = L2UN; return KErrNone; |
|
1342 |
case 0x40: cacheL1 = L1UN; cacheL2 = L2UN; return KErrNone; |
|
1343 |
case 0x44: cacheL1 = BFNC; cacheL2 = L2UN; return KErrNone; |
|
1344 |
case 0x48: cacheL1 = MiniCacheConfig(); cacheL2 = L2UN; return KErrNone; |
|
1345 |
case 0x108: cacheL1 = WTRA; cacheL2 = L2UN; return KErrNone; |
|
1346 |
case 0x10c: cacheL1 = WBRA; cacheL2 = L2UN; return KErrNone; |
|
1347 |
case 0x140: cacheL1 = L1UN; cacheL2 = WBWA; return KErrNone; |
|
1348 |
case 0x148: cacheL1 = WTRA; cacheL2 = WBWA; return KErrNone; |
|
1349 |
case 0x14c: cacheL1 = WBRA; cacheL2 = WBWA; return KErrNone; |
|
1350 |
} |
|
1351 |
return KErrNotSupported; |
|
1352 |
} |
|
1353 |
#else //__HAS_EXTERNAL_CACHE__ |
|
1354 |
// ***MANZANO without L2 cache****** // |
|
1355 |
||
1356 |
static const TUint16 CacheBuffAttributes[16]= |
|
1357 |
// FBLK BFNC BUFC L1UN WTRA WTWA WBRA WBWA -----------AltCache-------- MAXC |
|
1358 |
{0x00,0x44,0x40,0x40,0x148,0x148,0x14C,0x14C,SPE,SPE,SPE,SPE,UNS,UNS,UNS,0x14C};
|
|
1359 |
static const TUint8 CacheBuffActual[16]= |
|
1360 |
{FBLK,BFNC,BUFC,BUFC,WTRA,WTRA,WBRA,WBRA,FBLK,FBLK,FBLK,FBLK,FBLK,FBLK,FBLK,WBRA};
|
|
1361 |
#endif //__HAS_EXTERNAL_CACHE__ |
|
1362 |
||
1363 |
#else |
|
1364 |
// ***XSCALE that is not MANZANO (no L2 cache)****** // |
|
1365 |
||
1366 |
// X C B |
|
1367 |
static const TUint16 CacheBuffAttributes[16]= |
|
1368 |
{0x00,0x44,0x04,0x04,0x08,0x08,0x0C,0x4C,SPE,SPE,SPE,SPE,UNS,UNS,UNS,0x4C};
|
|
1369 |
static const TUint8 CacheBuffActual[16]= |
|
1370 |
{FBLK,BFNC,BUFC,BUFC,WTRA,WTRA,WBRA,WBWA,FBLK,FBLK,FBLK,FBLK,FBLK,FBLK,FBLK,WBWA};
|
|
1371 |
#endif |
|
1372 |
||
1373 |
// ***Common code for all XSCALE cores*** // |
|
1374 |
||
1375 |
extern TUint MiniCacheConfig(); |
|
1376 |
void ProcessSpecialCacheAttr(TUint& cache, TUint& cbatt) |
|
1377 |
{
|
|
1378 |
// If writeback requested, give writeback or writethrough |
|
1379 |
// If writethrough requested, give writethrough or uncached |
|
1380 |
// Give other allocation policy if necessary. |
|
1381 |
TUint mccfg=MiniCacheConfig(); |
|
1382 |
__KTRACE_OPT(KMMU,Kern::Printf("MiniCacheConfig: %x",mccfg));
|
|
1383 |
||
1384 |
if (cache<AWBR && mccfg>=AWBR) // asked for WT but cache is set for WB |
|
1385 |
{
|
|
1386 |
cache=BUFC; // so give uncached, buffered, coalescing |
|
1387 |
#if defined (__CPU_XSCALE_MANZANO__) |
|
1388 |
cbatt=0x40; |
|
1389 |
#else |
|
1390 |
cbatt=0x04; |
|
1391 |
#endif |
|
1392 |
} |
|
1393 |
else |
|
1394 |
{
|
|
1395 |
cache=mccfg; // give whatever minicache is configured for |
|
1396 |
cbatt=0x48; // minicache attributes |
|
1397 |
} |
|
1398 |
} |
|
1399 |
#endif |
|
1400 |
||
1401 |
static const TUint8 ActualReadPrivilegeLevel[4]={4,1,4,4}; // RORO,RWNO,RWRO,RWRW
|
|
1402 |
static const TUint8 ActualWritePrivilegeLevel[4]={0,1,1,4}; // RORO,RWNO,RWRO,RWRW
|
|
1403 |
||
1404 |
/** Calculates cb attributes for page table and sets actual cache attributes*/ |
|
1405 |
TInt GetCacheAttr(TUint& cacheL1, TUint& cacheL2, TUint& cbatt) |
|
1406 |
{
|
|
1407 |
TInt r = KErrNone; |
|
1408 |
// Scale down L2 to 0-4 : NC, WTRA, WTWA, WBRA, WBWA |
|
1409 |
#if defined (__CPU_XSCALE_MANZANO__) && defined(__HAS_EXTERNAL_CACHE__) |
|
1410 |
if (cacheL2 == MAXC) cacheL2 = WBWA-3; // Scale down L2 cache attributes... |
|
1411 |
else if (cacheL2 > WBWA) return KErrNotSupported; // ... to 0-4 for... |
|
1412 |
else if (cacheL2 < WTRA) cacheL2 = L2UN; // ... L2UN to WBWA |
|
1413 |
else cacheL2-=3; // |
|
1414 |
#else |
|
1415 |
cacheL2 = 0; // Either no L2 cache or L2 cache attributes will be just a copy of L1 cache attributes. |
|
1416 |
#endif |
|
1417 |
||
1418 |
//Get cb page attributes. (On some platforms, tex bits are includded as well.) |
|
1419 |
cbatt = CacheBuffAttributes[cacheL1 + (cacheL2<<4)]; |
|
1420 |
__KTRACE_OPT(KMMU,Kern::Printf("GetCacheAttr, table returned:%x",cbatt));
|
|
1421 |
||
1422 |
#if defined(__CPU_XSCALE__) |
|
1423 |
//Check if altDCache/LLR cache attributes are defined |
|
1424 |
if (cbatt == SPE) |
|
1425 |
{
|
|
1426 |
cacheL2 = 0; //Not L2 cached in such case |
|
1427 |
ProcessSpecialCacheAttr(cacheL1,cbatt); |
|
1428 |
__KTRACE_OPT(KMMU,Kern::Printf("GetCacheAttr, spec case returned:%x",cbatt));
|
|
1429 |
} |
|
1430 |
#endif |
|
1431 |
||
1432 |
if(cbatt == UNS) |
|
1433 |
return KErrNotSupported; |
|
1434 |
||
1435 |
//W Got CB page attributes. Now, find out what are the actual cache attributes. |
|
1436 |
#if defined(__CPU_XSCALE_MANZANO__) && defined(__HAS_EXTERNAL_CACHE__) |
|
1437 |
r = CacheAttributesActual(cacheL1, cacheL2, cbatt); |
|
1438 |
#else |
|
1439 |
cacheL1 = CacheBuffActual[cacheL1]; |
|
1440 |
#if defined(__HAS_EXTERNAL_CACHE__) |
|
1441 |
cacheL2 = cacheL1; |
|
1442 |
#else |
|
1443 |
cacheL2 = 0; |
|
1444 |
#endif |
|
1445 |
#endif |
|
1446 |
return r; |
|
1447 |
} |
|
1448 |
||
1449 |
TInt ArmMmu::PdePtePermissions(TUint& aMapAttr, TPde& aPde, TPte& aPte) |
|
1450 |
{
|
|
1451 |
__KTRACE_OPT(KMMU,Kern::Printf(">ArmMmu::PdePtePermissions, mapattr=%08x",aMapAttr));
|
|
1452 |
TUint read=aMapAttr & EMapAttrReadMask; |
|
1453 |
TUint write=(aMapAttr & EMapAttrWriteMask)>>4; |
|
1454 |
TUint exec=(aMapAttr & EMapAttrExecMask)>>8; |
|
1455 |
||
1456 |
// if execute access is greater than read, adjust read (since there are no separate execute permissions on ARM) |
|
1457 |
if (exec>read) |
|
1458 |
read=exec; |
|
1459 |
TUint ap; |
|
1460 |
if (write==0) |
|
1461 |
{
|
|
1462 |
// read-only |
|
1463 |
if (read>=4) |
|
1464 |
ap=KArmV45PermRORO; // user and supervisor read-only |
|
1465 |
else |
|
1466 |
ap=KArmV45PermRWNO; // supervisor r/w user no access (since no RO/NO access is available) |
|
1467 |
} |
|
1468 |
else if (write<4) |
|
1469 |
{
|
|
1470 |
// only supervisor can write |
|
1471 |
if (read>=4) |
|
1472 |
ap=KArmV45PermRWRO; // supervisor r/w user r/o |
|
1473 |
else |
|
1474 |
ap=KArmV45PermRWNO; // supervisor r/w user no access |
|
1475 |
} |
|
1476 |
else |
|
1477 |
ap=KArmV45PermRWRW; // supervisor r/w user r/w |
|
1478 |
read=ActualReadPrivilegeLevel[ap]; |
|
1479 |
write=ActualWritePrivilegeLevel[ap]; |
|
1480 |
#ifndef __CPU_USE_MMU_TEX_FIELD |
|
1481 |
ap|=(ap<<2); |
|
1482 |
ap|=(ap<<4); // replicate permissions in all four subpages |
|
1483 |
#endif |
|
1484 |
ap<<=4; // shift access permissions into correct position for PTE |
|
1485 |
ap|=KArmPteSmallPage; // add in mandatory small page bits |
|
1486 |
||
1487 |
// Get cb atributes for the page table and the actual cache attributes |
|
1488 |
TUint cbatt; |
|
1489 |
TUint cacheL1=(aMapAttr & EMapAttrL1CacheMask)>>12; |
|
1490 |
TUint cacheL2=(aMapAttr & EMapAttrL2CacheMask)>>16; |
|
1491 |
TInt r = GetCacheAttr(cacheL1, cacheL2, cbatt); |
|
1492 |
||
1493 |
if (r==KErrNone) |
|
1494 |
{
|
|
1495 |
aPde=PT_PDE(EDomainClient); |
|
1496 |
aPte=ap|cbatt; |
|
1497 |
aMapAttr=read|(write<<4)|(read<<8)|(cacheL1<<12)|(cacheL2<<16); |
|
1498 |
} |
|
1499 |
__KTRACE_OPT(KMMU,Kern::Printf("<ArmMmu::PdePtePermissions, r=%d, mapattr=%08x, pde=%08x, pte=%08x",
|
|
1500 |
r,aMapAttr,aPde,aPte)); |
|
1501 |
return r; |
|
1502 |
} |
|
1503 |
||
1504 |
void ArmMmu::Map(TLinAddr aLinAddr, TPhysAddr aPhysAddr, TInt aSize, TPde aPdePerm, TPte aPtePerm, TInt aMapShift) |
|
1505 |
// |
|
1506 |
// Map a region of physical addresses aPhysAddr to aPhysAddr+aSize-1 to virtual address aLinAddr. |
|
1507 |
// Use permissions specified by aPdePerm and aPtePerm. Use mapping sizes up to and including (1<<aMapShift). |
|
1508 |
// Assume any page tables required are already assigned. |
|
1509 |
// aLinAddr, aPhysAddr, aSize must be page-aligned. |
|
1510 |
// |
|
1511 |
{
|
|
1512 |
__KTRACE_OPT(KMMU, Kern::Printf("ArmMmu::Map lin=%08x phys=%08x size=%08x", aLinAddr, aPhysAddr, aSize));
|
|
1513 |
__KTRACE_OPT(KMMU, Kern::Printf("pde=%08x pte=%08x mapshift=%d", aPdePerm, aPtePerm, aMapShift));
|
|
1514 |
TPde pt_pde=aPdePerm; |
|
1515 |
TPte sp_pte=aPtePerm; |
|
1516 |
TPde section_pde=SECTION_PDE_FROM_PDEPTE(pt_pde, sp_pte); |
|
1517 |
TPte lp_pte=LP_PTE_FROM_SP_PTE(sp_pte); |
|
1518 |
TLinAddr la=aLinAddr; |
|
1519 |
TPhysAddr pa=aPhysAddr; |
|
1520 |
TInt remain=aSize; |
|
1521 |
while (remain) |
|
1522 |
{
|
|
1523 |
if (aMapShift>=KChunkShift && (la & KChunkMask)==0 && remain>=KChunkSize) |
|
1524 |
{
|
|
1525 |
// use sections |
|
1526 |
TInt npdes = remain>>KChunkShift; |
|
1527 |
TPde* p_pde = PageDirectory + (la>>KChunkShift); |
|
1528 |
TPde* p_pde_E = p_pde + npdes; |
|
1529 |
TPde pde = pa|section_pde; |
|
1530 |
NKern::LockSystem(); |
|
1531 |
for (; p_pde < p_pde_E; pde+=KChunkSize) |
|
1532 |
{
|
|
1533 |
__ASSERT_DEBUG(*p_pde==0, MM::Panic(MM::EPdeAlreadyInUse)); |
|
1534 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PDE %08x to %08x", pde, p_pde));
|
|
1535 |
*p_pde++=pde; |
|
1536 |
} |
|
1537 |
NKern::UnlockSystem(); |
|
1538 |
npdes<<=KChunkShift; |
|
1539 |
la+=npdes, pa+=npdes, remain-=npdes; |
|
1540 |
continue; |
|
1541 |
} |
|
1542 |
TInt block_size = Min(remain, KChunkSize-(la&KChunkMask)); |
|
1543 |
TPte pa_mask=~KPageMask; |
|
1544 |
TPte pte_perm=sp_pte; |
|
1545 |
if (aMapShift>=KLargePageShift && block_size>=KLargePageSize) |
|
1546 |
{
|
|
1547 |
if ((la & KLargePageMask)==0) |
|
1548 |
{
|
|
1549 |
// use 64K large pages |
|
1550 |
pa_mask=~KLargePageMask; |
|
1551 |
pte_perm=lp_pte; |
|
1552 |
} |
|
1553 |
else |
|
1554 |
block_size = Min(remain, KLargePageSize-(la&KLargePageMask)); |
|
1555 |
} |
|
1556 |
block_size &= pa_mask; |
|
1557 |
||
1558 |
// use pages (large or small) |
|
1559 |
TInt id = PageTableId(la); |
|
1560 |
__ASSERT_DEBUG(id>=0, MM::Panic(MM::EMmuMapNoPageTable)); |
|
1561 |
TPte* p_pte = PageTable(id) + ((la&KChunkMask)>>KPageShift); |
|
1562 |
TPte* p_pte_E = p_pte + (block_size>>KPageShift); |
|
1563 |
SPageTableInfo& ptinfo = iPtInfo[id]; |
|
1564 |
NKern::LockSystem(); |
|
1565 |
for (; p_pte < p_pte_E; pa+=KPageSize) |
|
1566 |
{
|
|
1567 |
__ASSERT_DEBUG(*p_pte==0, MM::Panic(MM::EPteAlreadyInUse)); |
|
1568 |
TPte pte = (pa & pa_mask) | pte_perm; |
|
1569 |
__KTRACE_OPT(KMMU,Kern::Printf("Writing PTE %08x to %08x", pte, p_pte));
|
|
1570 |
*p_pte++=pte; |
|
1571 |
++ptinfo.iCount; |
|
1572 |
NKern::FlashSystem(); |
|
1573 |
} |
|
1574 |
NKern::UnlockSystem(); |
|
1575 |
la+=block_size, remain-=block_size; |
|
1576 |
} |
|
1577 |
} |
|
1578 |
||
1579 |
void ArmMmu::Unmap(TLinAddr aLinAddr, TInt aSize) |
|
1580 |
// |
|
1581 |
// Remove all mappings in the specified range of addresses. |
|
1582 |
// Assumes there are only global mappings involved. |
|
1583 |
// Don't free page tables. |
|
1584 |
// aLinAddr, aSize must be page-aligned. |
|
1585 |
// |
|
1586 |
{
|
|
1587 |
__KTRACE_OPT(KMMU, Kern::Printf("ArmMmu::Unmap lin=%08x size=%08x", aLinAddr, aSize));
|
|
1588 |
TLinAddr a=aLinAddr; |
|
1589 |
TLinAddr end=a+aSize; |
|
1590 |
__KTRACE_OPT(KMMU,Kern::Printf("a=%08x end=%08x",a,end));
|
|
1591 |
NKern::LockSystem(); |
|
1592 |
while(a!=end) |
|
1593 |
{
|
|
1594 |
TInt pdeIndex=a>>KChunkShift; |
|
1595 |
TLinAddr next=(pdeIndex<<KChunkShift)+KChunkSize; |
|
1596 |
TInt to_do = Min(TInt(end-a), TInt(next-a))>>KPageShift; |
|
1597 |
__KTRACE_OPT(KMMU,Kern::Printf("a=%08x next=%08x to_do=%d",a,next,to_do));
|
|
1598 |
TPde pde = PageDirectory[pdeIndex]; |
|
1599 |
if ( (pde&KPdePresentMask)==KArmV45PdeSection ) |
|
1600 |
{
|
|
1601 |
__ASSERT_DEBUG(!(a&KChunkMask), MM::Panic(MM::EUnmapBadAlignment)); |
|
1602 |
PageDirectory[pdeIndex]=0; |
|
1603 |
InvalidateTLBForPage(a); |
|
1604 |
a=next; |
|
1605 |
NKern::FlashSystem(); |
|
1606 |
continue; |
|
1607 |
} |
|
1608 |
TInt ptid = GetPageTableId(a); |
|
1609 |
SPageTableInfo& ptinfo=iPtInfo[ptid]; |
|
1610 |
if (ptid>=0) |
|
1611 |
{
|
|
1612 |
TPte* ppte = PageTable(ptid) + ((a&KChunkMask)>>KPageShift); |
|
1613 |
TPte* ppte_End = ppte + to_do; |
|
1614 |
for (; ppte<ppte_End; ++ppte, a+=KPageSize) |
|
1615 |
{
|
|
1616 |
TUint pte_type = *ppte & KPteTypeMask; |
|
1617 |
if (pte_type && pte_type != KArmV45PteLargePage) |
|
1618 |
{
|
|
1619 |
--ptinfo.iCount; |
|
1620 |
*ppte=0; |
|
1621 |
InvalidateTLBForPage(a); |
|
1622 |
} |
|
1623 |
else if (pte_type) |
|
1624 |
{
|
|
1625 |
__ASSERT_DEBUG(!(a&KLargePageMask), MM::Panic(MM::EUnmapBadAlignment)); |
|
1626 |
ptinfo.iCount-=KLargeSmallPageRatio; |
|
1627 |
memclr(ppte, KLargeSmallPageRatio*sizeof(TPte)); |
|
1628 |
InvalidateTLBForPage(a); |
|
1629 |
a+=(KLargePageSize-KPageSize); |
|
1630 |
ppte+=(KLargeSmallPageRatio-1); |
|
1631 |
} |
|
1632 |
NKern::FlashSystem(); |
|
1633 |
} |
|
1634 |
} |
|
1635 |
else |
|
1636 |
a += (to_do<<KPageShift); |
|
1637 |
} |
|
1638 |
NKern::UnlockSystem(); |
|
1639 |
} |
|
1640 |
||
1641 |
TInt ArmMmu::AllocDomain() |
|
1642 |
{
|
|
1643 |
NKern::FMWait(&DomainLock); |
|
1644 |
TInt r=-1; |
|
1645 |
if (Domains) |
|
1646 |
{
|
|
1647 |
r=__e32_find_ls1_32(Domains); |
|
1648 |
Domains &= ~(1<<r); |
|
1649 |
} |
|
1650 |
NKern::FMSignal(&DomainLock); |
|
1651 |
return r; |
|
1652 |
} |
|
1653 |
||
1654 |
void ArmMmu::FreeDomain(TInt aDomain) |
|
1655 |
{
|
|
1656 |
__ASSERT_ALWAYS(aDomain>=0 && aDomain<ENumDomains, MM::Panic(MM::EFreeInvalidDomain)); |
|
1657 |
TUint32 m=1<<aDomain; |
|
1658 |
NKern::FMWait(&DomainLock); |
|
1659 |
__ASSERT_ALWAYS(!(Domains&m), MM::Panic(MM::EFreeDomainNotAllocated)); |
|
1660 |
Domains|=m; |
|
1661 |
NKern::FMSignal(&DomainLock); |
|
1662 |
} |
|
1663 |
||
1664 |
void ArmMmu::ClearPages(TInt aNumPages, TPhysAddr* aPageList, TUint8 aClearByte) |
|
1665 |
{
|
|
1666 |
//map the pages at a temporary address, clear them and unmap |
|
1667 |
__ASSERT_MUTEX(RamAllocatorMutex); |
|
1668 |
while (--aNumPages >= 0) |
|
1669 |
{
|
|
1670 |
TPhysAddr pa; |
|
1671 |
if((TInt)aPageList&1) |
|
1672 |
{
|
|
1673 |
pa = (TPhysAddr)aPageList&~1; |
|
1674 |
*(TPhysAddr*)&aPageList += iPageSize; |
|
1675 |
} |
|
1676 |
else |
|
1677 |
pa = *aPageList++; |
|
1678 |
*iTempPte = pa | SP_PTE(KArmV45PermRWNO, KMemAttBuf); |
|
1679 |
__DRAIN_WRITE_BUFFER; |
|
1680 |
InvalidateTLBForPage(iTempAddr); |
|
1681 |
memset((TAny*)iTempAddr, aClearByte, iPageSize); |
|
1682 |
} |
|
1683 |
*iTempPte=0; |
|
1684 |
__DRAIN_WRITE_BUFFER; |
|
1685 |
InvalidateTLBForPage(iTempAddr); |
|
1686 |
} |
|
1687 |
||
1688 |
TLinAddr DoMapTemp(TPhysAddr aPage, TBool aCached, TLinAddr aTempAddr, TPte* aTempPte) |
|
1689 |
{
|
|
1690 |
__ASSERT_DEBUG(!*aTempPte,MM::Panic(MM::ETempMappingAlreadyInUse)); |
|
1691 |
*aTempPte = (aPage&~KPageMask) | SP_PTE(KArmV45PermRWNO, aCached?KDefaultCaching:KMemAttBuf); |
|
1692 |
__DRAIN_WRITE_BUFFER; |
|
1693 |
return aTempAddr; |
|
1694 |
} |
|
1695 |
||
1696 |
/** |
|
1697 |
Create a temporary mapping of a physical page. |
|
1698 |
The RamAllocatorMutex must be held before this function is called and not released |
|
1699 |
until after UnmapTemp has been called. |
|
1700 |
||
1701 |
@param aPage The physical address of the page to be mapped. |
|
1702 |
@param aCached Whether to map the page cached or not. |
|
1703 |
||
1704 |
@return The linear address of where the page has been mapped. |
|
1705 |
*/ |
|
1706 |
TLinAddr ArmMmu::MapTemp(TPhysAddr aPage, TBool aCached) |
|
1707 |
{
|
|
1708 |
__ASSERT_MUTEX(RamAllocatorMutex); |
|
1709 |
return DoMapTemp(aPage, aCached, iTempAddr, iTempPte); |
|
1710 |
} |
|
1711 |
||
1712 |
/** |
|
1713 |
Create a temporary mapping of a physical page, distinct from that created by MapTemp. |
|
1714 |
The RamAllocatorMutex must be held before this function is called and not released |
|
1715 |
until after UnmapSecondTemp has been called. |
|
1716 |
||
1717 |
@param aPage The physical address of the page to be mapped. |
|
1718 |
@param aCached Whether to map the page cached or not. |
|
1719 |
||
1720 |
@return The linear address of where the page has been mapped. |
|
1721 |
*/ |
|
1722 |
TLinAddr ArmMmu::MapSecondTemp(TPhysAddr aPage, TBool aCached) |
|
1723 |
{
|
|
1724 |
__ASSERT_MUTEX(RamAllocatorMutex); |
|
1725 |
return DoMapTemp(aPage, aCached, iSecondTempAddr, iSecondTempPte); |
|
1726 |
} |
|
1727 |
||
1728 |
void DoUnmapTemp(TLinAddr aTempAddr, TPte* aTempPte) |
|
1729 |
{
|
|
1730 |
*aTempPte = 0; |
|
1731 |
__DRAIN_WRITE_BUFFER; |
|
1732 |
InvalidateTLBForPage(aTempAddr); |
|
1733 |
} |
|
1734 |
||
1735 |
/** |
|
1736 |
Remove the temporary mapping created with MapTemp. |
|
1737 |
*/ |
|
1738 |
void ArmMmu::UnmapTemp() |
|
1739 |
{
|
|
1740 |
__ASSERT_MUTEX(RamAllocatorMutex); |
|
1741 |
DoUnmapTemp(iTempAddr, iTempPte); |
|
1742 |
} |
|
1743 |
||
1744 |
/** |
|
1745 |
Remove the temporary mapping created with MapSecondTemp. |
|
1746 |
*/ |
|
1747 |
void ArmMmu::UnmapSecondTemp() |
|
1748 |
{
|
|
1749 |
__ASSERT_MUTEX(RamAllocatorMutex); |
|
1750 |
DoUnmapTemp(iSecondTempAddr, iSecondTempPte); |
|
1751 |
} |
|
1752 |
||
1753 |
/* |
|
1754 |
* Performs cache maintenance on physical cache (VIPT & PIPT) for a page to be reused. |
|
1755 |
*/ |
|
1756 |
void ArmMmu::CacheMaintenanceOnDecommit(TPhysAddr aAddr) |
|
1757 |
{
|
|
1758 |
CacheMaintenance::PageToReusePhysicalCache(aAddr); |
|
1759 |
} |
|
1760 |
||
1761 |
void ArmMmu::CacheMaintenanceOnDecommit(const TPhysAddr* aAddr, TInt aCount) |
|
1762 |
{
|
|
1763 |
while (--aCount>=0) |
|
1764 |
ArmMmu::CacheMaintenanceOnDecommit(*aAddr++); |
|
1765 |
} |
|
1766 |
||
1767 |
void ArmMmu::CacheMaintenanceOnPreserve(TPhysAddr, TUint) |
|
1768 |
{
|
|
1769 |
//Not required for moving memory model |
|
1770 |
__ASSERT_ALWAYS(0, Panic(ECacheMaintenance)); |
|
1771 |
} |
|
1772 |
||
1773 |
void ArmMmu::CacheMaintenanceOnPreserve(const TPhysAddr*, TInt, TUint) |
|
1774 |
{
|
|
1775 |
//Not required for moving memory model |
|
1776 |
__ASSERT_ALWAYS(0, Panic(ECacheMaintenance)); |
|
1777 |
} |
|
1778 |
||
1779 |
void ArmMmu::CacheMaintenanceOnPreserve(TPhysAddr , TInt , TLinAddr , TUint ) |
|
1780 |
{
|
|
1781 |
//Not required for moving memory model |
|
1782 |
__ASSERT_ALWAYS(0, Panic(ECacheMaintenance)); |
|
1783 |
} |
|
1784 |
||
1785 |
||
1786 |
TInt ArmMmu::UnlockRamCachePages(TUint8* volatile & aBase, TInt aStartPage, TInt aNumPages) |
|
1787 |
{
|
|
1788 |
NKern::LockSystem(); |
|
1789 |
for(;;) |
|
1790 |
{
|
|
1791 |
TInt page = ((TLinAddr)aBase>>KPageShift)+aStartPage; |
|
1792 |
TPde* pd = PageDirectory+(page>>(KChunkShift-KPageShift)); |
|
1793 |
TPte* pt = SafePageTableFromPde(*pd++); |
|
1794 |
TInt pteIndex = page&(KChunkMask>>KPageShift); |
|
1795 |
if(!pt) |
|
1796 |
{
|
|
1797 |
// whole page table has gone, so skip all pages in it... |
|
1798 |
TInt pagesInPt = (KChunkSize>>KPageShift)-pteIndex; |
|
1799 |
aNumPages -= pagesInPt; |
|
1800 |
aStartPage += pagesInPt; |
|
1801 |
if(aNumPages>0) |
|
1802 |
continue; |
|
1803 |
NKern::UnlockSystem(); |
|
1804 |
return KErrNone; |
|
1805 |
} |
|
1806 |
pt += pteIndex; |
|
1807 |
do |
|
1808 |
{
|
|
1809 |
TInt pagesInPt = (KChunkSize>>KPageShift)-pteIndex; |
|
1810 |
if(pagesInPt>aNumPages) |
|
1811 |
pagesInPt = aNumPages; |
|
1812 |
if(pagesInPt>KMaxPages) |
|
1813 |
pagesInPt = KMaxPages; |
|
1814 |
||
1815 |
aNumPages -= pagesInPt; |
|
1816 |
aStartPage += pagesInPt; |
|
1817 |
||
1818 |
do |
|
1819 |
{
|
|
1820 |
TPte pte = *pt++; |
|
1821 |
if(pte!=KPteNotPresentEntry) // pte may be null if page has already been unlocked and reclaimed by system |
|
1822 |
iRamCache->DonateRamCachePage(SPageInfo::FromPhysAddr(pte)); |
|
1823 |
} |
|
1824 |
while(--pagesInPt); |
|
1825 |
||
1826 |
if(!aNumPages) |
|
1827 |
{
|
|
1828 |
NKern::UnlockSystem(); |
|
1829 |
return KErrNone; |
|
1830 |
} |
|
1831 |
||
1832 |
pteIndex = aStartPage&(KChunkMask>>KPageShift); |
|
1833 |
} |
|
1834 |
while(!NKern::FlashSystem() && pteIndex); |
|
1835 |
} |
|
1836 |
} |
|
1837 |
||
1838 |
||
1839 |
TInt ArmMmu::LockRamCachePages(TUint8* volatile & aBase, TInt aStartPage, TInt aNumPages) |
|
1840 |
{
|
|
1841 |
NKern::LockSystem(); |
|
1842 |
for(;;) |
|
1843 |
{
|
|
1844 |
TInt page = ((TLinAddr)aBase>>KPageShift)+aStartPage; |
|
1845 |
TPde* pd = PageDirectory+(page>>(KChunkShift-KPageShift)); |
|
1846 |
TPte* pt = SafePageTableFromPde(*pd++); |
|
1847 |
TInt pteIndex = page&(KChunkMask>>KPageShift); |
|
1848 |
if(!pt) |
|
1849 |
goto not_found; |
|
1850 |
pt += pteIndex; |
|
1851 |
do |
|
1852 |
{
|
|
1853 |
TInt pagesInPt = (KChunkSize>>KPageShift)-pteIndex; |
|
1854 |
if(pagesInPt>aNumPages) |
|
1855 |
pagesInPt = aNumPages; |
|
1856 |
if(pagesInPt>KMaxPages) |
|
1857 |
pagesInPt = KMaxPages; |
|
1858 |
||
1859 |
aNumPages -= pagesInPt; |
|
1860 |
aStartPage += pagesInPt; |
|
1861 |
||
1862 |
do |
|
1863 |
{
|
|
1864 |
TPte pte = *pt++; |
|
1865 |
if(pte==KPteNotPresentEntry) |
|
1866 |
goto not_found; |
|
1867 |
if(!iRamCache->ReclaimRamCachePage(SPageInfo::FromPhysAddr(pte))) |
|
1868 |
goto not_found; |
|
1869 |
} |
|
1870 |
while(--pagesInPt); |
|
1871 |
||
1872 |
if(!aNumPages) |
|
1873 |
{
|
|
1874 |
NKern::UnlockSystem(); |
|
1875 |
return KErrNone; |
|
1876 |
} |
|
1877 |
||
1878 |
pteIndex = aStartPage&(KChunkMask>>KPageShift); |
|
1879 |
} |
|
1880 |
while(!NKern::FlashSystem() && pteIndex); |
|
1881 |
} |
|
1882 |
not_found: |
|
1883 |
NKern::UnlockSystem(); |
|
1884 |
return KErrNotFound; |
|
1885 |
} |
|
1886 |
||
1887 |
||
1888 |
void RamCache::SetFree(SPageInfo* aPageInfo) |
|
1889 |
{
|
|
1890 |
// Make a page free |
|
1891 |
SPageInfo::TType type = aPageInfo->Type(); |
|
1892 |
if(type==SPageInfo::EPagedCache) |
|
1893 |
{
|
|
1894 |
TInt offset = aPageInfo->Offset()<<KPageShift; |
|
1895 |
DArmPlatChunk* chunk = (DArmPlatChunk*)aPageInfo->Owner(); |
|
1896 |
__NK_ASSERT_DEBUG(TUint(offset)<TUint(chunk->iMaxSize)); |
|
1897 |
TLinAddr lin = ((TLinAddr)chunk->iBase)+offset; |
|
1898 |
TPte* pt = PtePtrFromLinAddr(lin); |
|
1899 |
*pt = KPteNotPresentEntry; |
|
1900 |
__DRAIN_WRITE_BUFFER; |
|
1901 |
InvalidateTLBForPage(lin); |
|
1902 |
((ArmMmu*)iMmu)->SyncCodeMappings(); |
|
1903 |
CacheMaintenance::PageToReuseVirtualCache(lin); |
|
1904 |
// actually decommit it from chunk... |
|
1905 |
TInt ptid = ((TLinAddr)pt-KPageTableBase)>>KPageTableShift; |
|
1906 |
SPageTableInfo& ptinfo=((ArmMmu*)iMmu)->iPtInfo[ptid]; |
|
1907 |
if(!--ptinfo.iCount) |
|
1908 |
{
|
|
1909 |
((ArmMmu*)iMmu)->DoUnassignPageTable(lin); |
|
1910 |
chunk->RemovePde(offset); |
|
1911 |
NKern::UnlockSystem(); |
|
1912 |
((ArmMmu*)iMmu)->FreePageTable(ptid); |
|
1913 |
NKern::LockSystem(); |
|
1914 |
} |
|
1915 |
} |
|
1916 |
else |
|
1917 |
{
|
|
1918 |
__KTRACE_OPT2(KPAGING,KPANIC,Kern::Printf("DP: SetFree() with bad page type = %d",aPageInfo->Type()));
|
|
1919 |
Panic(EUnexpectedPageType); |
|
1920 |
} |
|
1921 |
} |
|
1922 |
||
1923 |
||
1924 |
// |
|
1925 |
// MemModelDemandPaging |
|
1926 |
// |
|
1927 |
||
1928 |
class MemModelDemandPaging : public DemandPaging |
|
1929 |
{
|
|
1930 |
public: |
|
1931 |
// From RamCacheBase |
|
1932 |
virtual void Init2(); |
|
1933 |
virtual TInt Init3(); |
|
1934 |
virtual TBool PageUnmapped(SPageInfo* aPageInfo); |
|
1935 |
// From DemandPaging |
|
1936 |
virtual TInt Fault(TAny* aExceptionInfo); |
|
1937 |
virtual void SetOld(SPageInfo* aPageInfo); |
|
1938 |
virtual void SetFree(SPageInfo* aPageInfo); |
|
1939 |
virtual void NotifyPageFree(TPhysAddr aPage); |
|
1940 |
virtual TInt EnsurePagePresent(TLinAddr aPage, DProcess* aProcess); |
|
1941 |
virtual TPhysAddr LinearToPhysical(TLinAddr aPage, DProcess* aProcess); |
|
1942 |
virtual void AllocLoadAddress(DPagingRequest& aReq, TInt aDeviceId); |
|
1943 |
virtual TInt PageState(TLinAddr aAddr); |
|
1944 |
virtual TBool NeedsMutexOrderCheck(TLinAddr aStartAddr, TUint aLength); |
|
1945 |
// New |
|
1946 |
inline ArmMmu& Mmu() { return (ArmMmu&)*iMmu; }
|
|
1947 |
void InitRomPaging(); |
|
1948 |
void InitCodePaging(); |
|
1949 |
TInt HandleFault(TArmExcInfo& aExc, TLinAddr aFaultAddress, TBool aInRom); |
|
1950 |
TInt PageIn(TLinAddr aAddress, DMemModelCodeSegMemory* aCodeSegMemory); |
|
1951 |
private: |
|
1952 |
TLinAddr GetLinearAddress(SPageInfo* aPageInfo); |
|
1953 |
}; |
|
1954 |
||
1955 |
||
1956 |
// |
|
1957 |
// MemModelDemandPaging |
|
1958 |
// |
|
1959 |
||
1960 |
||
1961 |
DemandPaging* DemandPaging::New() |
|
1962 |
{
|
|
1963 |
return new MemModelDemandPaging(); |
|
1964 |
} |
|
1965 |
||
1966 |
||
1967 |
void MemModelDemandPaging::Init2() |
|
1968 |
{
|
|
1969 |
__KTRACE_OPT2(KPAGING,KBOOT,Kern::Printf(">MemModelDemandPaging::Init2"));
|
|
1970 |
DemandPaging::Init2(); |
|
1971 |
__KTRACE_OPT2(KPAGING,KBOOT,Kern::Printf("<MemModelDemandPaging::Init2"));
|
|
1972 |
} |
|
1973 |
||
1974 |
||
1975 |
void MemModelDemandPaging::AllocLoadAddress(DPagingRequest& aReq, TInt aReqId) |
|
1976 |
{
|
|
1977 |
aReq.iLoadAddr = iTempPages + aReqId * KPageSize; |
|
1978 |
aReq.iLoadPte = PtePtrFromLinAddr(aReq.iLoadAddr); |
|
1979 |
} |
|
1980 |
||
1981 |
||
1982 |
TInt MemModelDemandPaging::Init3() |
|
1983 |
{
|
|
1984 |
TInt r=DemandPaging::Init3(); |
|
1985 |
if(r!=KErrNone) |
|
1986 |
return r; |
|
1987 |
||
1988 |
// Create a region for mapping pages during page in |
|
1989 |
DPlatChunkHw* chunk; |
|
1990 |
TInt chunkSize = KMaxPagingDevices * KPagingRequestsPerDevice * KPageSize; |
|
1991 |
DPlatChunkHw::DoNew(chunk, KPhysAddrInvalid, chunkSize, EMapAttrSupRw|EMapAttrFullyBlocking); |
|
1992 |
if(!chunk) |
|
1993 |
Panic(EInitialiseFailed); |
|
1994 |
iTempPages = chunk->iLinAddr; |
|
1995 |
||
1996 |
if(RomPagingRequested()) |
|
1997 |
InitRomPaging(); |
|
1998 |
||
1999 |
if (CodePagingRequested()) |
|
2000 |
InitCodePaging(); |
|
2001 |
||
2002 |
__KTRACE_OPT2(KPAGING,KBOOT,Kern::Printf("<MemModelDemandPaging::Init3"));
|
|
2003 |
return KErrNone; |
|
2004 |
} |
|
2005 |
||
2006 |
||
2007 |
void MemModelDemandPaging::InitRomPaging() |
|
2008 |
{
|
|
2009 |
// Make page tables for demand paged part of ROM... |
|
2010 |
__KTRACE_OPT2(KPAGING,KBOOT,Kern::Printf("MemModelDemandPaging::Init3 making page tables for paged ROM"));
|
|
2011 |
TLinAddr lin = iRomPagedLinearBase&~KChunkMask; // first chunk with paged ROM in |
|
2012 |
TLinAddr linEnd = iRomLinearBase+iRomSize; |
|
2013 |
while(lin<linEnd) |
|
2014 |
{
|
|
2015 |
// Get a Page Table |
|
2016 |
TInt ptid = Mmu().PageTableId(lin); |
|
2017 |
if(ptid<0) |
|
2018 |
{
|
|
2019 |
MmuBase::Wait(); |
|
2020 |
ptid = Mmu().AllocPageTable(); |
|
2021 |
MmuBase::Signal(); |
|
2022 |
__NK_ASSERT_DEBUG(ptid>=0); |
|
2023 |
Mmu().PtInfo(ptid).SetGlobal(lin >> KChunkShift); |
|
2024 |
} |
|
2025 |
||
2026 |
// Get new page table addresses |
|
2027 |
TPte* pt = PageTable(ptid); |
|
2028 |
TPhysAddr ptPhys=Mmu().LinearToPhysical((TLinAddr)pt); |
|
2029 |
||
2030 |
// Pointer to page dirctory entry |
|
2031 |
TPde* ppde = PageDirectory + (lin>>KChunkShift); |
|
2032 |
||
2033 |
// Fill in Page Table |
|
2034 |
TPte* ptEnd = pt+(1<<(KChunkShift-KPageShift)); |
|
2035 |
pt += (lin&KChunkMask)>>KPageShift; |
|
2036 |
do |
|
2037 |
{
|
|
2038 |
if(lin<iRomPagedLinearBase) |
|
2039 |
*pt++ = Mmu().LinearToPhysical(lin) | KRomPtePermissions; |
|
2040 |
else |
|
2041 |
*pt++ = KPteNotPresentEntry; |
|
2042 |
lin += KPageSize; |
|
2043 |
} |
|
2044 |
while(pt<ptEnd && lin<=linEnd); |
|
2045 |
__DRAIN_WRITE_BUFFER; |
|
2046 |
||
2047 |
// Add new Page Table to the Page Directory |
|
2048 |
TPde newpde = ptPhys | KShadowPdePerm; |
|
2049 |
__KTRACE_OPT2(KPAGING,KMMU,Kern::Printf("Writing PDE %08x to %08x", newpde, ppde));
|
|
2050 |
TInt irq=NKern::DisableAllInterrupts(); |
|
2051 |
*ppde = newpde; |
|
2052 |
__DRAIN_WRITE_BUFFER; |
|
2053 |
FlushTLBs(); |
|
2054 |
NKern::RestoreInterrupts(irq); |
|
2055 |
} |
|
2056 |
} |
|
2057 |
||
2058 |
||
2059 |
void MemModelDemandPaging::InitCodePaging() |
|
2060 |
{
|
|
2061 |
// Initialise code paging info |
|
2062 |
iCodeLinearBase = Mmu().iUserCodeBase; |
|
2063 |
iCodeSize = Mmu().iMaxUserCodeSize; |
|
2064 |
} |
|
2065 |
||
2066 |
/** |
|
2067 |
@return ETrue when the unmapped page should be freed, EFalse otherwise |
|
2068 |
*/ |
|
2069 |
TBool MemModelDemandPaging::PageUnmapped(SPageInfo* aPageInfo) |
|
2070 |
{
|
|
2071 |
SPageInfo::TType type = aPageInfo->Type(); |
|
2072 |
||
2073 |
if(type!=SPageInfo::EPagedCache && type!=SPageInfo::EPagedCode) |
|
2074 |
{
|
|
2075 |
__NK_ASSERT_DEBUG(type!=SPageInfo::EPagedData); // not supported yet |
|
2076 |
return ETrue; |
|
2077 |
} |
|
2078 |
||
2079 |
RemovePage(aPageInfo); |
|
2080 |
AddAsFreePage(aPageInfo); |
|
2081 |
// Return false to stop DMemModelChunk::DoDecommit from freeing this page |
|
2082 |
return EFalse; |
|
2083 |
} |
|
2084 |
||
2085 |
||
2086 |
TLinAddr MemModelDemandPaging::GetLinearAddress(SPageInfo* aPageInfo) |
|
2087 |
{
|
|
2088 |
TInt offset = aPageInfo->Offset()<<KPageShift; |
|
2089 |
SPageInfo::TType type = aPageInfo->Type(); |
|
2090 |
__NK_ASSERT_DEBUG(TUint(offset)<(type==SPageInfo::EPagedROM ? iRomSize : iCodeSize)); |
|
2091 |
TLinAddr base = type==SPageInfo::EPagedROM ? iRomLinearBase : iCodeLinearBase; |
|
2092 |
return base + offset; |
|
2093 |
} |
|
2094 |
||
2095 |
||
2096 |
void MemModelDemandPaging::SetOld(SPageInfo* aPageInfo) |
|
2097 |
{
|
|
2098 |
__NK_ASSERT_DEBUG(aPageInfo->State() == SPageInfo::EStatePagedOld); |
|
2099 |
SPageInfo::TType type = aPageInfo->Type(); |
|
2100 |
||
2101 |
if(type==SPageInfo::EPagedROM || type==SPageInfo::EPagedCode) |
|
2102 |
{
|
|
2103 |
START_PAGING_BENCHMARK; |
|
2104 |
||
2105 |
// get linear address of page... |
|
2106 |
TLinAddr lin = GetLinearAddress(aPageInfo); |
|
2107 |
||
2108 |
// make page inaccessible... |
|
2109 |
TPte* pt = PtePtrFromLinAddr(lin); |
|
2110 |
*pt &= ~KPtePresentMask; |
|
2111 |
__DRAIN_WRITE_BUFFER; |
|
2112 |
InvalidateTLBForPage(lin); |
|
2113 |
Mmu().SyncCodeMappings(); |
|
2114 |
||
2115 |
if (type==SPageInfo::EPagedCode) |
|
2116 |
END_PAGING_BENCHMARK(this, EPagingBmSetCodePageOld); |
|
2117 |
} |
|
2118 |
else if(type==SPageInfo::EPagedCache) |
|
2119 |
{
|
|
2120 |
// leave page accessible |
|
2121 |
} |
|
2122 |
else if(type!=SPageInfo::EPagedFree) |
|
2123 |
{
|
|
2124 |
__KTRACE_OPT2(KPAGING,KPANIC,Kern::Printf("DP: SetOld() with bad page type = %d",aPageInfo->Type()));
|
|
2125 |
Panic(EUnexpectedPageType); |
|
2126 |
} |
|
2127 |
NKern::FlashSystem(); |
|
2128 |
} |
|
2129 |
||
2130 |
||
2131 |
void MemModelDemandPaging::SetFree(SPageInfo* aPageInfo) |
|
2132 |
{
|
|
2133 |
__ASSERT_SYSTEM_LOCK; |
|
2134 |
__ASSERT_MUTEX(MmuBase::RamAllocatorMutex); |
|
2135 |
__NK_ASSERT_DEBUG(aPageInfo->State() == SPageInfo::EStatePagedDead); |
|
2136 |
if(aPageInfo->LockCount()) |
|
2137 |
Panic(ERamPageLocked); |
|
2138 |
||
2139 |
SPageInfo::TType type = aPageInfo->Type(); |
|
2140 |
||
2141 |
if(type==SPageInfo::EPagedROM || type==SPageInfo::EPagedCode) |
|
2142 |
{
|
|
2143 |
START_PAGING_BENCHMARK; |
|
2144 |
||
2145 |
// get linear address of page... |
|
2146 |
TLinAddr lin = GetLinearAddress(aPageInfo); |
|
2147 |
||
2148 |
// unmap it... |
|
2149 |
TPte* pt = PtePtrFromLinAddr(lin); |
|
2150 |
*pt = KPteNotPresentEntry; |
|
2151 |
__DRAIN_WRITE_BUFFER; |
|
2152 |
InvalidateTLBForPage(lin); |
|
2153 |
Mmu().SyncCodeMappings(); |
|
2154 |
||
2155 |
if (type==SPageInfo::EPagedCode) |
|
2156 |
END_PAGING_BENCHMARK(this, EPagingBmSetCodePageFree); |
|
2157 |
#ifdef BTRACE_PAGING |
|
2158 |
TInt subCat = type==SPageInfo::EPagedCode ? BTrace::EPagingPageOutCode : BTrace::EPagingPageOutROM; |
|
2159 |
TPhysAddr phys = aPageInfo->PhysAddr(); |
|
2160 |
BTraceContext8(BTrace::EPaging,subCat,phys,lin); |
|
2161 |
#endif |
|
2162 |
} |
|
2163 |
else if(type==SPageInfo::EPagedCache) |
|
2164 |
{
|
|
2165 |
// get linear address of page... |
|
2166 |
TInt offset = aPageInfo->Offset()<<KPageShift; |
|
2167 |
DArmPlatChunk* chunk = (DArmPlatChunk*)aPageInfo->Owner(); |
|
2168 |
__NK_ASSERT_DEBUG(TUint(offset)<TUint(chunk->iMaxSize)); |
|
2169 |
TLinAddr lin = ((TLinAddr)chunk->iBase)+offset; |
|
2170 |
||
2171 |
// unmap it... |
|
2172 |
TPte* pt = PtePtrFromLinAddr(lin); |
|
2173 |
*pt = KPteNotPresentEntry; |
|
2174 |
__DRAIN_WRITE_BUFFER; |
|
2175 |
InvalidateTLBForPage(lin); |
|
2176 |
Mmu().SyncCodeMappings(); |
|
2177 |
NKern::UnlockSystem(); |
|
2178 |
CacheMaintenance::PageToReuseVirtualCache(lin); |
|
2179 |
NKern::LockSystem(); |
|
2180 |
||
2181 |
// actually decommit it from chunk... |
|
2182 |
TInt ptid = ((TLinAddr)pt-KPageTableBase)>>KPageTableShift; |
|
2183 |
SPageTableInfo& ptinfo=((ArmMmu*)iMmu)->iPtInfo[ptid]; |
|
2184 |
if(!--ptinfo.iCount) |
|
2185 |
{
|
|
2186 |
((ArmMmu*)iMmu)->DoUnassignPageTable(lin); |
|
2187 |
chunk->RemovePde(offset); |
|
2188 |
NKern::UnlockSystem(); |
|
2189 |
((ArmMmu*)iMmu)->FreePageTable(ptid); |
|
2190 |
NKern::LockSystem(); |
|
2191 |
} |
|
2192 |
||
2193 |
#ifdef BTRACE_PAGING |
|
2194 |
TPhysAddr phys = aPageInfo->PhysAddr(); |
|
2195 |
BTraceContext8(BTrace::EPaging,BTrace::EPagingPageOutCache,phys,lin); |
|
2196 |
#endif |
|
2197 |
} |
|
2198 |
else if(type==SPageInfo::EPagedFree) |
|
2199 |
{
|
|
2200 |
// already free... |
|
2201 |
#ifdef BTRACE_PAGING |
|
2202 |
TPhysAddr phys = aPageInfo->PhysAddr(); |
|
2203 |
BTraceContext4(BTrace::EPaging,BTrace::EPagingPageOutFree,phys); |
|
2204 |
#endif |
|
2205 |
// external cache may not have been cleaned if PageUnmapped called |
|
2206 |
CacheMaintenance::PageToReusePhysicalCache(aPageInfo->PhysAddr()); |
|
2207 |
} |
|
2208 |
else |
|
2209 |
{
|
|
2210 |
__KTRACE_OPT2(KPAGING,KPANIC,Kern::Printf("DP: SetFree() with bad page type = %d",aPageInfo->Type()));
|
|
2211 |
Panic(EUnexpectedPageType); |
|
2212 |
} |
|
2213 |
NKern::FlashSystem(); |
|
2214 |
} |
|
2215 |
||
2216 |
||
2217 |
void MemModelDemandPaging::NotifyPageFree(TPhysAddr aPage) |
|
2218 |
{
|
|
2219 |
MM::Panic(MM::EOperationNotImplemented); |
|
2220 |
} |
|
2221 |
||
2222 |
||
2223 |
/** |
|
2224 |
Return True if exception was caused by a memory write access. |
|
2225 |
This function can cause a paging exception! |
|
2226 |
*/ |
|
2227 |
static TBool FaultDuringWrite(TArmExcInfo& aExc) |
|
2228 |
{
|
|
2229 |
// We can't decode jazelle instruction to determine if they faulted during a read. |
|
2230 |
// Therefore we will treat them as writes (which will panic the thread)... |
|
2231 |
if(aExc.iCpsr&(1<<24)) |
|
2232 |
return ETrue; |
|
2233 |
||
2234 |
if(aExc.iCpsr&(1<<5)) |
|
2235 |
{
|
|
2236 |
// thumb |
|
2237 |
TUint32 op = *(TUint16*)aExc.iR15; |
|
2238 |
switch((op>>13)&7) |
|
2239 |
{
|
|
2240 |
case 2: |
|
2241 |
if((op&0xfa00)==0x5000) |
|
2242 |
return ETrue; // STR (2) and STRB (2) |
|
2243 |
if((op&0xfe00)==0x5200) |
|
2244 |
return ETrue; // STRH (2) |
|
2245 |
return EFalse; |
|
2246 |
case 3: |
|
2247 |
return !(op&(1<<11)); // STR (1) and STRB (1) |
|
2248 |
case 4: |
|
2249 |
return !(op&(1<<11)); // STR (3) and STRH (1) |
|
2250 |
case 5: |
|
2251 |
return (op&0xfe00)==0xb400; // PUSH |
|
2252 |
case 6: |
|
2253 |
return (op&0xf800)==0xc000; // STMIA |
|
2254 |
} |
|
2255 |
} |
|
2256 |
else |
|
2257 |
{
|
|
2258 |
// ARM |
|
2259 |
TUint32 op = *(TUint32*)aExc.iR15; |
|
2260 |
if(op<0xf0000000) |
|
2261 |
{
|
|
2262 |
switch((op>>25)&7) |
|
2263 |
{
|
|
2264 |
case 0: |
|
2265 |
if((op&0xf0)==(0xb0)) |
|
2266 |
return !(op&(1<<20)); // load/store halfword |
|
2267 |
else if((op&0x0e1000f0)==(0x000000f0)) |
|
2268 |
return ETrue; // store double |
|
2269 |
else if((op&0x0fb000f0) == 0x010000f0) |
|
2270 |
return ETrue; // swap instruction |
|
2271 |
else if((op&0x0ff000f0) == 0x01800090) |
|
2272 |
return ETrue; // strex |
|
2273 |
return EFalse; |
|
2274 |
case 2: |
|
2275 |
return !(op&(1<<20)); // load/store immediate |
|
2276 |
case 3: |
|
2277 |
if(!(op&0x10)) |
|
2278 |
return !(op&(1<<20)); // load/store register offset |
|
2279 |
return EFalse; |
|
2280 |
case 4: |
|
2281 |
return !(op&(1<<20)); // load/store multiple |
|
2282 |
case 6: |
|
2283 |
return !(op&(1<<20)); // coproc store |
|
2284 |
} |
|
2285 |
} |
|
2286 |
else |
|
2287 |
{
|
|
2288 |
switch((op>>25)&7) |
|
2289 |
{
|
|
2290 |
case 4: |
|
2291 |
if((op&0xfe5f0f00)==(0xf84d0500)) |
|
2292 |
return ETrue; // SRS instructions |
|
2293 |
return EFalse; |
|
2294 |
case 6: |
|
2295 |
return !(op&(1<<20)); // coproc store (STC2) |
|
2296 |
} |
|
2297 |
} |
|
2298 |
} |
|
2299 |
return EFalse; |
|
2300 |
} |
|
2301 |
||
2302 |
||
2303 |
TInt MemModelDemandPaging::Fault(TAny* aExceptionInfo) |
|
2304 |
{
|
|
2305 |
TArmExcInfo& exc=*(TArmExcInfo*)aExceptionInfo; |
|
2306 |
||
2307 |
// Get faulting address |
|
2308 |
TLinAddr faultAddress = exc.iFaultAddress; |
|
2309 |
if(exc.iExcCode==EArmExceptionDataAbort) |
|
2310 |
{
|
|
2311 |
// Only handle page translation faults |
|
2312 |
if((exc.iFaultStatus&0xf)!=0x7) |
|
2313 |
return KErrUnknown; |
|
2314 |
// Let writes take an exception rather than page in any memory... |
|
2315 |
if(FaultDuringWrite(exc)) |
|
2316 |
return KErrUnknown; |
|
2317 |
} |
|
2318 |
else if (exc.iExcCode != EArmExceptionPrefetchAbort) |
|
2319 |
return KErrUnknown; // Not prefetch or data abort |
|
2320 |
||
2321 |
DThread* thread = TheCurrentThread; |
|
2322 |
||
2323 |
// check which ragion fault occured in... |
|
2324 |
TBool inRom=ETrue; |
|
2325 |
if(TUint(faultAddress-iRomPagedLinearBase)<iRomPagedSize) |
|
2326 |
{
|
|
2327 |
// in ROM |
|
2328 |
} |
|
2329 |
else if(TUint(faultAddress-iCodeLinearBase)<iCodeSize) |
|
2330 |
{
|
|
2331 |
// in code |
|
2332 |
inRom=EFalse; |
|
2333 |
} |
|
2334 |
else |
|
2335 |
return KErrUnknown; // Not in pageable region |
|
2336 |
||
2337 |
// Check if thread holds fast mutex and claim system lock |
|
2338 |
NFastMutex* fm = NKern::HeldFastMutex(); |
|
2339 |
TPagingExcTrap* trap = thread->iPagingExcTrap; |
|
2340 |
if(!fm) |
|
2341 |
NKern::LockSystem(); |
|
2342 |
else |
|
2343 |
{
|
|
2344 |
if(!trap || fm!=&TheScheduler.iLock) |
|
2345 |
{
|
|
2346 |
__KTRACE_OPT2(KPAGING,KPANIC,Kern::Printf("DP: Fault with FM Held! %x (%O pc=%x)",faultAddress,&Kern::CurrentThread(),exc.iR15));
|
|
2347 |
Panic(EPageFaultWhilstFMHeld); // Not allowed to hold mutexes |
|
2348 |
} |
|
2349 |
||
2350 |
// Current thread already has the system lock... |
|
2351 |
NKern::FlashSystem(); // Let someone else have a go with the system lock. |
|
2352 |
} |
|
2353 |
||
2354 |
// System locked here |
|
2355 |
||
2356 |
TInt r = KErrNone; |
|
2357 |
if(thread->IsRealtime()) |
|
2358 |
r = CheckRealtimeThreadFault(thread, aExceptionInfo); |
|
2359 |
if (r == KErrNone) |
|
2360 |
r = HandleFault(exc, faultAddress, inRom); |
|
2361 |
||
2362 |
// Restore system lock state |
|
2363 |
if (fm != NKern::HeldFastMutex()) |
|
2364 |
{
|
|
2365 |
if (fm) |
|
2366 |
NKern::LockSystem(); |
|
2367 |
else |
|
2368 |
NKern::UnlockSystem(); |
|
2369 |
} |
|
2370 |
||
2371 |
// Deal with XTRAP_PAGING |
|
2372 |
if(r == KErrNone && trap) |
|
2373 |
{
|
|
2374 |
trap->Exception(1); // Return from exception trap with result '1' (value>0) |
|
2375 |
// code doesn't continue beyond this point. |
|
2376 |
} |
|
2377 |
||
2378 |
return r; |
|
2379 |
} |
|
2380 |
||
2381 |
||
2382 |
TInt MemModelDemandPaging::HandleFault(TArmExcInfo& aExc, TLinAddr aFaultAddress, TBool aInRom) |
|
2383 |
{
|
|
2384 |
++iEventInfo.iPageFaultCount; |
|
2385 |
||
2386 |
// get page table entry... |
|
2387 |
TPte* pt = SafePtePtrFromLinAddr(aFaultAddress); |
|
2388 |
if(!pt) |
|
2389 |
return KErrNotFound; |
|
2390 |
TPte pte = *pt; |
|
2391 |
||
2392 |
// Do what is required to make page accessible... |
|
2393 |
||
2394 |
if(pte&KPtePresentMask) |
|
2395 |
{
|
|
2396 |
// PTE is present, so assume it has already been dealt with |
|
2397 |
#ifdef BTRACE_PAGING |
|
2398 |
BTraceContext12(BTrace::EPaging,BTrace::EPagingPageNop,pte&~KPageMask,aFaultAddress,aExc.iR15); |
|
2399 |
#endif |
|
2400 |
return KErrNone; |
|
2401 |
} |
|
2402 |
||
2403 |
if(pte!=KPteNotPresentEntry) |
|
2404 |
{
|
|
2405 |
// PTE alread has a page |
|
2406 |
SPageInfo* pageInfo = SPageInfo::FromPhysAddr(pte); |
|
2407 |
if(pageInfo->State()==SPageInfo::EStatePagedDead) |
|
2408 |
{
|
|
2409 |
// page currently being unmapped, so do that here... |
|
2410 |
*pt = KPteNotPresentEntry; // Update page table |
|
2411 |
__DRAIN_WRITE_BUFFER; |
|
2412 |
} |
|
2413 |
else |
|
2414 |
{
|
|
2415 |
// page just needs making young again... |
|
2416 |
*pt = TPte(pte|KArmPteSmallPage); // Update page table |
|
2417 |
__DRAIN_WRITE_BUFFER; |
|
2418 |
Rejuvenate(pageInfo); |
|
2419 |
#ifdef BTRACE_PAGING |
|
2420 |
BTraceContext12(BTrace::EPaging,BTrace::EPagingRejuvenate,pte&~KPageMask,aFaultAddress,aExc.iR15); |
|
2421 |
#endif |
|
2422 |
return KErrNone; |
|
2423 |
} |
|
2424 |
} |
|
2425 |
||
2426 |
// PTE not present, so page it in... |
|
2427 |
// check if fault in a CodeSeg... |
|
2428 |
DMemModelCodeSegMemory* codeSegMemory = NULL; |
|
2429 |
if (aInRom) |
|
2430 |
NKern::ThreadEnterCS(); |
|
2431 |
else |
|
2432 |
{
|
|
2433 |
// find CodeSeg... |
|
2434 |
DMemModelCodeSeg* codeSeg = (DMemModelCodeSeg*)DCodeSeg::CodeSegsByAddress.Find(aFaultAddress); |
|
2435 |
if (!codeSeg) |
|
2436 |
return KErrNotFound; |
|
2437 |
codeSegMemory = codeSeg->Memory(); |
|
2438 |
if (codeSegMemory==0 || !codeSegMemory->iIsDemandPaged) |
|
2439 |
return KErrNotFound; |
|
2440 |
// open reference on CodeSegMemory |
|
2441 |
NKern::ThreadEnterCS(); |
|
2442 |
#ifdef _DEBUG |
|
2443 |
TInt r = |
|
2444 |
#endif |
|
2445 |
codeSegMemory->Open(); |
|
2446 |
__NK_ASSERT_DEBUG(r==KErrNone); |
|
2447 |
NKern::FlashSystem(); |
|
2448 |
} |
|
2449 |
||
2450 |
#ifdef BTRACE_PAGING |
|
2451 |
BTraceContext8(BTrace::EPaging,BTrace::EPagingPageInBegin,aFaultAddress,aExc.iR15); |
|
2452 |
#endif |
|
2453 |
||
2454 |
TInt r = PageIn(aFaultAddress,codeSegMemory); |
|
2455 |
||
2456 |
NKern::UnlockSystem(); |
|
2457 |
||
2458 |
if(codeSegMemory) |
|
2459 |
codeSegMemory->Close(); |
|
2460 |
||
2461 |
NKern::ThreadLeaveCS(); |
|
2462 |
||
2463 |
return r; |
|
2464 |
} |
|
2465 |
||
2466 |
||
2467 |
TInt MemModelDemandPaging::PageIn(TLinAddr aAddress, DMemModelCodeSegMemory* aCodeSegMemory) |
|
2468 |
{
|
|
2469 |
// Get a request object - this may block until one is available |
|
2470 |
DPagingRequest* req = AcquireRequestObject(); |
|
2471 |
||
2472 |
// Get page table entry |
|
2473 |
TPte* pt = SafePtePtrFromLinAddr(aAddress); |
|
2474 |
||
2475 |
// Check page is still required... |
|
2476 |
if(!pt || *pt!=KPteNotPresentEntry) |
|
2477 |
{
|
|
2478 |
#ifdef BTRACE_PAGING |
|
2479 |
BTraceContext0(BTrace::EPaging,BTrace::EPagingPageInUnneeded); |
|
2480 |
#endif |
|
2481 |
ReleaseRequestObject(req); |
|
2482 |
return pt ? KErrNone : KErrNotFound; |
|
2483 |
} |
|
2484 |
||
2485 |
++iEventInfo.iPageInReadCount; |
|
2486 |
||
2487 |
// Get a free page |
|
2488 |
SPageInfo* pageInfo = AllocateNewPage(); |
|
2489 |
__NK_ASSERT_DEBUG(pageInfo); |
|
2490 |
||
2491 |
// Get physical address of free page |
|
2492 |
TPhysAddr phys = pageInfo->PhysAddr(); |
|
2493 |
__NK_ASSERT_DEBUG(phys!=KPhysAddrInvalid); |
|
2494 |
||
2495 |
// Temporarily map free page |
|
2496 |
TLinAddr loadAddr = req->iLoadAddr; |
|
2497 |
pt = req->iLoadPte; |
|
2498 |
*pt = phys | SP_PTE(KArmV45PermRWNO, KMemAttTempDemandPaging); |
|
2499 |
__DRAIN_WRITE_BUFFER; |
|
2500 |
||
2501 |
// Read page from backing store |
|
2502 |
aAddress &= ~KPageMask; |
|
2503 |
NKern::UnlockSystem(); |
|
2504 |
||
2505 |
TInt r; |
|
2506 |
if (!aCodeSegMemory) |
|
2507 |
r = ReadRomPage(req, aAddress); |
|
2508 |
else |
|
2509 |
{
|
|
2510 |
r = ReadCodePage(req, aCodeSegMemory, aAddress); |
|
2511 |
if (r == KErrNone) |
|
2512 |
aCodeSegMemory->ApplyCodeFixups((TUint32*)loadAddr, aAddress); |
|
2513 |
} |
|
2514 |
if(r!=KErrNone) |
|
2515 |
Panic(EPageInFailed); |
|
2516 |
||
2517 |
// make caches consistant (uncached memory is used for page loading) |
|
2518 |
__DRAIN_WRITE_BUFFER; |
|
2519 |
NKern::LockSystem(); |
|
2520 |
||
2521 |
// Invalidate temporary mapping |
|
2522 |
*pt = KPteNotPresentEntry; |
|
2523 |
__DRAIN_WRITE_BUFFER; |
|
2524 |
InvalidateTLBForPage(loadAddr); |
|
2525 |
||
2526 |
ReleaseRequestObject(req); |
|
2527 |
||
2528 |
// Get page table entry |
|
2529 |
pt = SafePtePtrFromLinAddr(aAddress); |
|
2530 |
||
2531 |
// Check page still needs updating |
|
2532 |
TBool notNeeded = pt==0 || *pt!=KPteNotPresentEntry; |
|
2533 |
if(notNeeded) |
|
2534 |
{
|
|
2535 |
// We don't need the new page after all, so put it on the active list as a free page |
|
2536 |
__KTRACE_OPT(KPAGING,Kern::Printf("DP: PageIn (New page not used)"));
|
|
2537 |
#ifdef BTRACE_PAGING |
|
2538 |
BTraceContext0(BTrace::EPaging,BTrace::EPagingPageInUnneeded); |
|
2539 |
#endif |
|
2540 |
AddAsFreePage(pageInfo); |
|
2541 |
return pt ? KErrNone : KErrNotFound; |
|
2542 |
} |
|
2543 |
||
2544 |
// Update page info |
|
2545 |
if (!aCodeSegMemory) |
|
2546 |
pageInfo->SetPagedROM((aAddress-iRomLinearBase)>>KPageShift); |
|
2547 |
else |
|
2548 |
pageInfo->SetPagedCode(aCodeSegMemory,(aAddress-Mmu().iUserCodeBase)>>KPageShift); |
|
2549 |
||
2550 |
// Map page into final location |
|
2551 |
*pt = phys | (aCodeSegMemory ? KUserCodeLoadPte : KRomPtePermissions); |
|
2552 |
__DRAIN_WRITE_BUFFER; |
|
2553 |
#ifdef BTRACE_PAGING |
|
2554 |
TInt subCat = aCodeSegMemory ? BTrace::EPagingPageInCode : BTrace::EPagingPageInROM; |
|
2555 |
BTraceContext8(BTrace::EPaging,subCat,phys,aAddress); |
|
2556 |
#endif |
|
2557 |
||
2558 |
AddAsYoungest(pageInfo); |
|
2559 |
BalanceAges(); |
|
2560 |
||
2561 |
return KErrNone; |
|
2562 |
} |
|
2563 |
||
2564 |
||
2565 |
inline TUint8 ReadByte(TLinAddr aAddress) |
|
2566 |
{ return *(volatile TUint8*)aAddress; }
|
|
2567 |
||
2568 |
||
2569 |
TInt MemModelDemandPaging::EnsurePagePresent(TLinAddr aPage, DProcess* aProcess) |
|
2570 |
{
|
|
2571 |
XTRAPD(exc,XT_DEFAULT,XTRAP_PAGING_RETRY(CHECK_PAGING_SAFE; ReadByte(aPage);)); |
|
2572 |
return exc; |
|
2573 |
} |
|
2574 |
||
2575 |
||
2576 |
TPhysAddr MemModelDemandPaging::LinearToPhysical(TLinAddr aPage, DProcess* aProcess) |
|
2577 |
{
|
|
2578 |
return Mmu().LinearToPhysical(aPage); |
|
2579 |
} |
|
2580 |
||
2581 |
||
2582 |
TInt MemModelDemandPaging::PageState(TLinAddr aAddr) |
|
2583 |
{
|
|
2584 |
TPte* ptePtr = 0; |
|
2585 |
TPte pte = 0; |
|
2586 |
TInt r = 0; |
|
2587 |
SPageInfo* pageInfo = NULL; |
|
2588 |
||
2589 |
NKern::LockSystem(); |
|
2590 |
||
2591 |
DMemModelCodeSegMemory* codeSegMemory = 0; |
|
2592 |
if(TUint(aAddr-iRomPagedLinearBase)<iRomPagedSize) |
|
2593 |
r |= EPageStateInRom; |
|
2594 |
else if (TUint(aAddr-iCodeLinearBase)<iCodeSize) |
|
2595 |
{
|
|
2596 |
DMemModelCodeSeg* codeSeg = (DMemModelCodeSeg*)DCodeSeg::CodeSegsByAddress.Find(aAddr); |
|
2597 |
if(codeSeg) |
|
2598 |
codeSegMemory = codeSeg->Memory(); |
|
2599 |
if (codeSegMemory) |
|
2600 |
{
|
|
2601 |
r |= EPageStateInRamCode; |
|
2602 |
if (codeSegMemory->iIsDemandPaged) |
|
2603 |
r |= EPageStatePaged; |
|
2604 |
} |
|
2605 |
} |
|
2606 |
||
2607 |
ptePtr = SafePtePtrFromLinAddr(aAddr); |
|
2608 |
if (!ptePtr) |
|
2609 |
goto done; |
|
2610 |
r |= EPageStatePageTablePresent; |
|
2611 |
pte = *ptePtr; |
|
2612 |
if (pte == KPteNotPresentEntry) |
|
2613 |
goto done; |
|
2614 |
r |= EPageStatePtePresent; |
|
2615 |
if (pte & KPtePresentMask) |
|
2616 |
r |= EPageStatePteValid; |
|
2617 |
||
2618 |
pageInfo = SPageInfo::FromPhysAddr(pte); |
|
2619 |
r |= pageInfo->Type(); |
|
2620 |
r |= pageInfo->State()<<8; |
|
2621 |
||
2622 |
done: |
|
2623 |
NKern::UnlockSystem(); |
|
2624 |
return r; |
|
2625 |
} |
|
2626 |
||
2627 |
||
2628 |
TBool MemModelDemandPaging::NeedsMutexOrderCheck(TLinAddr aStartAddr, TUint aLength) |
|
2629 |
{
|
|
2630 |
// Don't check mutex order for reads from unpaged rom, kernel data area and kernel stack chunk |
|
2631 |
TLinAddr endAddr = aStartAddr + aLength; |
|
2632 |
TLinAddr stackBase = (TLinAddr)MM::SvStackChunk->Base(); |
|
2633 |
TLinAddr stackEnd = stackBase + MM::SvStackChunk->iMaxSize; |
|
2634 |
TLinAddr unpagedRomEnd = iRomPagedLinearBase ? iRomPagedLinearBase : iRomLinearBase + iRomSize; |
|
2635 |
TBool rangeInUnpagedRom = aStartAddr >= iRomLinearBase && endAddr <= unpagedRomEnd; |
|
2636 |
TBool rangeInKernelData = aStartAddr >= KKernelDataBase && endAddr <= KKernelDataEnd; |
|
2637 |
TBool rangeInKernelStack = aStartAddr >= stackBase && endAddr <= stackEnd; |
|
2638 |
return !rangeInUnpagedRom && !rangeInKernelData && !rangeInKernelStack; |
|
2639 |
} |
|
2640 |
||
2641 |
||
2642 |
EXPORT_C TBool DDemandPagingLock::Lock(DThread* aThread, TLinAddr aStart, TInt aSize) |
|
2643 |
{
|
|
2644 |
MemModelDemandPaging* pager = (MemModelDemandPaging*)iThePager; |
|
2645 |
if(pager) |
|
2646 |
{
|
|
2647 |
ArmMmu& m = pager->Mmu(); |
|
2648 |
TLinAddr end = aStart+aSize; |
|
2649 |
||
2650 |
if ((aStart < TUint(pager->iRomPagedLinearBase+pager->iRomPagedSize) && end > pager->iRomPagedLinearBase) || |
|
2651 |
(aStart < TUint(m.iUserCodeBase + m.iMaxUserCodeSize) && end > m.iUserCodeBase)) |
|
2652 |
return pager->ReserveLock(aThread,aStart,aSize,*this); |
|
2653 |
} |
|
2654 |
||
2655 |
return EFalse; |
|
2656 |
} |
|
2657 |
||
2658 |
void ArmMmu::DisablePageModification(DMemModelChunk* aChunk, TInt aOffset) |
|
2659 |
// |
|
2660 |
// Mark the page at aOffset in aChunk inaccessible to prevent it being |
|
2661 |
// modified while defrag is in progress. Save the required information |
|
2662 |
// to allow the fault handler to deal with this. |
|
2663 |
// Flush the cache for the page so that it can be aliased elsewhere for |
|
2664 |
// copying. |
|
2665 |
// Call this with the system unlocked. |
|
2666 |
// |
|
2667 |
{
|
|
2668 |
__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::DisablePageModification() offset=%08x", aOffset));
|
|
2669 |
||
2670 |
// Acquire the system lock here for atomic access to aChunk->iBase as moving |
|
2671 |
// between the home and run addresses (a reschedule) may update aChunk->iBase. |
|
2672 |
NKern::LockSystem(); |
|
2673 |
||
2674 |
iDisabledAddr = (TLinAddr)(aChunk->iBase) + aOffset; |
|
2675 |
TInt ptid=GetPageTableId(iDisabledAddr); |
|
2676 |
if(ptid<0) |
|
2677 |
Panic(EDefragDisablePageFailed); |
|
2678 |
||
2679 |
TPte* pPte = PageTable(ptid) + ((aOffset&KChunkMask)>>KPageShift); |
|
2680 |
TPte pte = *pPte; |
|
2681 |
if ((pte & KPteTypeMask) != KArmPteSmallPage) |
|
2682 |
Panic(EDefragDisablePageFailed); |
|
2683 |
||
2684 |
iDisabledPte = pPte; |
|
2685 |
iDisabledOldVal = pte; |
|
2686 |
||
2687 |
*pPte = 0; |
|
2688 |
__DRAIN_WRITE_BUFFER; |
|
2689 |
InvalidateTLBForPage(iDisabledAddr); |
|
2690 |
NKern::UnlockSystem(); |
|
2691 |
||
2692 |
CacheMaintenance::PageToPreserveAndReuseVirtualCache(iDisabledAddr); |
|
2693 |
__DRAIN_WRITE_BUFFER; |
|
2694 |
} |
|
2695 |
||
2696 |
TBool FaultStatusFromLinAddr(TLinAddr aAddr, TBool aKernel, TUint32& aFaultStatus) |
|
2697 |
// Walk the page tables looking for the given linear address. If access |
|
2698 |
// would've caused a fault, return ETrue and fill in aFaultStatus with a |
|
2699 |
// FSR value. Otherwise, return EFalse. Assumes it was a read. |
|
2700 |
{
|
|
2701 |
TPde pde = PageDirectory[aAddr>>KChunkShift]; |
|
2702 |
TPde pdetype = pde & KPdeTypeMask; |
|
2703 |
if (pdetype == 0) |
|
2704 |
{
|
|
2705 |
// section translation fault |
|
2706 |
aFaultStatus = 0x5; |
|
2707 |
return ETrue; |
|
2708 |
} |
|
2709 |
||
2710 |
TPte pte=0; |
|
2711 |
TInt domain = (pde >> 5) & 0xf; |
|
2712 |
TUint32 dacr = Arm::Dacr(); |
|
2713 |
TInt domaccess = (dacr >> (domain<<1)) & 0x3; |
|
2714 |
TInt ispage = (pdetype == KArmV45PdeSection) ? 0 : 0x2; |
|
2715 |
||
2716 |
if (ispage) |
|
2717 |
{
|
|
2718 |
pte = *PtePtrFromLinAddr(aAddr); |
|
2719 |
if ((pte & KPteTypeMask) == 0) |
|
2720 |
{
|
|
2721 |
// page translation fault |
|
2722 |
aFaultStatus = 0x7; |
|
2723 |
return ETrue; |
|
2724 |
} |
|
2725 |
} |
|
2726 |
||
2727 |
if (domaccess == 0x3) |
|
2728 |
{
|
|
2729 |
// manager access |
|
2730 |
return EFalse; |
|
2731 |
} |
|
2732 |
if (domaccess == 0) |
|
2733 |
{
|
|
2734 |
// domain fault |
|
2735 |
aFaultStatus = 0x9 | ispage; |
|
2736 |
return ETrue; |
|
2737 |
} |
|
2738 |
||
2739 |
TInt perms; |
|
2740 |
if (ispage) |
|
2741 |
perms = (pte >> 4) & 0x3; |
|
2742 |
else |
|
2743 |
perms = (pde >> 10) & 0x3; |
|
2744 |
||
2745 |
if (aKernel || perms != 0x1) |
|
2746 |
return EFalse; |
|
2747 |
||
2748 |
// permission fault |
|
2749 |
aFaultStatus = 0xd | ispage; |
|
2750 |
return ETrue; |
|
2751 |
} |
|
2752 |
||
2753 |
TInt ArmMmu::RamDefragFault(TAny* aExceptionInfo) |
|
2754 |
{
|
|
2755 |
TArmExcInfo& exc=*(TArmExcInfo*)aExceptionInfo; |
|
2756 |
||
2757 |
// Get faulting address |
|
2758 |
TLinAddr faultAddress; |
|
2759 |
TBool prefetch=EFalse; |
|
2760 |
if(exc.iExcCode==EArmExceptionDataAbort) |
|
2761 |
{
|
|
2762 |
// Only handle page translation faults |
|
2763 |
if((exc.iFaultStatus & 0xf) != 0x7) |
|
2764 |
return KErrUnknown; |
|
2765 |
faultAddress = exc.iFaultAddress; |
|
2766 |
} |
|
2767 |
else if(exc.iExcCode==EArmExceptionPrefetchAbort) |
|
2768 |
{
|
|
2769 |
prefetch = ETrue; |
|
2770 |
faultAddress = exc.iR15; |
|
2771 |
} |
|
2772 |
else |
|
2773 |
return KErrUnknown; // Not data/prefetch abort |
|
2774 |
||
2775 |
TBool kernelmode = exc.iCpsr&EMaskMode != EUserMode; |
|
2776 |
||
2777 |
// Take system lock if not already held |
|
2778 |
NFastMutex* fm = NKern::HeldFastMutex(); |
|
2779 |
if(!fm) |
|
2780 |
NKern::LockSystem(); |
|
2781 |
else if(fm!=&TheScheduler.iLock) |
|
2782 |
{
|
|
2783 |
__KTRACE_OPT2(KMMU,KPANIC,Kern::Printf("Defrag: Fault with FM Held! %x (%O pc=%x)",faultAddress,TheCurrentThread,exc.iR15));
|
|
2784 |
Panic(EDefragFaultWhilstFMHeld); // Not allowed to hold mutexes |
|
2785 |
} |
|
2786 |
||
2787 |
TInt r = KErrUnknown; |
|
2788 |
||
2789 |
// check if the mapping of the page has already been restored and retry if so |
|
2790 |
if (prefetch) |
|
2791 |
{
|
|
2792 |
TUint32 fsr; |
|
2793 |
if (!FaultStatusFromLinAddr(faultAddress, kernelmode, fsr)) |
|
2794 |
{
|
|
2795 |
r = KErrNone; |
|
2796 |
goto leave; |
|
2797 |
} |
|
2798 |
} |
|
2799 |
else |
|
2800 |
{
|
|
2801 |
TPte* pt = SafePtePtrFromLinAddr(faultAddress); |
|
2802 |
if(!pt) |
|
2803 |
{
|
|
2804 |
r = KErrNotFound; |
|
2805 |
goto leave; |
|
2806 |
} |
|
2807 |
if ((*pt & 0x3) != 0) |
|
2808 |
{
|
|
2809 |
r = KErrNone; |
|
2810 |
goto leave; |
|
2811 |
} |
|
2812 |
} |
|
2813 |
||
2814 |
// check if the fault occurred in the page we are moving |
|
2815 |
if (iDisabledPte && TUint(faultAddress - iDisabledAddr) < TUint(KPageSize)) |
|
2816 |
{
|
|
2817 |
// restore access to the page |
|
2818 |
*iDisabledPte = iDisabledOldVal; |
|
2819 |
__DRAIN_WRITE_BUFFER; |
|
2820 |
InvalidateTLBForPage(iDisabledAddr); |
|
2821 |
iDisabledAddr = 0; |
|
2822 |
iDisabledPte = NULL; |
|
2823 |
iDisabledOldVal = 0; |
|
2824 |
r = KErrNone; |
|
2825 |
} |
|
2826 |
||
2827 |
leave: |
|
2828 |
// Restore system lock state |
|
2829 |
if (!fm) |
|
2830 |
NKern::UnlockSystem(); |
|
2831 |
||
2832 |
return r; |
|
2833 |
} |