// Copyright (c) 2002-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// e32/drivers/dma2_pil.cpp

// DMA Platform Independent Layer (PIL)

//

//

#include <drivers/dma.h>

#include <drivers/dma_hai.h>

#include <kernel/kern_priv.h>

// Symbian Min() & Max() are broken, so we have to define them ourselves

inline TUint Min(TUint aLeft, TUint aRight)

	{return(aLeft < aRight ? aLeft : aRight);}

inline TUint Max(TUint aLeft, TUint aRight)

	{return(aLeft > aRight ? aLeft : aRight);}

// Uncomment the following #define only when freezing the DMA2 export library.

//#define __FREEZE_DMA2_LIB

#ifdef __FREEZE_DMA2_LIB

TInt DmaChannelMgr::StaticExtension(TInt, TAny*) {return 0;}

TDmaChannel* DmaChannelMgr::Open(TUint32, TBool, TUint) {return 0;}

void DmaChannelMgr::Close(TDmaChannel*) {}

EXPORT_C const TDmaTestInfo& DmaTestInfo() {static TDmaTestInfo a; return a;}

EXPORT_C const TDmaV2TestInfo& DmaTestInfoV2() {static TDmaV2TestInfo a; return a;}

#endif	// #ifdef __FREEZE_DMA2_LIB

static const char KDmaPanicCat[] = "DMA " __FILE__;

//////////////////////////////////////////////////////////////////////

// DmaChannelMgr

//

// Wait, Signal, and Initialise are defined here in the PIL.

// Open, Close and Extension must be defined in the PSL.

NFastMutex DmaChannelMgr::Lock;

void DmaChannelMgr::Wait()

	{

	NKern::FMWait(&Lock);

	}

void DmaChannelMgr::Signal()

	{

	NKern::FMSignal(&Lock);

	}

TInt DmaChannelMgr::Initialise()

	{

	return KErrNone;

	}

class TDmaCancelInfo : public SDblQueLink

	{

public:

	TDmaCancelInfo();

	void Signal();

public:

	NFastSemaphore iSem;

	};

TDmaCancelInfo::TDmaCancelInfo()

	: iSem(0)

	{

	iNext = this;

	iPrev = this;

	}

void TDmaCancelInfo::Signal()

	{

	TDmaCancelInfo* p = this;

	FOREVER

		{

		TDmaCancelInfo* next = (TDmaCancelInfo*)p->iNext;

		if (p!=next)

			p->Deque();

		NKern::FSSignal(&p->iSem);	// Don't dereference p after this

		if (p==next)

			break;

		p = next;

		}

	}

//////////////////////////////////////////////////////////////////////////////

#ifdef __DMASIM__

#ifdef __WINS__

typedef TLinAddr TPhysAddr;

#endif

static inline TPhysAddr LinToPhys(TLinAddr aLin) {return aLin;}

#else

static inline TPhysAddr LinToPhys(TLinAddr aLin) {return Epoc::LinearToPhysical(aLin);}

#endif

//

// Return minimum of aMaxSize and size of largest physically contiguous block

// starting at aLinAddr.

//

static TInt MaxPhysSize(TLinAddr aLinAddr, const TInt aMaxSize)

	{

	const TPhysAddr physBase = LinToPhys(aLinAddr);

	TLinAddr lin = aLinAddr;

	TInt size = 0;

	for (;;)

		{

		// Round up the linear address to the next MMU page boundary

		const TLinAddr linBoundary = Kern::RoundToPageSize(lin + 1);

		size += linBoundary - lin;

		if (size >= aMaxSize)

			return aMaxSize;

		if ((physBase + size) != LinToPhys(linBoundary))

			return size;

		lin = linBoundary;

		}

	}

//////////////////////////////////////////////////////////////////////////////

// TDmac

TDmac::TDmac(const SCreateInfo& aInfo)

	: iMaxDesCount(aInfo.iDesCount),

	  iAvailDesCount(aInfo.iDesCount),

	  iHdrPool(NULL),

#ifndef __WINS__

	  iHwDesChunk(NULL),

#endif

	  iDesPool(NULL),

	  iDesSize(aInfo.iDesSize),

	  iCapsHwDes(aInfo.iCapsHwDes),

	  iFreeHdr(NULL)

	{

	__DMA_ASSERTD(iMaxDesCount > 0);

	__DMA_ASSERTD(iDesSize > 0);

	}

//

// Second-phase c'tor

//

TInt TDmac::Create(const SCreateInfo& aInfo)

	{

	iHdrPool = new SDmaDesHdr[iMaxDesCount];

	if (iHdrPool == NULL)

		{

		return KErrNoMemory;

		}

	TInt r = AllocDesPool(aInfo.iDesChunkAttribs);

	if (r != KErrNone)

		{

		return KErrNoMemory;

		}

	// Link all descriptor headers together on the free list

	iFreeHdr = iHdrPool;

	for (TInt i = 0; i < iMaxDesCount - 1; i++)

		iHdrPool[i].iNext = iHdrPool + i + 1;

	iHdrPool[iMaxDesCount-1].iNext = NULL;

	__DMA_INVARIANT();

	return KErrNone;

	}

TDmac::~TDmac()

	{

	__DMA_INVARIANT();

	FreeDesPool();

	delete[] iHdrPool;

	}

void TDmac::Transfer(const TDmaChannel& /*aChannel*/, const SDmaDesHdr& /*aHdr*/)

	{

	// TDmac needs to override this function if it has reported the channel

	// type for which the PIL calls it.

	__DMA_CANT_HAPPEN();

	}

void TDmac::Transfer(const TDmaChannel& /*aChannel*/, const SDmaDesHdr& /*aSrcHdr*/,

					 const SDmaDesHdr& /*aDstHdr*/)

	{

	// TDmac needs to override this function if it has reported the channel

	// type for which the PIL calls it.

	__DMA_CANT_HAPPEN();

	}

TInt TDmac::PauseTransfer(const TDmaChannel& /*aChannel*/)

	{

	// TDmac needs to override this function if it has reported support for

	// channel pausing/resuming.

	return KErrNotSupported;

	}

TInt TDmac::ResumeTransfer(const TDmaChannel& /*aChannel*/)

	{

	// TDmac needs to override this function if it has reported support for

	// channel pausing/resuming.

	return KErrNotSupported;

	}

TInt TDmac::AllocDesPool(TUint aAttribs)

	{

	// Calling thread must be in CS

	__ASSERT_CRITICAL;

	TInt r;

	if (iCapsHwDes)

		{

		const TInt size = iMaxDesCount * iDesSize;

#ifdef __WINS__

		(void)aAttribs;

		iDesPool = new TUint8[size];

		r = iDesPool ? KErrNone : KErrNoMemory;

#else

		// Chunk not mapped as supervisor r/w user none? incorrect mask passed by PSL

		__DMA_ASSERTD((aAttribs & EMapAttrAccessMask) == EMapAttrSupRw);

		TPhysAddr phys;

		r = Epoc::AllocPhysicalRam(size, phys);

		if (r == KErrNone)

			{

			r = DPlatChunkHw::New(iHwDesChunk, phys, size, aAttribs);

			if (r == KErrNone)

				{

				iDesPool = (TAny*)iHwDesChunk->LinearAddress();

				__KTRACE_OPT(KDMA, Kern::Printf("descriptor hw chunk created lin=0x%08X phys=0x%08X, size=0x%X",

												iHwDesChunk->iLinAddr, iHwDesChunk->iPhysAddr, size));

				}

			else

				Epoc::FreePhysicalRam(phys, size);

			}

#endif

		}

	else

		{

		iDesPool = new TDmaTransferArgs[iMaxDesCount];

		r = iDesPool ? KErrNone : KErrNoMemory;

		}

	return r;

	}

void TDmac::FreeDesPool()

	{

	// Calling thread must be in CS

	__ASSERT_CRITICAL;

	if (iCapsHwDes)

		{

#ifdef __WINS__

		delete[] iDesPool;

#else

		if (iHwDesChunk)

			{

			const TPhysAddr phys = iHwDesChunk->PhysicalAddress();

			const TInt size = iHwDesChunk->iSize;

			iHwDesChunk->Close(NULL);

			Epoc::FreePhysicalRam(phys, size);

			}

#endif

		}

	else

		{

		Kern::Free(iDesPool);

		}

	}

//

// Prealloc the given number of descriptors.

//

TInt TDmac::ReserveSetOfDes(TInt aCount)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("TDmac::ReserveSetOfDes count=%d", aCount));

	__DMA_ASSERTD(aCount > 0);

	TInt r = KErrTooBig;

	Wait();

	if (iAvailDesCount - aCount >= 0)

		{

		iAvailDesCount -= aCount;

		r = KErrNone;

		}

	Signal();

	__DMA_INVARIANT();

	return r;

	}

//

// Return the given number of preallocated descriptors to the free pool.

//

void TDmac::ReleaseSetOfDes(TInt aCount)

	{

	__DMA_ASSERTD(aCount >= 0);

	Wait();

	iAvailDesCount += aCount;

	Signal();

	__DMA_INVARIANT();

	}

//

// Queue DFC and update word used to communicate with channel DFC.

//

// Called in interrupt context by PSL.

//

void TDmac::HandleIsr(TDmaChannel& aChannel, TUint aEventMask, TBool aIsComplete)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("TDmac::HandleIsr"));

	// Function needs to be called by PSL in ISR context

	__DMA_ASSERTD(NKern::CurrentContext() == NKern::EInterrupt);

	// First the ISR callback stuff

	// Is this a transfer completion notification?

	if (aEventMask & EDmaCallbackRequestCompletion)

		{

		// If so, has the client requested an ISR callback?

		if (__e32_atomic_load_acq32(&aChannel.iIsrCbRequest))

			{

			__KTRACE_OPT(KDMA, Kern::Printf("ISR callback"));

			// Since iIsrCbRequest was set no threads will be

			// modifying the request queue.

			const DDmaRequest* const req = _LOFF(aChannel.iReqQ.First(), DDmaRequest, iLink);

			// We expect the request to have requested

			// ISR callback

			__NK_ASSERT_DEBUG(req->iIsrCb);

			TDmaCallback const cb = req->iDmaCb;

			TAny* const arg = req->iDmaCbArg;

			// Execute the client callback

			(*cb)(EDmaCallbackRequestCompletion,

				  (aIsComplete ? EDmaResultOK : EDmaResultError),

				  arg,

				  NULL);

			// Now let's see if the callback rescheduled the transfer request

			// (see TDmaChannel::IsrRedoRequest()).

			const TBool redo = aChannel.iRedoRequest;

			aChannel.iRedoRequest = EFalse;

			const TBool stop = __e32_atomic_load_acq32(&aChannel.iIsrDfc) &

				(TUint32)TDmaChannel::KCancelFlagMask;

			// There won't be another ISR callback if this callback didn't

			// reschedule the request, or the client cancelled all requests, or

			// this callback rescheduled the request with a DFC callback.

			if (!redo || stop || !req->iIsrCb)

				{

				__e32_atomic_store_rel32(&aChannel.iIsrCbRequest, EFalse);

				}

			if (redo && !stop)

				{

				// We won't queue the channel DFC in this case and just return.

				__KTRACE_OPT(KDMA, Kern::Printf("CB rescheduled xfer -> no DFC"));

				return;

				}

			// Not redoing or being cancelled means we've been calling the

			// request's ISR callback for the last time. We're going to

			// complete the request via the DFC in the usual way.

			}

		}

	// Now queue a DFC if necessary. The possible scenarios are:

	// a) DFC not queued (orig == 0)              -> update iIsrDfc + queue DFC

	// b) DFC queued, not running yet (orig != 0) -> just update iIsrDfc

	// c) DFC running / iIsrDfc not reset yet (orig != 0) -> just update iIsrDfc

	// d) DFC running / iIsrDfc already reset (orig == 0) -> update iIsrDfc + requeue DFC

	// Set error flag if necessary.

	const TUint32 inc = aIsComplete ? 1u : TUint32(TDmaChannel::KErrorFlagMask) | 1u;

	// Add 'inc' (interrupt count increment + poss. error flag) to 'iIsrDfc' if

	// cancel flag is not set, do nothing otherwise. Assign original value of

	// 'iIsrDfc' to 'orig' in any case.

	const TUint32 orig = __e32_atomic_tau_ord32(&aChannel.iIsrDfc,

												TUint32(TDmaChannel::KCancelFlagMask),

												0,

												inc);

	// As transfer should be suspended when an error occurs, we

	// should never get there with the error flag already set.

	__DMA_ASSERTD((orig & inc & (TUint32)TDmaChannel::KErrorFlagMask) == 0);

	if (orig == 0)

		{

		aChannel.iDfc.Add();

		}

	}

TInt TDmac::InitDes(const SDmaDesHdr& aHdr, const TDmaTransferArgs& aTransferArgs)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("TDmac::InitDes"));

	TInt r;

	if (iCapsHwDes)

		{

		__KTRACE_OPT(KDMA, Kern::Printf("iCaps.iHwDescriptors"));

		r = InitHwDes(aHdr, aTransferArgs);

		}

	else

		{

		TDmaTransferArgs& args = HdrToDes(aHdr);

		args = aTransferArgs;

		r = KErrNone;

		}

	return r;

	}

TInt TDmac::InitHwDes(const SDmaDesHdr& /*aHdr*/, const TDmaTransferArgs& /*aTransferArgs*/)

	{

	// concrete controller must override if SDmacCaps::iHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::InitSrcHwDes(const SDmaDesHdr& /*aHdr*/, const TDmaTransferArgs& /*aTransferArgs*/)

	{

	// concrete controller must override if SDmacCaps::iAsymHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::InitDstHwDes(const SDmaDesHdr& /*aHdr*/, const TDmaTransferArgs& /*aTransferArgs*/)

	{

	// concrete controller must override if SDmacCaps::iAsymHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::UpdateDes(const SDmaDesHdr& aHdr, TUint32 aSrcAddr, TUint32 aDstAddr,

					  TUint aTransferCount, TUint32 aPslRequestInfo)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("TDmac::UpdateDes"));

	TInt r;

	if (iCapsHwDes)

		{

		__KTRACE_OPT(KDMA, Kern::Printf("iCaps.iHwDescriptors"));

		r = UpdateHwDes(aHdr, aSrcAddr, aDstAddr, aTransferCount, aPslRequestInfo);

		}

	else

		{

		TDmaTransferArgs& args = HdrToDes(aHdr);

		if (aSrcAddr != KPhysAddrInvalid)

			args.iSrcConfig.iAddr = aSrcAddr;

		if (aDstAddr != KPhysAddrInvalid)

			args.iDstConfig.iAddr = aDstAddr;

		if (aTransferCount)

			args.iTransferCount = aTransferCount;

		if (aPslRequestInfo)

			args.iPslRequestInfo = aPslRequestInfo;

		r = KErrNone;

		}

	return r;

	}

TInt TDmac::UpdateHwDes(const SDmaDesHdr& /*aHdr*/, TUint32 /*aSrcAddr*/, TUint32 /*aDstAddr*/,

						TUint /*aTransferCount*/, TUint32 /*aPslRequestInfo*/)

	{

	// concrete controller must override if SDmacCaps::iHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::UpdateSrcHwDes(const SDmaDesHdr& /*aHdr*/, TUint32 /*aSrcAddr*/,

						   TUint /*aTransferCount*/, TUint32 /*aPslRequestInfo*/)

	{

	// concrete controller must override if SDmacCaps::iAsymHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::UpdateDstHwDes(const SDmaDesHdr& /*aHdr*/, TUint32 /*aDstAddr*/,

						   TUint /*aTransferCount*/, TUint32 /*aPslRequestInfo*/)

	{

	// concrete controller must override if SDmacCaps::iAsymHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

void TDmac::ChainHwDes(const SDmaDesHdr& /*aHdr*/, const SDmaDesHdr& /*aNextHdr*/)

	{

	// concrete controller must override if SDmacCaps::iHwDescriptors set

	__DMA_CANT_HAPPEN();

	}

void TDmac::AppendHwDes(const TDmaChannel& /*aChannel*/, const SDmaDesHdr& /*aLastHdr*/,

						const SDmaDesHdr& /*aNewHdr*/)

	{

 	// concrete controller must override if SDmacCaps::iHwDescriptors set

	__DMA_CANT_HAPPEN();

	}