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// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32\include\nkern\x86\nk_plat.h
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//
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// WARNING: This file contains some APIs which are internal and are subject
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// to change without notice. Such APIs should therefore not be used
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// outside the Kernel and Hardware Services package.
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//
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/**
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@file
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@internalComponent
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*/
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#ifndef __NK_X86_H__
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#define __NK_X86_H__
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#include <nk_cpu.h>
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#define IRQ_STACK_SIZE 1024
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//#define __SCHEDULER_MACHINE_CODED__
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//#define __DFC_MACHINE_CODED__
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//#define __MSTIM_MACHINE_CODED__
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//#define __PRI_LIST_MACHINE_CODED__
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//#define __FAST_SEM_MACHINE_CODED__
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//#define __FAST_MUTEX_MACHINE_CODED__
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// TScheduler member data
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#define i_ExcInfo iExtras[15] // pointer to exception info for crash debugger
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class TX86RegSet;
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class NThread : public NThreadBase
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{
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public:
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TInt Create(SNThreadCreateInfo& anInfo, TBool aInitial);
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inline void Stillborn()
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{}
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void GetUserContext(TX86RegSet& aContext);
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void ModifyUsp(TLinAddr aUsp);
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public:
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TUint32 i_NThread_Pad1;
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TUint64 iCoprocessorState[64]; // state of FPU, SSE, SSE2
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};
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__ASSERT_COMPILE(!(_FOFF(NThread,iCoprocessorState)&7));
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// Positions of registers on stack, relative to saved SP
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struct SThreadStack
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{
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TUint32 iCR0;
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TUint32 iEbx;
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TUint32 iEsi;
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TUint32 iEdi;
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TUint32 iEbp;
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TUint32 iGs;
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TUint32 iFs;
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TUint32 iReschedFlag;
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TUint32 iEip;
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};
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extern "C" {
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GLREF_D TUint32 X86_IrqStack[IRQ_STACK_SIZE/4];
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GLREF_D TLinAddr X86_IrqHandler;
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GLREF_D TInt X86_IrqNestCount;
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GLREF_D SCpuIdleHandler CpuIdleHandler;
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GLREF_D TBool X86_UseGlobalPTEs;
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GLREF_D TUint64 DefaultCoprocessorState[64];
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}
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/** Ensure the ordering of explicit memory writes
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On x86 this is a no-op
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*/
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#define wmb()
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#define smp_wmb()
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/** Ensure the ordering of explicit memory accesses
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On x86 any instruction with the LOCK prefix does this
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*/
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#ifdef __GCC32__
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#define mb() __asm__ __volatile__("lock add dword ptr [esp], 0" : : : "memory")
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#else
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#define mb() do { _asm lock add dword ptr [esp], 0 } while (0)
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#endif
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#define smp_mb()
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// End of file
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#endif
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