author | Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com> |
Tue, 31 Aug 2010 16:34:26 +0300 | |
branch | RCL_3 |
changeset 43 | c1f20ce4abcf |
parent 0 | a41df078684a |
child 44 | 3e88ff8f41d5 |
permissions | -rw-r--r-- |
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// Copyright (c) 2007-2009 Nokia Corporation and/or its subsidiary(-ies). |
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// All rights reserved. |
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// This component and the accompanying materials are made available |
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// under the terms of the License "Eclipse Public License v1.0" |
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// which accompanies this distribution, and is available |
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// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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// |
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// Initial Contributors: |
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// Nokia Corporation - initial contribution. |
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// |
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// Contributors: |
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// |
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// Description: |
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// e32\include\nkernsmp\x86\nk_plat.h |
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// |
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// WARNING: This file contains some APIs which are internal and are subject |
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// to change without notice. Such APIs should therefore not be used |
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// outside the Kernel and Hardware Services package. |
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// |
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/** |
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@file |
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@internalComponent |
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*/ |
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#ifndef __NK_X86_H__ |
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#define __NK_X86_H__ |
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#include <nk_cpu.h> |
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class TSubScheduler; |
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class TScheduler; |
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struct TX86Tss; |
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// TSubScheduler member data |
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struct TSubSchedulerX |
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{ |
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TUint32 iSSXP[9]; |
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volatile TUint32 iIrqCount; // count of interrupts handled |
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TAny* iExcInfo; // pointer to exception info for crash debugger |
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volatile TInt iCrashState; // 0=normal, 1=this CPU faulted, 2=this CPU has received an NMI and halted |
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TUint32 iAPICID; // Local APIC ID for this CPU (starts at -1) |
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volatile TInt iIrqNestCount; // IRQ nest count for this CPU (starts at -1) |
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TLinAddr iIrqStackTop; // Top of IRQ stack for this CPU |
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TX86Tss* iTss; // Address of TSS for this CPU |
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SRatioInv iCpuFreqRI; // Ratio of CPU frequency to maximum possible CPU frequency |
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SRatioInv iTimerFreqRI; // Ratio of CPU local timer frequency to maximum possible |
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volatile TUint64HL iTimestampOffset; // 64 bit value to add to CPU TSC to give NKern::Timestamp() |
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TUint32 iSSXP2[36]; |
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TUint64 iSSXP3; // one 64 bit value to guarantee alignment |
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}; |
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// TScheduler member data |
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struct TSchedulerX |
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{ |
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TUint64 iTimerMax; // Maximum per-CPU timer frequency (after prescaling) |
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TUint32 iSXP[30]; |
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}; |
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#define CRASH_IPI_VECTOR 0x27 |
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#define RESCHED_IPI_VECTOR 0x28 |
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#define TIMESLICE_VECTOR 0x29 |
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#define GENERIC_IPI_VECTOR 0x2A |
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#define TRANSFERRED_IRQ_VECTOR 0x2E |
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#define SPURIOUS_INTERRUPT_VECTOR 0x2F |
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extern "C" TSubScheduler* SubSchedulerLookupTable[256]; // look up subscheduler from APIC ID |
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#define IRQ_STACK_SIZE 1024 |
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//#define __SCHEDULER_MACHINE_CODED__ |
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//#define __DFC_MACHINE_CODED__ |
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//#define __MSTIM_MACHINE_CODED__ |
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//#define __PRI_LIST_MACHINE_CODED__ |
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//#define __FAST_SEM_MACHINE_CODED__ |
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//#define __FAST_MUTEX_MACHINE_CODED__ |
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class TX86RegSet; |
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class NThread : public NThreadBase |
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{ |
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public: |
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TInt Create(SNThreadCreateInfo& anInfo, TBool aInitial); |
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void Stillborn(); |
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void GetUserContext(TX86RegSet& aContext, TUint32& aAvailRegMask); |
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void SetUserContext(const TX86RegSet& aContext, TUint32& aRegMask); |
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void GetSystemContext(TX86RegSet& aContext, TUint32& aAvailRegMask); |
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void CompleteContextSave(); |
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public: |
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TUint64 iCoprocessorState[64]; // state of FPU, SSE, SSE2 |
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}; |
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__ASSERT_COMPILE(!(_FOFF(NThread,iCoprocessorState)&7)); |
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// Positions of registers on stack, relative to saved SP |
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struct SThreadReschedStack |
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{ |
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TUint32 iCR0; |
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TUint32 iReschedFlag; |
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TUint32 iEip; |
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TUint32 iReason; |
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}; |
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// Registers pushed on stack for all exceptions other than slow exec |
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struct SThreadExcStack |
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{ |
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TUint32 iEcx; |
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TUint32 iEdx; |
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TUint32 iEbx; |
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TUint32 iEsi; |
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TUint32 iEdi; |
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TUint32 iEbp; |
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TUint32 iEax; |
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TUint32 iDs; |
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TUint32 iEs; |
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TUint32 iFs; |
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TUint32 iGs; |
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TUint32 iVector; |
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TUint32 iError; |
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TUint32 iEip; |
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TUint32 iCs; |
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TUint32 iEflags; |
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TUint32 iEsp3; // only if iCs does not indicate CPL=0 |
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TUint32 iSs3; // only if iCs does not indicate CPL=0 |
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}; |
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// Registers pushed on stack for slow exec |
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struct SThreadSlowExecStack |
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{ |
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TUint32 iEcx; |
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TUint32 iEdx; |
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TUint32 iEbx; |
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TUint32 iEsi; |
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TUint32 iEdi; |
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TUint32 iEbp; |
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TUint32 iEax; |
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TUint32 iDs; |
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TUint32 iEs; |
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TUint32 iFs; |
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TUint32 iGs; |
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TUint32 iArgs[8]; // space for extra arguments copied from user side |
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TUint32 iVector; |
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TUint32 iError; |
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TUint32 iEip; |
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TUint32 iCs; |
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TUint32 iEflags; |
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TUint32 iEsp3; // only if iCs does not indicate CPL=0 |
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TUint32 iSs3; // only if iCs does not indicate CPL=0 |
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}; |
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// Top of stack after thread creation for threads with parameter block passed |
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// by value. |
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struct SThreadStackStub |
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{ |
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enum {EVector=0xffffffffu}; |
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TLinAddr iPBlock; // pointer to parameter block |
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TUint32 iVector; |
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TUint32 iError; |
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TUint32 iEip; |
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TUint32 iCs; |
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TUint32 iEflags; |
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}; |
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// Stack structure at thread creation either at top of stack (if parameter block |
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// passed by reference) or below parameter block if passed by value. |
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struct SThreadInitStack |
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{ |
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enum {EVector=0xfffffffeu}; |
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SThreadReschedStack iR; |
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SThreadExcStack iX; |
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}; |
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extern "C" { |
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GLREF_D TLinAddr X86_IrqHandler; |
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GLREF_D SCpuIdleHandler CpuIdleHandler; |
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GLREF_D TUint32 X86_CPUID; |
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GLREF_D TBool X86_UseGlobalPTEs; |
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GLREF_D TUint64 DefaultCoprocessorState[64]; |
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} |
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/** Ensure the ordering of explicit memory writes |
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On x86 this is a no-op |
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*/ |
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#define wmb() |
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#define smp_wmb() wmb() |
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/** Ensure the ordering of explicit memory accesses |
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On x86 any instruction with the LOCK prefix does this |
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*/ |
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#ifdef __GCC32__ |
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#define mb() __asm__ __volatile__("lock add dword ptr [esp], 0" : : : "memory") |
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#else |
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#define mb() do { _asm lock add dword ptr [esp], 0 } while (0) |
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#endif |
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#define smp_mb() mb() |
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/** |
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@internalComponent |
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*/ |
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extern "C" void send_resched_ipis(TUint32 aMask); |
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// End of file |
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#endif |