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1 /* |
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2 * Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of the License "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * |
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16 */ |
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17 // |
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18 // TO DO: (mandatory) |
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19 // |
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20 // Add here a definition for your CPU (list in CONFIG.INC) |
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21 // |
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22 macro __CPU_ARM11MP__ |
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23 // |
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24 // TO DO: (mandatory) |
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25 // |
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26 // Add here a definition for your Memory Model |
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27 // |
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28 #define MM_MULTIPLE |
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29 // |
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30 // TO DO: (mandatory) |
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31 // |
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32 // Macro which generates the names for the binaries for this platform |
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33 // |
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34 #ifndef VariantTarget |
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35 #define VariantTarget(name,ext) _ne1_tb_##name##.##ext |
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36 #endif |
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37 |
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38 #ifndef VariantMediaDefIncludePath |
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39 #define VariantMediaDefIncludePath /epoc32/include/ne1_tb |
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40 #endif |
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41 |
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42 // Used in MMP files for include paths e.g. to hcrconfig.h header |
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43 #ifndef VariantIncludePath |
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44 #define VariantIncludePath /epoc32/include/ne1_tb |
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45 #endif |
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46 |
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47 |
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48 //Include debug support |
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49 macro __DEBUGGER_SUPPORT__ |
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50 |
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51 // |
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52 // TO DO: |
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53 // |
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54 // If euser is built from the variant, uncomment the following line to build it |
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55 // as ARM rather than Thumb |
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56 // |
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57 //#define __BUILD_VARIANT_EUSER_AS_ARM__ |
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58 // |
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59 // TO DO: (optional) |
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60 // |
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61 // To replace some of the generic utility functions with variant specific |
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62 // versions (eg to replace memcpy with a version optimised for the hardware), |
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63 // uncomment the two lines below and edit the files in the replacementUtils |
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64 // directory. |
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65 // |
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66 //#define REPLACE_GENERIC_UTILS |
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67 //#define VariantReplacementUtilsPath ne1_tb/replacement_utils |
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68 // |
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69 // TO DO: (optional) |
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70 // |
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71 // Enable BTrace support in release versions of the kernel by adding |
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72 // the following BTRACE macro declarations |
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73 // |
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74 macro BTRACE_KERNEL_ALL |
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75 // |
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76 // TO DO: |
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77 // |
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78 // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor. |
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79 // |
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80 //#define __CPU_ARM1136_IS_R1__ |
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81 // |
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82 |
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83 // Include the following line if default memory mapping should use shared memory. |
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84 // Should be on for multicore (SMP) devices. |
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85 |
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86 macro __CPU_USE_SHARED_MEMORY |
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87 |
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88 // Include the following line if CPU cannot tolerate the presence of nonshared |
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89 // cached memory. This seems to be the case for the ARM11 MPCore - corruption |
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90 // of data is observed in non-shared cached regions if __CPU_USE_SHARED_MEMORY |
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91 // is used. |
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92 |
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93 macro __CPU_FORCE_SHARED_MEMORY_IF_CACHED |
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94 |
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95 |
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96 |
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97 // TO DO: |
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98 // |
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99 // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973 |
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100 // "CLREX instruction might be ignored during data cache line fill" |
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101 // is fixed on this hardware. |
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102 // |
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103 //#define __CPU_ARM1136_ERRATUM_406973_FIXED |
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104 |
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105 // Uncomment next line if using the ARM1136 processor and ARM1136 Erratum 408022 |
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106 // "Cancelled write to CONTEXTID register might update ASID" |
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107 // is fixed on this hardware. |
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108 // |
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109 //#define __CPU_ARM1136_ERRATUM_408022_FIXED |
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110 |
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111 |
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112 // Uncomment if: |
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113 // 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache |
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114 // operation might fail to invalidate some lines if coincident with linefill" |
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115 // is fixed on this hardware, or |
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116 // 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache |
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117 // operation might fail to invalidate some lines if coincident with linefill |
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118 // is fixed on this hardware. |
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119 // Workaround: |
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120 // 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. |
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121 // 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. |
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122 // If this macro is enabled, it should be accompanied by: |
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123 // "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh |
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124 // |
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125 // #define __CPU_ARM1136_ERRATUM_411920_FIXED |
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126 |
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127 macro FAULTY_NONSHARED_DEVICE_MEMORY |
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128 |
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129 #define AsspNKernIncludePath /epoc32/include/assp/naviengine/nkern |
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130 |
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131 // FIQ can not be disabled on naviengine, tell kernel to ignore it... |
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132 macro __FIQ_IS_UNCONTROLLED__ |
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133 |
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134 macro MONITOR_THREAD_CPU_TIME |
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135 |
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136 #if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__) |
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137 library VariantTarget(kanaviengine,lib) |
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138 #endif |
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139 |