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1 // Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // This file contains stepping code refactored from rm_debug_kerneldriver.cpp/rm_debug_kerneldriver.h |
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15 // |
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16 |
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17 #include <e32def.h> |
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18 #include <e32def_private.h> |
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19 #include <e32cmn.h> |
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20 #include <e32cmn_private.h> |
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21 #include <kernel/kernel.h> |
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22 #include <kernel/kern_priv.h> |
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23 #include <nk_trace.h> |
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24 #include <arm.h> |
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25 #include <rm_debug_api.h> |
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26 |
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27 #include "d_rmd_stepping.h" |
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28 #include "d_rmd_breakpoints.h" |
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29 #include "rm_debug_kerneldriver.h" // needed to access DRM_DebugChannel |
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30 #include "rm_debug_driver.h" |
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31 #include "debug_logging.h" |
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32 |
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33 using namespace Debug; |
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34 |
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35 // |
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36 // DRMDStepping::DRMDStepping |
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37 // |
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38 DRMDStepping::DRMDStepping(DRM_DebugChannel* aChannel) |
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39 : |
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40 iChannel(aChannel) |
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41 { |
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42 // to do |
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43 } |
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44 |
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45 // |
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46 // DRMDStepping::~DRM_DebugChannel |
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47 // |
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48 DRMDStepping::~DRMDStepping() |
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49 { |
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50 // to do |
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51 } |
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52 |
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53 // |
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54 // DRMDStepping::IsExecuted |
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55 // |
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56 TBool DRMDStepping::IsExecuted(TUint8 aCondition ,TUint32 aStatusRegister) |
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57 { |
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58 LOG_MSG("DRMDStepping::IsExecuted()"); |
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59 |
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60 TBool N = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000008; |
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61 TBool Z = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000004; |
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62 TBool C = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000002; |
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63 TBool V = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000001; |
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64 |
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65 switch(aCondition) |
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66 { |
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67 case 0: |
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68 return Z; |
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69 case 1: |
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70 return !Z; |
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71 case 2: |
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72 return C; |
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73 case 3: |
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74 return !C; |
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75 case 4: |
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76 return N; |
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77 case 5: |
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78 return !N; |
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79 case 6: |
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80 return V; |
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81 case 7: |
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82 return !V; |
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83 case 8: |
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84 return (C && !Z); |
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85 case 9: |
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86 return (!C || Z); |
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87 case 10: |
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88 return (N == V); |
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89 case 11: |
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90 return (N != V); |
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91 case 12: |
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92 return ((N == V) && !Z); |
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93 case 13: |
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94 return (Z || (N != V)); |
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95 case 14: |
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96 case 15: |
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97 return ETrue; |
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98 } |
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99 |
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100 return EFalse; |
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101 } |
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102 |
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103 // |
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104 // DRMDStepping::IsPreviousInstructionMovePCToLR |
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105 // |
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106 TBool DRMDStepping::IsPreviousInstructionMovePCToLR(DThread *aThread) |
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107 { |
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108 LOG_MSG("DRMDStepping::IsPreviousInstructionMovePCToLR()"); |
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109 |
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110 TInt err = KErrNone; |
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111 |
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112 // there are several types of instructions that modify the PC that aren't |
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113 // designated as linked or non linked branches. the way gcc generates the |
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114 // code can tell us whether or not these instructions are to be treated as |
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115 // linked branches. the main cases are bx and any type of mov or load or |
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116 // arithmatic operation that changes the PC. if these are really just |
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117 // function calls that will return, gcc will generate a mov lr, pc |
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118 // instruction as the previous instruction. note that this is just for arm |
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119 // and armi |
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120 |
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121 // get the address of the previous instruction |
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122 TUint32 address = 0; |
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123 err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, address); |
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124 if(err != KErrNone) |
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125 { |
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126 LOG_MSG2("Non-zero error code discarded: %d", err); |
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127 } |
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128 address -= 4; |
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129 |
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130 TBuf8<4> previousInstruction; |
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131 err = iChannel->DoReadMemory(aThread, address, 4, previousInstruction); |
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132 if (KErrNone != err) |
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133 { |
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134 LOG_MSG2("Error %d reading memory at address %x", address); |
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135 return EFalse; |
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136 } |
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137 |
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138 const TUint32 movePCToLRIgnoringCondition = 0x01A0E00F; |
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139 |
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140 TUint32 inst = *(TUint32 *)previousInstruction.Ptr(); |
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141 |
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142 if ((inst & 0x0FFFFFFF) == movePCToLRIgnoringCondition) |
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143 { |
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144 return ETrue; |
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145 } |
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146 |
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147 return EFalse; |
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148 } |
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149 |
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150 // |
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151 // DRMDStepping::DecodeDataProcessingInstruction |
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152 // |
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153 void DRMDStepping::DecodeDataProcessingInstruction(TUint8 aOpcode, TUint32 aOp1, TUint32 aOp2, TUint32 aStatusRegister, TUint32 &aBreakAddress) |
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154 { |
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155 LOG_MSG("DRMDStepping::DecodeDataProcessingInstruction()"); |
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156 |
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157 switch(aOpcode) |
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158 { |
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159 case 0: |
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160 { |
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161 // AND |
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162 aBreakAddress = aOp1 & aOp2; |
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163 break; |
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164 } |
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165 case 1: |
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166 { |
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167 // EOR |
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168 aBreakAddress = aOp1 ^ aOp2; |
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169 break; |
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170 } |
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171 case 2: |
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172 { |
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173 // SUB |
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174 aBreakAddress = aOp1 - aOp2; |
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175 break; |
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176 } |
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177 case 3: |
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178 { |
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179 // RSB |
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180 aBreakAddress = aOp2 - aOp1; |
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181 break; |
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182 } |
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183 case 4: |
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184 { |
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185 // ADD |
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186 aBreakAddress = aOp1 + aOp2; |
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187 break; |
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188 } |
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189 case 5: |
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190 { |
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191 // ADC |
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192 aBreakAddress = aOp1 + aOp2 + (aStatusRegister & arm_carry_bit()) ? 1 : 0; |
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193 break; |
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194 } |
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195 case 6: |
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196 { |
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197 // SBC |
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198 aBreakAddress = aOp1 - aOp2 - (aStatusRegister & arm_carry_bit()) ? 0 : 1; |
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199 break; |
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200 } |
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201 case 7: |
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202 { |
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203 // RSC |
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204 aBreakAddress = aOp2 - aOp1 - (aStatusRegister & arm_carry_bit()) ? 0 : 1; |
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205 break; |
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206 } |
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207 case 12: |
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208 { |
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209 // ORR |
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210 aBreakAddress = aOp1 | aOp2; |
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211 break; |
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212 } |
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213 case 13: |
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214 { |
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215 // MOV |
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216 aBreakAddress = aOp2; |
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217 break; |
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218 } |
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219 case 14: |
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220 { |
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221 // BIC |
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222 aBreakAddress = aOp1 & ~aOp2; |
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223 break; |
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224 } |
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225 case 15: |
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226 { |
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227 // MVN |
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228 aBreakAddress = ~aOp2; |
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229 break; |
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230 } |
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231 } |
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232 } |
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233 |
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234 // |
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235 // DRMDStepping::CurrentInstruction |
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236 // |
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237 // Returns the current instruction bitpattern (either 32-bits or 16-bits) if possible |
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238 TInt DRMDStepping::CurrentInstruction(DThread* aThread, TUint32& aInstruction) |
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239 { |
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240 LOG_MSG("DRMDStepping::CurrentInstruction"); |
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241 |
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242 // What is the current PC? |
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243 TUint32 pc; |
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244 ReturnIfError(CurrentPC(aThread,pc)); |
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245 |
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246 // Read it one byte at a time to ensure alignment doesn't matter |
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247 TUint32 inst = 0; |
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248 for(TInt i=3;i>=0;i--) |
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249 { |
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250 |
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251 TBuf8<1> instruction; |
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252 TInt err = iChannel->DoReadMemory(aThread, (pc+i), 1, instruction); |
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253 if (KErrNone != err) |
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254 { |
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255 LOG_MSG2("DRMDStepping::CurrentInstruction : Failed to read memory at current PC: return 0x%08x",pc); |
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256 return err; |
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257 } |
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258 |
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259 inst = (inst << 8) | (*(TUint8 *)instruction.Ptr()); |
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260 } |
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261 |
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262 aInstruction = inst; |
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263 |
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264 LOG_MSG2("DRMDStepping::CurrentInstruction 0x%08x", aInstruction); |
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265 |
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266 return KErrNone; |
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267 } |
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268 |
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269 // |
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270 // DRMDStepping::CurrentArchMode |
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271 // |
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272 // Determines architecture mode from the supplied cpsr |
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273 TInt DRMDStepping::CurrentArchMode(const TUint32 aCpsr, Debug::TArchitectureMode& aMode) |
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274 { |
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275 // Thumb2 work will depend on having a suitable cpu architecture to compile for... |
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276 #ifdef ECpuJf |
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277 // State table as per ARM ARM DDI0406A, section A.2.5.1 |
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278 if(aCpsr & ECpuJf) |
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279 { |
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280 if (aCpsr & ECpuThumb) |
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281 { |
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282 // ThumbEE (Thumb2) |
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283 aMode = Debug::EThumb2EEMode; |
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284 } |
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285 else |
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286 { |
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287 // Jazelle mode - not supported |
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288 return KErrNotSupported; |
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289 } |
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290 } |
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291 else |
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292 #endif |
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293 { |
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294 if (aCpsr & ECpuThumb) |
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295 { |
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296 // Thumb mode |
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297 aMode = Debug::EThumbMode; |
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298 } |
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299 else |
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300 { |
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301 // ARM mode |
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302 aMode = Debug::EArmMode; |
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303 } |
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304 } |
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305 |
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306 return KErrNone; |
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307 } |
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308 |
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309 // |
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310 // DRMDStepping::PCAfterInstructionExecutes |
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311 // |
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312 // Note, this function pretty much ignores all the arguments except for aThread. |
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313 // The arguments continue to exist so that the function has the same prototype as |
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314 // the original from Nokia. In the long term this function will be re-factored |
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315 // to remove obsolete parameters. |
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316 // |
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317 TUint32 DRMDStepping::PCAfterInstructionExecutes(DThread *aThread, TUint32 aCurrentPC, TUint32 aStatusRegister, TInt aInstSize, /*TBool aStepInto,*/ TUint32 &aNewRangeEnd, TBool &aChangingModes) |
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318 { |
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319 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes()"); |
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320 |
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321 // by default we will set the breakpoint at the next instruction |
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322 TUint32 breakAddress = aCurrentPC + aInstSize; |
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323 |
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324 TInt err = KErrNone; |
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325 |
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326 // determine the architecture |
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327 TUint32 cpuid; |
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328 asm("mrc p15, 0, cpuid, c0, c0, 0 "); |
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329 LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpuid = 0x%08x\n",cpuid); |
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330 |
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331 cpuid >>= 8; |
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332 cpuid &= 0xFF; |
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333 |
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334 // determine the architecture mode for the current instruction |
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335 TArchitectureMode mode = EArmMode; // Default assumption is ARM |
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336 |
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337 // Now we must examine the CPSR to read the T and J bits. See ARM ARM DDI0406A, section B1.3.3 |
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338 TUint32 cpsr; |
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339 |
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340 ReturnIfError(CurrentCPSR(aThread,cpsr)); |
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341 LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpsr = 0x%08x\n",cpsr); |
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342 |
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343 // Determine the mode |
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344 ReturnIfError(CurrentArchMode(cpsr,mode)); |
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345 |
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346 // Decode instruction based on current CPU mode |
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347 switch(mode) |
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348 { |
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349 case Debug::EArmMode: |
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350 { |
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351 // Obtain the current instruction bit pattern |
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352 TUint32 inst; |
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353 ReturnIfError(CurrentInstruction(aThread,inst)); |
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354 |
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355 LOG_MSG2("Current instruction: %x", inst); |
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356 |
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357 // check the conditions to see if this will actually get executed |
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358 if (IsExecuted(((inst>>28) & 0x0000000F), aStatusRegister)) |
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359 { |
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360 switch(arm_opcode(inst)) // bits 27-25 |
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361 { |
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362 case 0: |
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363 { |
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364 switch((inst & 0x00000010) >> 4) // bit 4 |
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365 { |
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366 case 0: |
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367 { |
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368 switch((inst & 0x01800000) >> 23) // bits 24-23 |
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369 { |
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370 case 2: |
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371 { |
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372 // move to/from status register. pc updates not allowed |
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373 // or TST, TEQ, CMP, CMN which don't modify the PC |
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374 break; |
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375 } |
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376 default: |
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377 { |
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378 // Data processing immediate shift |
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379 if (arm_rd(inst) == PC_REGISTER) |
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380 { |
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381 TUint32 rn = aCurrentPC + 8; |
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382 if (arm_rn(inst) != PC_REGISTER) // bits 19-16 |
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383 { |
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384 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); |
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385 if(err != KErrNone) |
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386 { |
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387 LOG_MSG2("Non-zero error code discarded: %d", err); |
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388 } |
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389 } |
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390 |
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391 TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister); |
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392 |
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393 DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress); |
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394 } |
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395 break; |
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396 } |
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397 } |
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398 break; |
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399 } |
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400 case 1: |
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401 { |
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402 switch((inst & 0x00000080) >> 7) // bit 7 |
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403 { |
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404 case 0: |
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405 { |
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406 switch((inst & 0x01900000) >> 20) // bits 24-23 and bit 20 |
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407 { |
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408 case 0x10: |
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409 { |
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410 // from figure 3-3 |
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411 switch((inst & 0x000000F0) >> 4) // bits 7-4 |
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412 { |
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413 case 1: |
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414 { |
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415 if (((inst & 0x00400000) >> 22) == 0) // bit 22 |
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416 { |
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417 // BX |
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418 // this is a strange case. normally this is used in the epilogue to branch the the link |
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419 // register. sometimes it is used to call a function, and the LR is stored in the previous |
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420 // instruction. since what we want to do is different for the two cases when stepping over, |
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421 // we need to read the previous instruction to see what we should do |
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422 err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress); |
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423 if(err != KErrNone) |
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424 { |
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425 LOG_MSG2("Non-zero error code discarded: %d", err); |
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426 } |
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427 |
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428 if ((breakAddress & 0x00000001) == 1) |
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429 { |
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430 aChangingModes = ETrue; |
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431 } |
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432 |
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433 breakAddress &= 0xFFFFFFFE; |
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434 } |
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435 break; |
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436 } |
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437 case 3: |
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438 { |
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439 // BLX |
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440 { |
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441 err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress); |
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442 if(err != KErrNone) |
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443 { |
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444 LOG_MSG2("Non-zero error code discarded: %d", err); |
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445 } |
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446 |
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447 if ((breakAddress & 0x00000001) == 1) |
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448 { |
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449 aChangingModes = ETrue; |
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450 } |
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451 |
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452 breakAddress &= 0xFFFFFFFE; |
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453 } |
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454 break; |
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455 } |
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456 default: |
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457 { |
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458 // either doesn't modify the PC or it is illegal to |
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459 break; |
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460 } |
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461 } |
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462 break; |
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463 } |
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464 default: |
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465 { |
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466 // Data processing register shift |
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467 if (((inst & 0x01800000) >> 23) == 2) // bits 24-23 |
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468 { |
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469 // TST, TEQ, CMP, CMN don't modify the PC |
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470 } |
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471 else if (arm_rd(inst) == PC_REGISTER) |
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472 { |
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473 // destination register is the PC |
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474 TUint32 rn = aCurrentPC + 8; |
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475 if (arm_rn(inst) != PC_REGISTER) // bits 19-16 |
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476 { |
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477 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); |
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478 if(err != KErrNone) |
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479 { |
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480 LOG_MSG2("Non-zero error code discarded: %d", err); |
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481 } |
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482 } |
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483 |
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484 TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister); |
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485 |
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486 DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress); |
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487 } |
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488 break; |
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489 } |
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490 } |
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491 break; |
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492 } |
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493 default: |
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494 { |
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495 // from figure 3-2, updates to the PC illegal |
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496 break; |
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497 } |
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498 } |
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499 break; |
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500 } |
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501 } |
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502 break; |
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503 } |
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504 case 1: |
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505 { |
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506 if (((inst & 0x01800000) >> 23) == 2) // bits 24-23 |
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507 { |
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508 // cannot modify the PC |
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509 break; |
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510 } |
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511 else if (arm_rd(inst) == PC_REGISTER) |
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512 { |
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513 // destination register is the PC |
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514 TUint32 rn; |
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515 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); // bits 19-16 |
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516 if(err != KErrNone) |
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517 { |
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518 LOG_MSG2("Non-zero error code discarded: %d", err); |
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519 } |
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520 TUint32 shifter = ((arm_data_imm(inst) >> arm_data_rot(inst)) | (arm_data_imm(inst) << (32 - arm_data_rot(inst)))) & 0xffffffff; |
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521 |
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522 DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress); |
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523 } |
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524 break; |
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525 } |
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526 case 2: |
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527 { |
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528 // load/store immediate offset |
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529 if (arm_load(inst)) // bit 20 |
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530 { |
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531 // loading a register from memory |
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532 if (arm_rd(inst) == PC_REGISTER) |
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533 { |
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534 // loading the PC register |
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535 TUint32 base; |
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536 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base); |
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537 if(err != KErrNone) |
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538 { |
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539 LOG_MSG2("Non-zero error code discarded: %d", err); |
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540 } |
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541 |
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542 /* Note: At runtime the PC would be 8 further on |
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543 */ |
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544 if (arm_rn(inst) == PC_REGISTER) |
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545 { |
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546 base = aCurrentPC + 8; |
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547 } |
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548 |
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549 TUint32 offset = 0; |
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550 |
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551 if (arm_single_pre(inst)) |
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552 { |
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553 // Pre-indexing |
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554 offset = arm_single_imm(inst); |
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555 |
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556 if (arm_single_u(inst)) |
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557 { |
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558 base += offset; |
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559 } |
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560 else |
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561 { |
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562 base -= offset; |
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563 } |
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564 } |
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565 |
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566 TBuf8<4> destination; |
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567 err = iChannel->DoReadMemory(aThread, base, 4, destination); |
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568 |
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569 if (KErrNone == err) |
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570 { |
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571 breakAddress = *(TUint32 *)destination.Ptr(); |
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572 |
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573 if ((breakAddress & 0x00000001) == 1) |
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574 { |
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575 aChangingModes = ETrue; |
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576 } |
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577 breakAddress &= 0xFFFFFFFE; |
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578 } |
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579 else |
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580 { |
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581 LOG_MSG("Error reading memory in decoding step instruction"); |
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582 } |
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583 } |
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584 } |
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585 break; |
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586 } |
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587 case 3: |
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588 { |
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589 if (((inst & 0xF0000000) != 0xF0000000) && ((inst & 0x00000010) == 0)) |
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590 { |
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591 // load/store register offset |
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592 if (arm_load(inst)) // bit 20 |
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593 { |
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594 // loading a register from memory |
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595 if (arm_rd(inst) == PC_REGISTER) |
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596 { |
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597 // loading the PC register |
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598 TUint32 base = 0; |
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599 if(arm_rn(inst) == PC_REGISTER) |
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600 { |
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601 base = aCurrentPC + 8; |
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602 } |
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603 else |
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604 { |
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605 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base); |
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606 if(err != KErrNone) |
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607 { |
|
608 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
609 } |
|
610 } |
|
611 |
|
612 TUint32 offset = 0; |
|
613 |
|
614 if (arm_single_pre(inst)) |
|
615 { |
|
616 offset = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister); |
|
617 |
|
618 if (arm_single_u(inst)) |
|
619 { |
|
620 base += offset; |
|
621 } |
|
622 else |
|
623 { |
|
624 base -= offset; |
|
625 } |
|
626 } |
|
627 |
|
628 TBuf8<4> destination; |
|
629 err = iChannel->DoReadMemory(aThread, base, 4, destination); |
|
630 |
|
631 if (KErrNone == err) |
|
632 { |
|
633 breakAddress = *(TUint32 *)destination.Ptr(); |
|
634 |
|
635 if ((breakAddress & 0x00000001) == 1) |
|
636 { |
|
637 aChangingModes = ETrue; |
|
638 } |
|
639 breakAddress &= 0xFFFFFFFE; |
|
640 } |
|
641 else |
|
642 { |
|
643 LOG_MSG("Error reading memory in decoding step instruction"); |
|
644 } |
|
645 } |
|
646 } |
|
647 } |
|
648 break; |
|
649 } |
|
650 case 4: |
|
651 { |
|
652 if ((inst & 0xF0000000) != 0xF0000000) |
|
653 { |
|
654 // load/store multiple |
|
655 if (arm_load(inst)) // bit 20 |
|
656 { |
|
657 // loading a register from memory |
|
658 if (((inst & 0x00008000) >> 15)) |
|
659 { |
|
660 // loading the PC register |
|
661 TInt offset = 0; |
|
662 if (arm_block_u(inst)) |
|
663 { |
|
664 TUint32 reglist = arm_block_reglist(inst); |
|
665 offset = iChannel->Bitcount(reglist) * 4 - 4; |
|
666 if (arm_block_pre(inst)) |
|
667 offset += 4; |
|
668 } |
|
669 else if (arm_block_pre(inst)) |
|
670 { |
|
671 offset = -4; |
|
672 } |
|
673 |
|
674 TUint32 temp = 0; |
|
675 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), temp); |
|
676 if(err != KErrNone) |
|
677 { |
|
678 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
679 } |
|
680 |
|
681 temp += offset; |
|
682 |
|
683 TBuf8<4> destination; |
|
684 err = iChannel->DoReadMemory(aThread, temp, 4, destination); |
|
685 |
|
686 if (KErrNone == err) |
|
687 { |
|
688 breakAddress = *(TUint32 *)destination.Ptr(); |
|
689 if ((breakAddress & 0x00000001) == 1) |
|
690 { |
|
691 aChangingModes = ETrue; |
|
692 } |
|
693 breakAddress &= 0xFFFFFFFE; |
|
694 } |
|
695 else |
|
696 { |
|
697 LOG_MSG("Error reading memory in decoding step instruction"); |
|
698 } |
|
699 } |
|
700 } |
|
701 } |
|
702 break; |
|
703 } |
|
704 case 5: |
|
705 { |
|
706 if ((inst & 0xF0000000) == 0xF0000000) |
|
707 { |
|
708 // BLX |
|
709 { |
|
710 breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC); |
|
711 |
|
712 // Unconditionally change into Thumb mode |
|
713 aChangingModes = ETrue; |
|
714 |
|
715 breakAddress &= 0xFFFFFFFE; |
|
716 } |
|
717 } |
|
718 else |
|
719 { |
|
720 if ((inst & 0x01000000)) // bit 24 |
|
721 { |
|
722 // BL |
|
723 { |
|
724 breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC); |
|
725 } |
|
726 } |
|
727 else |
|
728 { |
|
729 // B |
|
730 breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC); |
|
731 } |
|
732 } |
|
733 break; |
|
734 } |
|
735 } |
|
736 } |
|
737 } |
|
738 break; |
|
739 |
|
740 case Debug::EThumbMode: |
|
741 { |
|
742 // Thumb Mode |
|
743 // |
|
744 // Notes: This now includes the extra code |
|
745 // required to decode V6T2 instructions |
|
746 |
|
747 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Thumb Instruction"); |
|
748 |
|
749 TUint16 inst; |
|
750 |
|
751 // Obtain the current instruction bit pattern |
|
752 TUint32 inst32; |
|
753 ReturnIfError(CurrentInstruction(aThread,inst32)); |
|
754 |
|
755 inst = static_cast<TUint16>(inst32 & 0xFFFF); |
|
756 |
|
757 LOG_MSG2("Current Thumb instruction: 0x%x", inst); |
|
758 |
|
759 // v6T2 instructions |
|
760 |
|
761 // Note: v6T2 decoding is only enabled for DEBUG builds or if using an |
|
762 // an ARM_V6T2 supporting build system. At the time of writing, no |
|
763 // ARM_V6T2 supporting build system exists, so the stepping code cannot |
|
764 // be said to be known to work. Hence it is not run for release builds |
|
765 |
|
766 TBool use_v6t2_decodings = EFalse; |
|
767 |
|
768 #if defined(DEBUG) || defined(__ARMV6T2__) |
|
769 use_v6t2_decodings = ETrue; |
|
770 |
|
771 #endif |
|
772 // coverity[dead_error_line] |
|
773 if (use_v6t2_decodings) |
|
774 { |
|
775 // 16-bit encodings |
|
776 |
|
777 // A6.2.5 Misc 16-bit instructions |
|
778 // DONE Compare and branch on zero (page A8-66) |
|
779 // If then hints |
|
780 |
|
781 // ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ |
|
782 // |
|
783 // Compare and branch on Nonzero and Compare and Branch on Zero. |
|
784 if ((inst & 0xF500) == 0xB100) |
|
785 { |
|
786 LOG_MSG("ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ"); |
|
787 |
|
788 // Decoding as per ARM ARM description |
|
789 TUint32 op = (inst & 0x0800) >> 11; |
|
790 TUint32 i = (inst & 0x0200) >> 9; |
|
791 TUint32 imm5 = (inst & 0x00F8) >> 3; |
|
792 TUint32 Rn = inst & 0x0007; |
|
793 |
|
794 TUint32 imm32 = (i << 6) | (imm5 << 1); |
|
795 |
|
796 // Obtain value for register Rn |
|
797 TUint32 RnVal = 0; |
|
798 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
799 |
|
800 if (op) |
|
801 { |
|
802 // nonzero |
|
803 if (RnVal != 0x0) |
|
804 { |
|
805 // Branch |
|
806 breakAddress = aCurrentPC + imm32; |
|
807 } |
|
808 } |
|
809 else |
|
810 { |
|
811 // zero |
|
812 if (RnVal == 0x0) |
|
813 { |
|
814 // Branch |
|
815 breakAddress = aCurrentPC + imm32; |
|
816 } |
|
817 } |
|
818 } |
|
819 |
|
820 // ARM ARM DDI0406A - section A8.6.50 IT |
|
821 // |
|
822 // If Then instruction |
|
823 if ((inst & 0xFF00) == 0xBF00) |
|
824 { |
|
825 LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT"); |
|
826 |
|
827 // Decoding as per ARM ARM description |
|
828 TUint32 firstcond = inst & 0x00F0 >> 4; |
|
829 TUint32 mask = inst & 0x000F; |
|
830 |
|
831 if (firstcond == 0xF) |
|
832 { |
|
833 // unpredictable |
|
834 LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable"); |
|
835 break; |
|
836 } |
|
837 |
|
838 if ((firstcond == 0xE) && (BitCount(mask) != 1)) |
|
839 { |
|
840 // unpredictable |
|
841 LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable"); |
|
842 break; |
|
843 } |
|
844 |
|
845 // should check if 'in-it-block' |
|
846 LOG_MSG("Cannot step IT instructions."); |
|
847 |
|
848 // all the conds are as per Table A8-1 (i.e. the usual 16 cases) |
|
849 // no idea how to decode the it block 'after-the-fact' |
|
850 // so probably need to treat instructions in the it block |
|
851 // as 'may' be executed. So breakpoints at both possible locations |
|
852 // depending on whether the instruction is executed or not. |
|
853 |
|
854 // also, how do we know if we have hit a breakpoint whilst 'in' an it block? |
|
855 // can we check the status registers to find out? |
|
856 // |
|
857 // see arm arm page 390. |
|
858 // |
|
859 // seems to depend on the itstate field. this also says what the condition code |
|
860 // actually is, and how many instructions are left in the itblock. |
|
861 // perhaps we can just totally ignore this state, and always do the two-instruction |
|
862 // breakpoint thing? Not if there is any possibility that the address target |
|
863 // would be invalid for the non-taken branch address... |
|
864 } |
|
865 |
|
866 |
|
867 // 32-bit encodings. |
|
868 // |
|
869 |
|
870 // Load word A6-23 |
|
871 // Data processing instructions a6-28 |
|
872 // |
|
873 |
|
874 // ARM ARM DDI0406A - section A8.6.26 |
|
875 if (inst32 & 0xFFF0FFFF == 0xE3C08F00) |
|
876 { |
|
877 LOG_MSG("ARM ARM DDI0406A - section A8.6.26 - BXJ is not supported"); |
|
878 |
|
879 // Decoding as per ARM ARM description |
|
880 // TUint32 Rm = inst32 & 0x000F0000; // not needed yet |
|
881 } |
|
882 |
|
883 // return from exception... SUBS PC,LR. page b6-25 |
|
884 // |
|
885 // ARM ARM DDi046A - section B6.1.13 - SUBS PC,LR |
|
886 // |
|
887 // Encoding T1 |
|
888 if (inst32 & 0xFFFFFF00 == 0xF3DE8F00) |
|
889 { |
|
890 LOG_MSG("ARM ARM DDI0406A - section B6.1.13 - SUBS PC,LR Encoding T1"); |
|
891 |
|
892 // Decoding as per ARM ARM description |
|
893 TUint32 imm8 = inst32 & 0x000000FF; |
|
894 TUint32 imm32 = imm8; |
|
895 |
|
896 // TUint32 register_form = EFalse; // not needed for this decoding |
|
897 // TUint32 opcode = 0x2; // SUB // not needed for this decoding |
|
898 TUint32 n = 14; |
|
899 |
|
900 // Obtain LR |
|
901 TUint32 lrVal; |
|
902 ReturnIfError(RegisterValue(aThread,n,lrVal)); |
|
903 |
|
904 TUint32 operand2 = imm32; // always for Encoding T1 |
|
905 |
|
906 TUint32 result = lrVal - operand2; |
|
907 |
|
908 breakAddress = result; |
|
909 } |
|
910 |
|
911 // ARM ARM DDI0406A - section A8.6.16 - B |
|
912 // |
|
913 // Branch Encoding T3 |
|
914 if (inst32 & 0xF800D000 == 0xF0008000) |
|
915 { |
|
916 LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B Encoding T3"); |
|
917 |
|
918 // Decoding as per ARM ARM description |
|
919 TUint32 S = inst32 & 0x04000000 >> 26; |
|
920 // TUint32 cond = inst32 & 0x03C00000 >> 22; // not needed for this decoding |
|
921 TUint32 imm6 = inst32 & 0x003F0000 >> 16; |
|
922 TUint32 J1 = inst32 & 0x00002000 >> 13; |
|
923 TUint32 J2 = inst32 & 0x00000800 >> 11; |
|
924 TUint32 imm11 = inst32 & 0x000007FF; |
|
925 |
|
926 TUint32 imm32 = S ? 0xFFFFFFFF : 0 ; |
|
927 imm32 = (imm32 << 1) | J2; |
|
928 imm32 = (imm32 << 1) | J1; |
|
929 imm32 = (imm32 << 6) | imm6; |
|
930 imm32 = (imm32 << 11) | imm11; |
|
931 imm32 = (imm32 << 1) | 0; |
|
932 |
|
933 breakAddress = aCurrentPC + imm32; |
|
934 } |
|
935 |
|
936 // ARM ARM DDI0406A - section A8.6.16 - B |
|
937 // |
|
938 // Branch Encoding T4 |
|
939 if (inst32 & 0xF800D000 == 0xF0009000) |
|
940 { |
|
941 LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B"); |
|
942 |
|
943 // Decoding as per ARM ARM description |
|
944 TUint32 S = inst32 & 0x04000000 >> 26; |
|
945 TUint32 imm10 = inst32 & 0x03FF0000 >> 16; |
|
946 TUint32 J1 = inst32 & 0x00002000 >> 12; |
|
947 TUint32 J2 = inst32 & 0x00000800 >> 11; |
|
948 TUint32 imm11 = inst32 & 0x000003FF; |
|
949 |
|
950 TUint32 I1 = !(J1 ^ S); |
|
951 TUint32 I2 = !(J2 ^ S); |
|
952 |
|
953 TUint32 imm32 = S ? 0xFFFFFFFF : 0; |
|
954 imm32 = (imm32 << 1) | S; |
|
955 imm32 = (imm32 << 1) | I1; |
|
956 imm32 = (imm32 << 1) | I2; |
|
957 imm32 = (imm32 << 10) | imm10; |
|
958 imm32 = (imm32 << 11) | imm11; |
|
959 imm32 = (imm32 << 1) | 0; |
|
960 |
|
961 breakAddress = aCurrentPC + imm32; |
|
962 } |
|
963 |
|
964 |
|
965 // ARM ARM DDI0406A - section A8.6.225 - TBB, TBH |
|
966 // |
|
967 // Table Branch Byte, Table Branch Halfword |
|
968 if (inst32 & 0xFFF0FFE0 == 0xE8D0F000) |
|
969 { |
|
970 LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1"); |
|
971 |
|
972 // Decoding as per ARM ARM description |
|
973 TUint32 Rn = inst32 & 0x000F0000 >> 16; |
|
974 TUint32 H = inst32 & 0x00000010 >> 4; |
|
975 TUint32 Rm = inst32 & 0x0000000F; |
|
976 |
|
977 // Unpredictable? |
|
978 if (Rm == 13 || Rm == 15) |
|
979 { |
|
980 LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1 - Unpredictable"); |
|
981 break; |
|
982 } |
|
983 |
|
984 TUint32 halfwords; |
|
985 TUint32 address; |
|
986 ReturnIfError(RegisterValue(aThread,Rn,address)); |
|
987 |
|
988 TUint32 offset; |
|
989 ReturnIfError(RegisterValue(aThread,Rm,offset)); |
|
990 |
|
991 if (H) |
|
992 { |
|
993 |
|
994 address += offset << 1; |
|
995 } |
|
996 else |
|
997 { |
|
998 address += offset; |
|
999 } |
|
1000 |
|
1001 ReturnIfError(ReadMem32(aThread,address,halfwords)); |
|
1002 |
|
1003 breakAddress = aCurrentPC + 2*halfwords; |
|
1004 break; |
|
1005 } |
|
1006 |
|
1007 // ARM ARM DDI0406A - section A8.6.55 - LDMDB, LDMEA |
|
1008 // |
|
1009 // LDMDB Encoding T1 |
|
1010 if (inst32 & 0xFFD02000 == 0xE9100000) |
|
1011 { |
|
1012 LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1"); |
|
1013 |
|
1014 // Decoding as per ARM ARM description |
|
1015 // TUint32 W = inst32 & 0x00200000 >> 21; // Not needed for this encoding |
|
1016 TUint32 Rn = inst32 & 0x000F0000 >> 16; |
|
1017 TUint32 P = inst32 & 0x00008000 >> 15; |
|
1018 TUint32 M = inst32 & 0x00004000 >> 14; |
|
1019 TUint32 registers = inst32 & 0x00001FFF; |
|
1020 |
|
1021 //TBool wback = (W == 1); // not needed for this encoding |
|
1022 |
|
1023 // Unpredictable? |
|
1024 if (Rn == 15 || BitCount(registers) < 2 || ((P == 1) && (M==1))) |
|
1025 { |
|
1026 LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1 - Unpredictable"); |
|
1027 break; |
|
1028 } |
|
1029 |
|
1030 TUint32 address; |
|
1031 ReturnIfError(RegisterValue(aThread,Rn,address)); |
|
1032 |
|
1033 address -= 4*BitCount(registers); |
|
1034 |
|
1035 for(TInt i=0; i<15; i++) |
|
1036 { |
|
1037 if (IsBitSet(registers,i)) |
|
1038 { |
|
1039 address +=4; |
|
1040 } |
|
1041 } |
|
1042 |
|
1043 if (IsBitSet(registers,15)) |
|
1044 { |
|
1045 TUint32 RnVal = 0; |
|
1046 ReturnIfError(ReadMem32(aThread,address,RnVal)); |
|
1047 |
|
1048 breakAddress = RnVal; |
|
1049 } |
|
1050 break; |
|
1051 } |
|
1052 |
|
1053 // ARM ARM DDI0406A - section A8.6.121 POP |
|
1054 // |
|
1055 // POP.W Encoding T2 |
|
1056 if (inst32 & 0xFFFF2000 == 0xE8BD0000) |
|
1057 { |
|
1058 LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2"); |
|
1059 |
|
1060 // Decoding as per ARM ARM description |
|
1061 TUint32 registers = inst32 & 0x00001FFF; |
|
1062 TUint32 P = inst32 & 0x00008000; |
|
1063 TUint32 M = inst32 & 0x00004000; |
|
1064 |
|
1065 // Unpredictable? |
|
1066 if ( (BitCount(registers)<2) || ((P == 1)&&(M == 1)) ) |
|
1067 { |
|
1068 LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2 - Unpredictable"); |
|
1069 break; |
|
1070 } |
|
1071 |
|
1072 TUint32 address; |
|
1073 ReturnIfError(RegisterValue(aThread,13,address)); |
|
1074 |
|
1075 for(TInt i=0; i< 15; i++) |
|
1076 { |
|
1077 if (IsBitSet(registers,i)) |
|
1078 { |
|
1079 address += 4; |
|
1080 } |
|
1081 } |
|
1082 |
|
1083 // Is the PC written? |
|
1084 if (IsBitSet(registers,15)) |
|
1085 { |
|
1086 // Yes |
|
1087 ReturnIfError(ReadMem32(aThread,address,breakAddress)); |
|
1088 } |
|
1089 } |
|
1090 |
|
1091 // POP Encoding T3 |
|
1092 if (inst32 & 0xFFFF0FFFF == 0xF85D0B04) |
|
1093 { |
|
1094 LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3"); |
|
1095 |
|
1096 // Decoding as per ARM ARM description |
|
1097 TUint32 Rt = inst32 & 0x0000F000 >> 12; |
|
1098 TUint32 registers = 1 << Rt; |
|
1099 |
|
1100 // Unpredictable? |
|
1101 if (Rt == 13 || Rt == 15) |
|
1102 { |
|
1103 LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3 - Unpredictable"); |
|
1104 break; |
|
1105 } |
|
1106 |
|
1107 TUint32 address; |
|
1108 ReturnIfError(RegisterValue(aThread,13,address)); |
|
1109 |
|
1110 for(TInt i=0; i< 15; i++) |
|
1111 { |
|
1112 if (IsBitSet(registers,i)) |
|
1113 { |
|
1114 address += 4; |
|
1115 } |
|
1116 } |
|
1117 |
|
1118 // Is the PC written? |
|
1119 if (IsBitSet(registers,15)) |
|
1120 { |
|
1121 // Yes |
|
1122 ReturnIfError(ReadMem32(aThread,address,breakAddress)); |
|
1123 } |
|
1124 |
|
1125 break; |
|
1126 } |
|
1127 |
|
1128 // ARM ARM DDI0406A - section A8.6.53 LDM |
|
1129 // |
|
1130 // Load Multiple Encoding T2 |
|
1131 if ((inst32 & 0xFFD02000) == 0xE8900000) |
|
1132 { |
|
1133 LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2"); |
|
1134 |
|
1135 // Decoding as per ARM ARM description |
|
1136 TUint32 W = inst32 & 0x0020000 >> 21; |
|
1137 TUint32 Rn = inst32 & 0x000F0000 >> 16; |
|
1138 TUint32 P = inst32 & 0x00008000 >> 15; |
|
1139 TUint32 M = inst32 & 0x00004000 >> 14; |
|
1140 TUint32 registers = inst32 & 0x0000FFFF; |
|
1141 TUint32 register_list = inst32 & 0x00001FFF; |
|
1142 |
|
1143 // POP? |
|
1144 if ( (W == 1) && (Rn == 13) ) |
|
1145 { |
|
1146 // POP instruction |
|
1147 LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - POP"); |
|
1148 } |
|
1149 |
|
1150 // Unpredictable? |
|
1151 if (Rn == 15 || BitCount(register_list) < 2 || ((P == 1) && (M == 1)) ) |
|
1152 { |
|
1153 LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - Unpredictable"); |
|
1154 break; |
|
1155 } |
|
1156 |
|
1157 TUint32 RnVal; |
|
1158 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
1159 |
|
1160 TUint32 address = RnVal; |
|
1161 |
|
1162 // Calculate offset of address |
|
1163 for(TInt i = 0; i < 15; i++) |
|
1164 { |
|
1165 if (IsBitSet(registers,i)) |
|
1166 { |
|
1167 address += 4; |
|
1168 } |
|
1169 } |
|
1170 |
|
1171 // Does it load the PC? |
|
1172 if (IsBitSet(registers,15)) |
|
1173 { |
|
1174 // Obtain the value loaded into the PC |
|
1175 ReturnIfError(ReadMem32(aThread,address,breakAddress)); |
|
1176 } |
|
1177 break; |
|
1178 |
|
1179 } |
|
1180 |
|
1181 // ARM ARM DDI0406A - section B6.1.8 RFE |
|
1182 // |
|
1183 // Return From Exception Encoding T1 RFEDB |
|
1184 if ((inst32 & 0xFFD0FFFF) == 0xE810C000) |
|
1185 { |
|
1186 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1"); |
|
1187 |
|
1188 // Decoding as per ARM ARM description |
|
1189 // TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding |
|
1190 TUint32 Rn = (inst32 & 0x000F0000) >> 16; |
|
1191 |
|
1192 // TBool wback = (W == 1); // not needed for this encoding |
|
1193 TBool increment = EFalse; |
|
1194 TBool wordhigher = EFalse; |
|
1195 |
|
1196 // Do calculation |
|
1197 if (Rn == 15) |
|
1198 { |
|
1199 // Unpredictable |
|
1200 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1 - Unpredictable"); |
|
1201 break; |
|
1202 } |
|
1203 |
|
1204 TUint32 RnVal = 0; |
|
1205 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
1206 |
|
1207 TUint32 address = 0; |
|
1208 ReturnIfError(ReadMem32(aThread,RnVal,address)); |
|
1209 |
|
1210 if (increment) |
|
1211 { |
|
1212 address -= 8; |
|
1213 } |
|
1214 |
|
1215 if (wordhigher) |
|
1216 { |
|
1217 address += 4; |
|
1218 } |
|
1219 |
|
1220 breakAddress = address; |
|
1221 break; |
|
1222 } |
|
1223 |
|
1224 // Return From Exception Encoding T2 RFEIA |
|
1225 if ((inst32 & 0xFFD0FFFF) == 0xE990C000) |
|
1226 { |
|
1227 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2"); |
|
1228 |
|
1229 // Decoding as per ARM ARM description |
|
1230 // TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding |
|
1231 TUint32 Rn = (inst32 & 0x000F0000) >> 16; |
|
1232 |
|
1233 // TBool wback = (W == 1); // not needed for this encoding |
|
1234 TBool increment = ETrue; |
|
1235 TBool wordhigher = EFalse; |
|
1236 |
|
1237 // Do calculation |
|
1238 if (Rn == 15) |
|
1239 { |
|
1240 // Unpredictable |
|
1241 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2 - Unpredictable"); |
|
1242 break; |
|
1243 } |
|
1244 |
|
1245 TUint32 RnVal = 0; |
|
1246 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
1247 |
|
1248 TUint32 address = 0; |
|
1249 ReturnIfError(ReadMem32(aThread,RnVal,address)); |
|
1250 |
|
1251 if (increment) |
|
1252 { |
|
1253 address -= 8; |
|
1254 } |
|
1255 |
|
1256 if (wordhigher) |
|
1257 { |
|
1258 address += 4; |
|
1259 } |
|
1260 |
|
1261 breakAddress = RnVal; |
|
1262 break; |
|
1263 } |
|
1264 |
|
1265 // Return From Exception Encoding A1 RFE<amode> |
|
1266 if ((inst32 & 0xFE50FFFF) == 0xF8100A00) |
|
1267 { |
|
1268 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1"); |
|
1269 |
|
1270 // Decoding as per ARM ARM description |
|
1271 TUint32 P = (inst32 & 0x01000000) >> 24; |
|
1272 TUint32 U = (inst32 & 0x00800000) >> 23; |
|
1273 // TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding |
|
1274 TUint32 Rn = (inst32 & 0x000F0000) >> 16; |
|
1275 |
|
1276 // TBool wback = (W == 1); // not needed for this encoding |
|
1277 TBool increment = (U == 1); |
|
1278 TBool wordhigher = (P == U); |
|
1279 |
|
1280 // Do calculation |
|
1281 if (Rn == 15) |
|
1282 { |
|
1283 // Unpredictable |
|
1284 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1 - Unpredictable"); |
|
1285 break; |
|
1286 } |
|
1287 |
|
1288 TUint32 RnVal = 0; |
|
1289 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
1290 |
|
1291 TUint32 address = 0; |
|
1292 ReturnIfError(ReadMem32(aThread,RnVal,address)); |
|
1293 |
|
1294 if (increment) |
|
1295 { |
|
1296 address -= 8; |
|
1297 } |
|
1298 |
|
1299 if (wordhigher) |
|
1300 { |
|
1301 address += 4; |
|
1302 } |
|
1303 |
|
1304 breakAddress = address; |
|
1305 break; |
|
1306 } |
|
1307 } |
|
1308 |
|
1309 // v4T/v5T/v6T instructions |
|
1310 switch(thumb_opcode(inst)) |
|
1311 { |
|
1312 case 0x08: |
|
1313 { |
|
1314 // Data-processing. See ARM ARM DDI0406A, section A6-8, A6.2.2. |
|
1315 |
|
1316 if ((thumb_inst_7_15(inst) == 0x08F)) |
|
1317 { |
|
1318 // BLX(2) |
|
1319 err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress); |
|
1320 if(err != KErrNone) |
|
1321 { |
|
1322 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1323 } |
|
1324 |
|
1325 if ((breakAddress & 0x00000001) == 0) |
|
1326 { |
|
1327 aChangingModes = ETrue; |
|
1328 } |
|
1329 |
|
1330 breakAddress &= 0xFFFFFFFE; |
|
1331 |
|
1332 // Report how we decoded this instruction |
|
1333 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX (2)"); |
|
1334 } |
|
1335 else if (thumb_inst_7_15(inst) == 0x08E) |
|
1336 { |
|
1337 // BX |
|
1338 err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress); |
|
1339 if(err != KErrNone) |
|
1340 { |
|
1341 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1342 } |
|
1343 |
|
1344 if ((breakAddress & 0x00000001) == 0) |
|
1345 { |
|
1346 aChangingModes = ETrue; |
|
1347 } |
|
1348 |
|
1349 breakAddress &= 0xFFFFFFFE; |
|
1350 |
|
1351 // Report how we decoded this instruction |
|
1352 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BX"); |
|
1353 } |
|
1354 else if ((thumb_inst_8_15(inst) == 0x46) && ((inst & 0x87) == 0x87)) |
|
1355 { |
|
1356 // MOV with PC as the destination |
|
1357 err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress); |
|
1358 if(err != KErrNone) |
|
1359 { |
|
1360 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1361 } |
|
1362 |
|
1363 // Report how we decoded this instruction |
|
1364 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as MOV with PC as the destination"); |
|
1365 } |
|
1366 else if ((thumb_inst_8_15(inst) == 0x44) && ((inst & 0x87) == 0x87)) |
|
1367 { |
|
1368 // ADD with PC as the destination |
|
1369 err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress); |
|
1370 if(err != KErrNone) |
|
1371 { |
|
1372 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1373 } |
|
1374 breakAddress += aCurrentPC + 4; // +4 because we need to use the PC+4 according to ARM ARM DDI0406A, section A6.1.2. |
|
1375 |
|
1376 // Report how we decoded this instruction |
|
1377 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as ADD with PC as the destination"); |
|
1378 } |
|
1379 break; |
|
1380 } |
|
1381 case 0x13: |
|
1382 { |
|
1383 // Load/Store single data item. See ARM ARM DDI0406A, section A6-10 |
|
1384 |
|
1385 //This instruction doesn't modify the PC. |
|
1386 |
|
1387 //if (thumb_inst_8_15(inst) == 0x9F) |
|
1388 //{ |
|
1389 // LDR(4) with the PC as the destination |
|
1390 // breakAddress = ReadRegister(aThread, SP_REGISTER) + (4 * (inst & 0x00FF)); |
|
1391 //} |
|
1392 |
|
1393 // Report how we decoded this instruction |
|
1394 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as This instruction doesn't modify the PC."); |
|
1395 break; |
|
1396 } |
|
1397 case 0x17: |
|
1398 { |
|
1399 // Misc 16-bit instruction. See ARM ARM DDI0406A, section A6-11 |
|
1400 |
|
1401 if (thumb_inst_8_15(inst) == 0xBD) |
|
1402 { |
|
1403 // POP with the PC in the list |
|
1404 TUint32 regList = (inst & 0x00FF); |
|
1405 TInt offset = 0; |
|
1406 err = iChannel->ReadKernelRegisterValue(aThread, SP_REGISTER, (T4ByteRegisterValue&)offset); |
|
1407 if(err != KErrNone) |
|
1408 { |
|
1409 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1410 } |
|
1411 offset += (iChannel->Bitcount(regList) * 4); |
|
1412 |
|
1413 TBuf8<4> destination; |
|
1414 err = iChannel->DoReadMemory(aThread, offset, 4, destination); |
|
1415 |
|
1416 if (KErrNone == err) |
|
1417 { |
|
1418 breakAddress = *(TUint32 *)destination.Ptr(); |
|
1419 |
|
1420 if ((breakAddress & 0x00000001) == 0) |
|
1421 { |
|
1422 aChangingModes = ETrue; |
|
1423 } |
|
1424 |
|
1425 breakAddress &= 0xFFFFFFFE; |
|
1426 } |
|
1427 else |
|
1428 { |
|
1429 LOG_MSG("Error reading memory in decoding step instruction"); |
|
1430 } |
|
1431 |
|
1432 // Report how we decoded this instruction |
|
1433 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as POP with the PC in the list"); |
|
1434 } |
|
1435 break; |
|
1436 } |
|
1437 case 0x1A: |
|
1438 case 0x1B: |
|
1439 { |
|
1440 // Conditional branch, and supervisor call. See ARM ARM DDI0406A, section A6-13 |
|
1441 |
|
1442 if (thumb_inst_8_15(inst) < 0xDE) |
|
1443 { |
|
1444 // B(1) conditional branch |
|
1445 if (IsExecuted(((inst & 0x0F00) >> 8), aStatusRegister)) |
|
1446 { |
|
1447 TUint32 offset = ((inst & 0x000000FF) << 1); |
|
1448 if (offset & 0x00000100) |
|
1449 { |
|
1450 offset |= 0xFFFFFF00; |
|
1451 } |
|
1452 |
|
1453 breakAddress = aCurrentPC + 4 + offset; |
|
1454 |
|
1455 // Report how we decoded this instruction |
|
1456 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(1) conditional branch"); |
|
1457 } |
|
1458 } |
|
1459 break; |
|
1460 } |
|
1461 case 0x1C: |
|
1462 { |
|
1463 // Unconditional branch, See ARM ARM DDI0406A, section A8-44. |
|
1464 |
|
1465 // B(2) unconditional branch |
|
1466 TUint32 offset = (inst & 0x000007FF) << 1; |
|
1467 if (offset & 0x00000800) |
|
1468 { |
|
1469 offset |= 0xFFFFF800; |
|
1470 } |
|
1471 |
|
1472 breakAddress = aCurrentPC + 4 + offset; |
|
1473 |
|
1474 // Report how we decoded this instruction |
|
1475 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(2) unconditional branch"); |
|
1476 |
|
1477 break; |
|
1478 } |
|
1479 case 0x1D: |
|
1480 { |
|
1481 if (!(inst & 0x0001)) |
|
1482 { |
|
1483 // BLX(1) |
|
1484 err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress); |
|
1485 if(err != KErrNone) |
|
1486 { |
|
1487 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1488 } |
|
1489 breakAddress += ((inst & 0x07FF) << 1); |
|
1490 if ((breakAddress & 0x00000001) == 0) |
|
1491 { |
|
1492 aChangingModes = ETrue; |
|
1493 } |
|
1494 |
|
1495 breakAddress &= 0xFFFFFFFC; |
|
1496 |
|
1497 // Report how we decoded this instruction |
|
1498 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX(1)"); |
|
1499 |
|
1500 } |
|
1501 break; |
|
1502 } |
|
1503 case 0x1E: |
|
1504 { |
|
1505 // Check for ARMv7 CPU |
|
1506 if(cpuid == 0xC0) |
|
1507 { |
|
1508 // BL/BLX 32-bit instruction |
|
1509 aNewRangeEnd += 4; |
|
1510 |
|
1511 breakAddress = (TUint32)thumb_instr_b_dest(inst32, aCurrentPC); |
|
1512 |
|
1513 if((inst32 >> 27) == 0x1D) |
|
1514 { |
|
1515 // BLX(1) |
|
1516 if ((breakAddress & 0x00000001) == 0) |
|
1517 { |
|
1518 aChangingModes = ETrue; |
|
1519 } |
|
1520 |
|
1521 breakAddress &= 0xFFFFFFFC; |
|
1522 |
|
1523 // Report how we decoded this instruction |
|
1524 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as 32-bit BLX(1)"); |
|
1525 } |
|
1526 else |
|
1527 { |
|
1528 // Report how we decoded this instruction |
|
1529 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: 32-bit BL instruction"); |
|
1530 } |
|
1531 LOG_MSG2(" 32-bit BL/BLX instruction: breakAddress = 0x%X", breakAddress); |
|
1532 } |
|
1533 else |
|
1534 { |
|
1535 // BL/BLX prefix - destination is encoded in this and the next instruction |
|
1536 aNewRangeEnd += 2; |
|
1537 |
|
1538 // Report how we decoded this instruction |
|
1539 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: BL/BLX prefix - destination is encoded in this and the next instruction"); |
|
1540 } |
|
1541 |
|
1542 |
|
1543 break; |
|
1544 } |
|
1545 case 0x1F: |
|
1546 { |
|
1547 { |
|
1548 // BL |
|
1549 err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress); |
|
1550 if(err != KErrNone) |
|
1551 { |
|
1552 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1553 } |
|
1554 breakAddress += ((inst & 0x07FF) << 1); |
|
1555 |
|
1556 // Report how we decoded this instruction |
|
1557 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BL"); |
|
1558 } |
|
1559 break; |
|
1560 } |
|
1561 default: |
|
1562 { |
|
1563 // Don't know any better at this point! |
|
1564 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes:- default to next instruction"); |
|
1565 } |
|
1566 break; |
|
1567 } |
|
1568 } |
|
1569 break; |
|
1570 |
|
1571 case Debug::EThumb2EEMode: |
|
1572 { |
|
1573 // Not yet supported |
|
1574 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Debug::EThumb2Mode is not supported"); |
|
1575 |
|
1576 } |
|
1577 break; |
|
1578 |
|
1579 default: |
|
1580 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Cannot determine CPU mode architecture"); |
|
1581 } |
|
1582 |
|
1583 LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes : return 0x%08x",breakAddress); |
|
1584 return breakAddress; |
|
1585 } |
|
1586 |
|
1587 // Obtain a 32-bit memory value with minimum fuss |
|
1588 TInt DRMDStepping::ReadMem32(DThread* aThread, const TUint32 aAddress, TUint32& aValue) |
|
1589 { |
|
1590 TBuf8<4> valBuf; |
|
1591 TInt err = iChannel->DoReadMemory(aThread, aAddress, 4, valBuf); |
|
1592 if (err != KErrNone) |
|
1593 { |
|
1594 LOG_MSG2("DRMDStepping::ReadMem32 failed to read memory at 0x%08x", aAddress); |
|
1595 return err; |
|
1596 } |
|
1597 |
|
1598 aValue = *(TUint32 *)valBuf.Ptr(); |
|
1599 |
|
1600 return KErrNone; |
|
1601 } |
|
1602 |
|
1603 // Obtain a 16-bit memory value with minimum fuss |
|
1604 TInt DRMDStepping::ReadMem16(DThread* aThread, const TUint32 aAddress, TUint16& aValue) |
|
1605 { |
|
1606 TBuf8<2> valBuf; |
|
1607 TInt err = iChannel->DoReadMemory(aThread, aAddress, 2, valBuf); |
|
1608 if (err != KErrNone) |
|
1609 { |
|
1610 LOG_MSG2("DRMDStepping::ReadMem16 failed to read memory at 0x%08x", aAddress); |
|
1611 return err; |
|
1612 } |
|
1613 |
|
1614 aValue = *(TUint16 *)valBuf.Ptr(); |
|
1615 |
|
1616 return KErrNone; |
|
1617 } |
|
1618 |
|
1619 // Obtain a 16-bit memory value with minimum fuss |
|
1620 TInt DRMDStepping::ReadMem8(DThread* aThread, const TUint32 aAddress, TUint8& aValue) |
|
1621 { |
|
1622 TBuf8<1> valBuf; |
|
1623 TInt err = iChannel->DoReadMemory(aThread, aAddress, 1, valBuf); |
|
1624 if (err != KErrNone) |
|
1625 { |
|
1626 LOG_MSG2("DRMDStepping::ReadMem8 failed to read memory at 0x%08x", aAddress); |
|
1627 return err; |
|
1628 } |
|
1629 |
|
1630 aValue = *(TUint8 *)valBuf.Ptr(); |
|
1631 |
|
1632 return KErrNone; |
|
1633 } |
|
1634 |
|
1635 // Obtain a core register value with minimum fuss |
|
1636 TInt DRMDStepping::RegisterValue(DThread *aThread, const TUint32 aKernelRegisterId, TUint32 &aValue) |
|
1637 { |
|
1638 TInt err = iChannel->ReadKernelRegisterValue(aThread, aKernelRegisterId, aValue); |
|
1639 if(err != KErrNone) |
|
1640 { |
|
1641 LOG_MSG3("DRMDStepping::RegisterValue failed to read register %d err = %d", aKernelRegisterId, err); |
|
1642 } |
|
1643 return err; |
|
1644 } |
|
1645 |
|
1646 |
|
1647 // Encodings from ARM ARM DDI0406A, section 9.2.1 |
|
1648 enum TThumb2EEOpcode |
|
1649 { |
|
1650 EThumb2HDP, // Handler Branch with Parameter |
|
1651 EThumb2UNDEF, // UNDEFINED |
|
1652 EThumb2HB, // Handler Branch, Handler Branch with Link |
|
1653 EThumb2HBLP, // Handle Branch with Link and Parameter |
|
1654 EThumb2LDRF, // Load Register from a frame |
|
1655 EThumb2CHKA, // Check Array |
|
1656 EThumb2LDRL, // Load Register from a literal pool |
|
1657 EThumb2LDRA, // Load Register (array operations) |
|
1658 EThumb2STR // Store Register to a frame |
|
1659 }; |
|
1660 |
|
1661 // |
|
1662 // DRMDStepping::ShiftedRegValue |
|
1663 // |
|
1664 TUint32 DRMDStepping::ShiftedRegValue(DThread *aThread, TUint32 aInstruction, TUint32 aCurrentPC, TUint32 aStatusRegister) |
|
1665 { |
|
1666 LOG_MSG("DRM_DebugChannel::ShiftedRegValue()"); |
|
1667 |
|
1668 TUint32 shift = 0; |
|
1669 if (aInstruction & 0x10) // bit 4 |
|
1670 { |
|
1671 shift = (arm_rs(aInstruction) == PC_REGISTER ? aCurrentPC + 8 : aStatusRegister) & 0xFF; |
|
1672 } |
|
1673 else |
|
1674 { |
|
1675 shift = arm_data_c(aInstruction); |
|
1676 } |
|
1677 |
|
1678 TInt rm = arm_rm(aInstruction); |
|
1679 |
|
1680 TUint32 res = 0; |
|
1681 if(rm == PC_REGISTER) |
|
1682 { |
|
1683 res = aCurrentPC + ((aInstruction & 0x10) ? 12 : 8); |
|
1684 } |
|
1685 else |
|
1686 { |
|
1687 TInt err = iChannel->ReadKernelRegisterValue(aThread, rm, res); |
|
1688 if(err != KErrNone) |
|
1689 { |
|
1690 LOG_MSG2("DRMDStepping::ShiftedRegValue - Non-zero error code discarded: %d", err); |
|
1691 } |
|
1692 } |
|
1693 |
|
1694 switch(arm_data_shift(aInstruction)) |
|
1695 { |
|
1696 case 0: // LSL |
|
1697 { |
|
1698 res = shift >= 32 ? 0 : res << shift; |
|
1699 break; |
|
1700 } |
|
1701 case 1: // LSR |
|
1702 { |
|
1703 res = shift >= 32 ? 0 : res >> shift; |
|
1704 break; |
|
1705 } |
|
1706 case 2: // ASR |
|
1707 { |
|
1708 if (shift >= 32) |
|
1709 shift = 31; |
|
1710 res = ((res & 0x80000000L) ? ~((~res) >> shift) : res >> shift); |
|
1711 break; |
|
1712 } |
|
1713 case 3: // ROR/RRX |
|
1714 { |
|
1715 shift &= 31; |
|
1716 if (shift == 0) |
|
1717 { |
|
1718 res = (res >> 1) | ((aStatusRegister & arm_carry_bit()) ? 0x80000000L : 0); |
|
1719 } |
|
1720 else |
|
1721 { |
|
1722 res = (res >> shift) | (res << (32 - shift)); |
|
1723 } |
|
1724 break; |
|
1725 } |
|
1726 } |
|
1727 |
|
1728 return res & 0xFFFFFFFF; |
|
1729 } |
|
1730 |
|
1731 // |
|
1732 // DRMDStepping::CurrentPC |
|
1733 // |
|
1734 // |
|
1735 // |
|
1736 TInt DRMDStepping::CurrentPC(DThread* aThread, TUint32& aPC) |
|
1737 { |
|
1738 LOG_MSG("DRMDStepping::CurrentPC"); |
|
1739 |
|
1740 TInt err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, aPC); |
|
1741 if(err != KErrNone) |
|
1742 { |
|
1743 // We don't know the current PC for this thread! |
|
1744 LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current PC"); |
|
1745 |
|
1746 return KErrGeneral; |
|
1747 } |
|
1748 |
|
1749 LOG_MSG2("DRMDStepping::CurrentPC 0x%08x", aPC); |
|
1750 |
|
1751 return KErrNone; |
|
1752 } |
|
1753 |
|
1754 // |
|
1755 // DRMDStepping::CurrentCPSR |
|
1756 // |
|
1757 // |
|
1758 // |
|
1759 TInt DRMDStepping::CurrentCPSR(DThread* aThread, TUint32& aCPSR) |
|
1760 { |
|
1761 LOG_MSG("DRMDStepping::CurrentCPSR"); |
|
1762 |
|
1763 TInt err = iChannel->ReadKernelRegisterValue(aThread, STATUS_REGISTER, aCPSR); |
|
1764 if(err != KErrNone) |
|
1765 { |
|
1766 // We don't know the current PC for this thread! |
|
1767 LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current CPSR"); |
|
1768 |
|
1769 return KErrGeneral; |
|
1770 } |
|
1771 |
|
1772 LOG_MSG2("DRMDStepping::CurrentCPSR 0x%08x", aCPSR); |
|
1773 |
|
1774 return KErrNone; |
|
1775 } |
|
1776 |
|
1777 // |
|
1778 // DRMDStepping::ModifyBreaksForStep |
|
1779 // |
|
1780 // Set a temporary breakpoint at the next instruction to be executed after the one at the current PC |
|
1781 // Disable the breakpoint at the current PC if one exists |
|
1782 // |
|
1783 TInt DRMDStepping::ModifyBreaksForStep(DThread *aThread, TUint32 aRangeStart, TUint32 aRangeEnd, /*TBool aStepInto,*/ TBool aResumeOnceOutOfRange, TBool aCheckForStubs, const TUint32 aNumSteps) |
|
1784 { |
|
1785 LOG_MSG2("DRMDStepping::ModifyBreaksForStep() Numsteps 0x%d",aNumSteps); |
|
1786 |
|
1787 // Validate arguments |
|
1788 if (!aThread) |
|
1789 { |
|
1790 LOG_MSG("DRMDStepping::ModifyBreaksForStep() - No aThread specified to step"); |
|
1791 return KErrArgument; |
|
1792 } |
|
1793 |
|
1794 // Current PC |
|
1795 TUint32 currentPC; |
|
1796 |
|
1797 ReturnIfError(CurrentPC(aThread,currentPC)); |
|
1798 LOG_MSG2("Current PC: 0x%x", currentPC); |
|
1799 |
|
1800 // disable breakpoint at the current PC if necessary |
|
1801 ReturnIfError(iChannel->iBreakManager->DisableBreakAtAddress(currentPC)); |
|
1802 |
|
1803 // Current CPSR |
|
1804 TUint32 statusRegister; |
|
1805 |
|
1806 ReturnIfError(CurrentCPSR(aThread,statusRegister)); |
|
1807 LOG_MSG2("Current CPSR: %x", statusRegister); |
|
1808 |
|
1809 TBool thumbMode = (statusRegister & ECpuThumb); |
|
1810 if (thumbMode) |
|
1811 LOG_MSG("Thumb Mode"); |
|
1812 |
|
1813 TInt instSize = thumbMode ? 2 : 4; |
|
1814 |
|
1815 TBool changingModes = EFalse; |
|
1816 |
|
1817 TUint32 breakAddress = 0; |
|
1818 |
|
1819 TUint32 newRangeEnd = aRangeEnd; |
|
1820 |
|
1821 breakAddress = PCAfterInstructionExecutes(aThread, currentPC, statusRegister, instSize, /* aStepInto, */ newRangeEnd, changingModes); |
|
1822 |
|
1823 /* |
|
1824 If there is already a user breakpoint at this address, we do not need to set a temp breakpoint. The program |
|
1825 should simply stop at that address. |
|
1826 */ |
|
1827 TBreakEntry* breakEntry = NULL; |
|
1828 do |
|
1829 { |
|
1830 breakEntry = iChannel->iBreakManager->GetNextBreak(breakEntry); |
|
1831 if(breakEntry && !iChannel->iBreakManager->IsTemporaryBreak(*breakEntry)) |
|
1832 { |
|
1833 if ((breakEntry->iAddress == breakAddress) && ((breakEntry->iThreadSpecific && breakEntry->iId == aThread->iId) || (!breakEntry->iThreadSpecific && breakEntry->iId == aThread->iOwningProcess->iId))) |
|
1834 { |
|
1835 LOG_MSG("DRMDStepping::ModifyBreaksForStep - Breakpoint already exists at the step target address\n"); |
|
1836 |
|
1837 // note also that if this is the case, we will not keep stepping if we hit a real breakpoint, so may as well set |
|
1838 // the step count = 0. |
|
1839 breakEntry->iNumSteps = 0; |
|
1840 |
|
1841 return KErrNone; |
|
1842 } |
|
1843 } |
|
1844 } while(breakEntry); |
|
1845 |
|
1846 breakEntry = NULL; |
|
1847 do |
|
1848 { |
|
1849 breakEntry = iChannel->iBreakManager->GetNextBreak(breakEntry); |
|
1850 if(breakEntry && iChannel->iBreakManager->IsTemporaryBreak(*breakEntry)) |
|
1851 { |
|
1852 if (breakEntry->iAddress == 0) |
|
1853 { |
|
1854 breakEntry->iId = aThread->iId; |
|
1855 breakEntry->iAddress = breakAddress; |
|
1856 breakEntry->iThreadSpecific = ETrue; |
|
1857 |
|
1858 TBool realThumbMode = (thumbMode && !changingModes) || (!thumbMode && changingModes); |
|
1859 |
|
1860 // Need to set the correct type of breakpoint for the mode we are in |
|
1861 // and the the one we are changing into |
|
1862 if(realThumbMode) |
|
1863 { |
|
1864 // We are remaining in Thumb mode |
|
1865 breakEntry->iMode = EThumbMode; |
|
1866 } |
|
1867 else |
|
1868 { |
|
1869 // We are switching to ARM mode |
|
1870 breakEntry->iMode = EArmMode; |
|
1871 } |
|
1872 |
|
1873 breakEntry->iResumeOnceOutOfRange = aResumeOnceOutOfRange; |
|
1874 breakEntry->iSteppingInto = ETrue /* aStepInto */; |
|
1875 breakEntry->iRangeStart = 0; // no longer used |
|
1876 breakEntry->iRangeEnd = 0; // no longer used |
|
1877 |
|
1878 LOG_MSG2("Adding temp breakpoint with id: %d", breakEntry->iBreakId); |
|
1879 LOG_MSG2("Adding temp breakpoint with thread id: %d", aThread->iId); |
|
1880 |
|
1881 // Record how many more steps to go after we hit this one |
|
1882 breakEntry->iNumSteps = aNumSteps; |
|
1883 |
|
1884 LOG_MSG3("Setting temp breakpoint id %d with %d steps to go\n", breakEntry->iBreakId, aNumSteps); |
|
1885 |
|
1886 return iChannel->iBreakManager->DoEnableBreak(*breakEntry, ETrue); |
|
1887 } |
|
1888 } |
|
1889 } while(breakEntry); |
|
1890 LOG_MSG("ModifyBreaksForStep : Failed to set suitable breakpoint for stepping"); |
|
1891 return KErrNoMemory; // should never get here |
|
1892 } |
|
1893 |
|
1894 // End of file - d-rmd-stepping.cpp |