// Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// This file contains stepping code refactored from rm_debug_kerneldriver.cpp/rm_debug_kerneldriver.h

//

#include <e32def.h>

#include <e32def_private.h>

#include <e32cmn.h>

#include <e32cmn_private.h>

#include <kernel/kernel.h> 

#include <kernel/kern_priv.h>

#include <nk_trace.h>

#include <arm.h>

#include <rm_debug_api.h>

#include "d_rmd_stepping.h"

#include "d_rmd_breakpoints.h"

#include "rm_debug_kerneldriver.h"	// needed to access DRM_DebugChannel

#include "rm_debug_driver.h"

#include "debug_logging.h"

using namespace Debug;

//

// DRMDStepping::DRMDStepping

//

DRMDStepping::DRMDStepping(DRM_DebugChannel* aChannel)

:

	iChannel(aChannel)

	{

	// to do

	}

//

// DRMDStepping::~DRM_DebugChannel

//

DRMDStepping::~DRMDStepping()

{

	// to do

}

//

// DRMDStepping::IsExecuted

//

TBool DRMDStepping::IsExecuted(TUint8 aCondition ,TUint32 aStatusRegister)

{

	LOG_MSG("DRMDStepping::IsExecuted()");

	TBool N = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000008;

	TBool Z = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000004;

	TBool C = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000002;

	TBool V = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000001;

	switch(aCondition)

	{

		case 0:

			return Z;

		case 1:

			return !Z;

		case 2:

			return C;

		case 3:

			return !C;

		case 4:

			return N;

		case 5:

			return !N;

		case 6:

			return V;

		case 7:

			return !V;

		case 8:

			return (C && !Z);

		case 9:

			return (!C || Z);

		case 10:

			return (N == V);

		case 11:

			return (N != V);

		case 12:

			return ((N == V) && !Z);

		case 13:

			return (Z || (N != V));

		case 14:

		case 15:

			return ETrue;

	}

	return EFalse;

}

//

// DRMDStepping::IsPreviousInstructionMovePCToLR

//

TBool DRMDStepping::IsPreviousInstructionMovePCToLR(DThread *aThread)

{

	LOG_MSG("DRMDStepping::IsPreviousInstructionMovePCToLR()");

	TInt err = KErrNone;

	// there are several types of instructions that modify the PC that aren't

	// designated as linked or non linked branches.  the way gcc generates the

	// code can tell us whether or not these instructions are to be treated as

	// linked branches.  the main cases are bx and any type of mov or load or

	// arithmatic operation that changes the PC.  if these are really just

	// function calls that will return, gcc will generate a mov	lr, pc

	// instruction as the previous instruction.  note that this is just for arm

	// and armi

	// get the address of the previous instruction

	TUint32 address = 0;

	err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, address);

	if(err != KErrNone)

	{

		LOG_MSG2("Non-zero error code discarded: %d", err);

	}

	address -= 4;

	TBuf8<4> previousInstruction;

	err = iChannel->DoReadMemory(aThread, address, 4, previousInstruction);

	if (KErrNone != err)

	{

		LOG_MSG2("Error %d reading memory at address %x", address);

		return EFalse;

	}

	const TUint32 movePCToLRIgnoringCondition = 0x01A0E00F;

	TUint32 inst = *(TUint32 *)previousInstruction.Ptr();

	if ((inst & 0x0FFFFFFF) == movePCToLRIgnoringCondition)

	{

		return ETrue;

	}

	return EFalse;

}

//

// DRMDStepping::DecodeDataProcessingInstruction

//

void DRMDStepping::DecodeDataProcessingInstruction(TUint8 aOpcode, TUint32 aOp1, TUint32 aOp2, TUint32 aStatusRegister, TUint32 &aBreakAddress)

{

	LOG_MSG("DRMDStepping::DecodeDataProcessingInstruction()");

	switch(aOpcode)

	{

		case 0:

		{

			// AND

			aBreakAddress = aOp1 & aOp2;

			break;

		}

		case 1:

		{

			// EOR

			aBreakAddress = aOp1 ^ aOp2;

			break;

		}

		case 2:

		{

			// SUB

			aBreakAddress = aOp1 - aOp2;

			break;

		}

		case 3:

		{

			// RSB

			aBreakAddress = aOp2 - aOp1;

			break;

		}

		case 4:

		{

			// ADD

			aBreakAddress = aOp1 + aOp2;

			break;

		}

		case 5:

		{

			// ADC

			aBreakAddress = aOp1 + aOp2 + (aStatusRegister & arm_carry_bit()) ? 1 : 0;

			break;

		}

		case 6:

		{

			// SBC

			aBreakAddress = aOp1 - aOp2 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;

			break;

		}

		case 7:

		{

			// RSC

			aBreakAddress = aOp2 - aOp1 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;

			break;

		}

		case 12:

		{

			// ORR

			aBreakAddress = aOp1 | aOp2;

			break;

		}

		case 13:

		{

			// MOV

			aBreakAddress = aOp2;

			break;

		}

		case 14:

		{

			// BIC

			aBreakAddress = aOp1 & ~aOp2;

			break;

		}

		case 15:

		{

			// MVN

			aBreakAddress = ~aOp2;

			break;

		}

	}

}

//

// DRMDStepping::CurrentInstruction

//

// Returns the current instruction bitpattern (either 32-bits or 16-bits) if possible

TInt DRMDStepping::CurrentInstruction(DThread* aThread, TUint32& aInstruction)

	{

	LOG_MSG("DRMDStepping::CurrentInstruction");

	// What is the current PC?

	TUint32 pc;	

	ReturnIfError(CurrentPC(aThread,pc));

	// Read it one byte at a time to ensure alignment doesn't matter

	TUint32 inst = 0;

	for(TInt i=3;i>=0;i--)

		{

		TBuf8<1> instruction;

		TInt err = iChannel->DoReadMemory(aThread, (pc+i), 1, instruction); 

		if (KErrNone != err)

			{

			LOG_MSG2("DRMDStepping::CurrentInstruction : Failed to read memory at current PC: return 0x%08x",pc);

			return err;

			}

		inst = (inst << 8) | (*(TUint8 *)instruction.Ptr());

		}

	aInstruction = inst;

	LOG_MSG2("DRMDStepping::CurrentInstruction 0x%08x", aInstruction);

	return KErrNone;

	}

//

// DRMDStepping::CurrentArchMode

//

// Determines architecture mode from the supplied cpsr

TInt DRMDStepping::CurrentArchMode(const TUint32 aCpsr, Debug::TArchitectureMode& aMode)

	{

// Thumb2 work will depend on having a suitable cpu architecture to compile for...

#ifdef ECpuJf

	// State table as per ARM ARM DDI0406A, section A.2.5.1

	if(aCpsr & ECpuJf)

		{

		if (aCpsr & ECpuThumb)

			{

			// ThumbEE (Thumb2)

			aMode = Debug::EThumb2EEMode;

			}

		else

			{

			// Jazelle mode - not supported

			return KErrNotSupported;

			}

		}

	else

#endif

		{

		if (aCpsr & ECpuThumb)

			{

			// Thumb mode

			aMode = Debug::EThumbMode;

			}

		else

			{

			// ARM mode

			aMode = Debug::EArmMode;

			}

		}

	return KErrNone;

	}

//

// DRMDStepping::PCAfterInstructionExecutes

//

// Note, this function pretty much ignores all the arguments except for aThread.

// The arguments continue to exist so that the function has the same prototype as

// the original from Nokia. In the long term this function will be re-factored

// to remove obsolete parameters.

//

TUint32 DRMDStepping::PCAfterInstructionExecutes(DThread *aThread, TUint32 aCurrentPC, TUint32 aStatusRegister, TInt aInstSize, /*TBool aStepInto,*/ TUint32 &aNewRangeEnd, TBool &aChangingModes)

{

	LOG_MSG("DRMDStepping::PCAfterInstructionExecutes()");

	// by default we will set the breakpoint at the next instruction

	TUint32 breakAddress = aCurrentPC + aInstSize;

	TInt err = KErrNone;

	// determine the architecture

    TUint32 cpuid;

   	asm("mrc p15, 0, cpuid, c0, c0, 0 ");

	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpuid = 0x%08x\n",cpuid);

    cpuid >>= 8;

    cpuid &= 0xFF;

	// determine the architecture mode for the current instruction

	TArchitectureMode mode = EArmMode;	// Default assumption is ARM 

	// Now we must examine the CPSR to read the T and J bits. See ARM ARM DDI0406A, section B1.3.3

	TUint32 cpsr;

	ReturnIfError(CurrentCPSR(aThread,cpsr));

	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpsr = 0x%08x\n",cpsr);

	// Determine the mode

	ReturnIfError(CurrentArchMode(cpsr,mode));

	// Decode instruction based on current CPU mode

	switch(mode)

	{

		case Debug::EArmMode:

		{

			// Obtain the current instruction bit pattern

			TUint32 inst;

			ReturnIfError(CurrentInstruction(aThread,inst));

			LOG_MSG2("Current instruction: %x", inst);

			// check the conditions to see if this will actually get executed

			if (IsExecuted(((inst>>28) & 0x0000000F), aStatusRegister)) 

			{

				switch(arm_opcode(inst)) // bits 27-25

				{

					case 0:

					{

						switch((inst & 0x00000010) >> 4) // bit 4

						{

							case 0:

							{

								switch((inst & 0x01800000) >> 23) // bits 24-23

								{

									case 2:

									{

										// move to/from status register.  pc updates not allowed

										// or TST, TEQ, CMP, CMN which don't modify the PC

										break;

									}

									default:

									{

										// Data processing immediate shift

										if (arm_rd(inst) == PC_REGISTER)

										{

											TUint32 rn = aCurrentPC + 8;

											if (arm_rn(inst) != PC_REGISTER) // bits 19-16

											{

												err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);

												if(err != KErrNone)

												{

													LOG_MSG2("Non-zero error code discarded: %d", err);

												}

											}

											TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);

											DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);

										}

										break;

									}

								}

								break;

							}					

							case 1:

							{

								switch((inst & 0x00000080) >> 7) // bit 7

								{

									case 0:

									{

										switch((inst & 0x01900000) >> 20) // bits 24-23 and bit 20

										{

											case 0x10:

											{

												// from figure 3-3

												switch((inst & 0x000000F0) >> 4) // bits 7-4

												{

													case 1:

													{

														if (((inst & 0x00400000) >> 22) == 0) // bit 22

														{

															// BX

															// this is a strange case.  normally this is used in the epilogue to branch the the link

															// register.  sometimes it is used to call a function, and the LR is stored in the previous

															// instruction.  since what we want to do is different for the two cases when stepping over,

															// we need to read the previous instruction to see what we should do

															err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);

															if(err != KErrNone)

															{

																LOG_MSG2("Non-zero error code discarded: %d", err);

															}

															if ((breakAddress & 0x00000001) == 1)

															{

																aChangingModes = ETrue;

															}

															breakAddress &= 0xFFFFFFFE;

														}

														break;

													}

													case 3:

													{

														// BLX

														{

															err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);

															if(err != KErrNone)

															{

																LOG_MSG2("Non-zero error code discarded: %d", err);

															}

															if ((breakAddress & 0x00000001) == 1)

															{

																aChangingModes = ETrue;

															}

															breakAddress &= 0xFFFFFFFE;

														}

														break;

													}

													default:

													{

														// either doesn't modify the PC or it is illegal to

														break;

													}

												}

												break;

											}

											default:

											{

												// Data processing register shift

												if (((inst & 0x01800000) >> 23) == 2) // bits 24-23

												{

													// TST, TEQ, CMP, CMN don't modify the PC

												}

												else if (arm_rd(inst) == PC_REGISTER)

												{

													// destination register is the PC

													TUint32 rn = aCurrentPC + 8;

													if (arm_rn(inst) != PC_REGISTER) // bits 19-16

													{

														err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);

														if(err != KErrNone)

														{

															LOG_MSG2("Non-zero error code discarded: %d", err);

														}

													}

													TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);

													DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);

												}

												break;

											}

										}

										break;

									}

									default:

									{

										// from figure 3-2, updates to the PC illegal

										break;

									}

								}

								break;

							}

						}

						break;

					}

					case 1:

					{

						if (((inst & 0x01800000) >> 23) == 2) // bits 24-23

						{

							// cannot modify the PC

							break;

						}

						else if (arm_rd(inst) == PC_REGISTER)

						{

							// destination register is the PC

							TUint32 rn;

							err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); // bits 19-16

							if(err != KErrNone)

							{

								LOG_MSG2("Non-zero error code discarded: %d", err);

							}

							TUint32 shifter = ((arm_data_imm(inst) >> arm_data_rot(inst)) | (arm_data_imm(inst) << (32 - arm_data_rot(inst)))) & 0xffffffff;

							DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);

						}

						break;

					}

					case 2:

					{

						// load/store immediate offset