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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\nkernsmp\arm\ncutils.cia |
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15 // |
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16 // |
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17 |
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18 #include <e32cia.h> |
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19 #include <arm.h> |
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20 #include <arm_gic.h> |
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21 |
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22 extern TSpinLock BTraceLock; |
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23 |
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24 extern "C" { |
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25 extern TUint32 CrashStateOut; |
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26 extern SFullArmRegSet DefaultRegSet; |
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27 } |
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28 |
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29 //#define __DBG_MON_FAULT__ |
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30 //#define __RAM_LOADED_CODE__ |
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31 //#define __EARLY_DEBUG__ |
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32 |
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33 #ifdef _DEBUG |
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34 #define ASM_KILL_LINK(rp,rs) asm("mov "#rs", #0xdf ");\ |
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35 asm("orr "#rs", "#rs", "#rs", lsl #8 ");\ |
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36 asm("orr "#rs", "#rs", "#rs", lsl #16 ");\ |
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37 asm("str "#rs", ["#rp"] ");\ |
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38 asm("str "#rs", ["#rp", #4] "); |
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39 #else |
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40 #define ASM_KILL_LINK(rp,rs) |
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41 #endif |
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42 |
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43 #ifdef __PRI_LIST_MACHINE_CODED__ |
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44 /** Return the priority of the highest priority item present on a priority list. |
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45 |
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46 @return The highest priority present or -1 if the list is empty. |
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47 */ |
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48 EXPORT_C __NAKED__ TInt TPriListBase::HighestPriority() |
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49 { |
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50 asm("ldr r2, [r0, #4] "); // r2=iPresent MSW |
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51 asm("ldr r1, [r0, #0] "); // r1=iPresent LSW |
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52 CLZ(0,2); // r0=31-MSB(r2) |
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53 asm("subs r0, r0, #32 "); // r0=-1-MSB(r2), 0 if r2=0 |
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54 CLZcc(CC_EQ,0,1); // if r2=0, r0=31-MSB(r1) |
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55 asm("rsb r0, r0, #31 "); // r0=highest priority |
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56 __JUMP(,lr); |
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57 } |
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58 |
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59 /** Find the highest priority item present on a priority list. |
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60 If multiple items at the same priority are present, return the first to be |
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61 added in chronological order. |
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62 |
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63 @return a pointer to the item or NULL if the list is empty. |
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64 */ |
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65 EXPORT_C __NAKED__ TPriListLink* TPriListBase::First() |
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66 { |
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67 asm("ldr r2, [r0, #4] "); // r2=iPresent MSW |
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68 asm("ldr r1, [r0], #8 "); // r1=iPresent LSW, r0=&iQueue[0] |
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69 CLZ(3,2); // r3=31-MSB(r2) |
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70 asm("subs r3, r3, #32 "); // r3=-1-MSB(r2), 0 if r2=0 |
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71 CLZcc(CC_EQ,3,1); // if r2=0, r3=31-MSB(r1) |
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72 asm("rsbs r3, r3, #31 "); // r3=highest priority |
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73 asm("ldrpl r0, [r0, r3, lsl #2] "); // if r3>=0 list is nonempty, r0->first entry |
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74 asm("movmi r0, #0 "); // if r3<0 list empty, return NULL |
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75 __JUMP(,lr); |
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76 } |
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77 |
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78 /** Add an item to a priority list. |
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79 |
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80 @param aLink = a pointer to the item - must not be NULL |
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81 */ |
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82 EXPORT_C __NAKED__ void TPriListBase::Add(TPriListLink* /*aLink*/) |
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83 { |
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84 asm("ldrb r2, [r1, #8]" ); // r2=priority of aLink |
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85 asm("add ip, r0, #8 "); // ip=&iQueue[0] |
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86 asm("ldr r3, [ip, r2, lsl #2]! "); // r3->first entry at this priority |
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87 asm("cmp r3, #0 "); // is this first entry at this priority? |
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88 asm("bne pri_list_add_1 "); // branch if not |
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89 asm("str r1, [ip] "); // if queue originally empty, iQueue[pri]=aThread |
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90 asm("ldrb ip, [r0, r2, lsr #3]! "); // ip=relevant byte of present mask, r0->same |
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91 asm("and r2, r2, #7 "); |
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92 asm("mov r3, #1 "); |
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93 asm("str r1, [r1, #0] "); // aThread->next=aThread |
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94 asm("orr ip, ip, r3, lsl r2 "); // ip |= 1<<(pri&7) |
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95 asm("str r1, [r1, #4] "); // aThread->iPrev=aThread |
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96 asm("strb ip, [r0] "); // update relevant byte of present mask |
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97 __JUMP(,lr); |
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98 asm("pri_list_add_1: "); |
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99 asm("ldr ip, [r3, #4] "); // if nonempty, ip=last |
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100 asm("str r1, [r3, #4] "); // first->prev=aThread |
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101 asm("stmia r1, {r3,ip} "); // aThread->next=r3=first, aThread->prev=ip=last |
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102 asm("str r1, [ip, #0] "); // last->next=aThread |
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103 __JUMP(,lr); |
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104 } |
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105 |
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106 |
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107 /** Removes an item from a priority list. |
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108 |
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109 @param aLink A pointer to the item - this must not be NULL. |
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110 */ |
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111 EXPORT_C __NAKED__ void TPriListBase::Remove(TPriListLink* /*aLink*/) |
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112 { |
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113 asm("ldmia r1, {r2,r3} "); // r2=aLink->iNext, r3=aLink->iPrev |
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114 ASM_KILL_LINK(r1,r12); |
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115 asm("subs r12, r1, r2 "); // check if more threads at this priority, r12=0 if not |
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116 asm("bne 1f "); // branch if there are more at same priority |
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117 asm("ldrb r2, [r1, #%a0]" : : "i" _FOFF(NThread, iPriority)); // r2=thread priority |
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118 asm("add r1, r0, #%a0" : : "i" _FOFF(TPriListBase, iQueue)); // r1->iQueue[0] |
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119 asm("str r12, [r1, r2, lsl #2] "); // iQueue[priority]=NULL |
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120 asm("ldrb r1, [r0, r2, lsr #3] "); // r1=relevant byte in present mask |
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121 asm("and r3, r2, #7 "); // r3=priority & 7 |
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122 asm("mov r12, #1 "); |
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123 asm("bic r1, r1, r12, lsl r3 "); // clear bit in present mask |
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124 asm("strb r1, [r0, r2, lsr #3] "); // update relevant byte in present mask |
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125 __JUMP(,lr); |
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126 asm("1: "); // get here if there are other threads at same priority |
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127 asm("ldrb r12, [r1, #%a0]" : : "i" _FOFF(NThread, iPriority)); // r12=thread priority |
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128 asm("add r0, r0, #%a0" : : "i" _FOFF(TPriListBase, iQueue)); // r0=&iQueue[0] |
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129 asm("str r3, [r2, #4] "); // next->prev=prev |
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130 asm("ldr r12, [r0, r12, lsl #2]! "); // r12=iQueue[priority], r0=&iQueue[priority] |
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131 asm("str r2, [r3, #0] "); // and prev->next=next |
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132 asm("cmp r12, r1 "); // if aThread was first... |
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133 asm("streq r2, [r0, #0] "); // iQueue[priority]=aThread->next |
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134 __JUMP(,lr); // finished |
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135 } |
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136 |
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137 |
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138 /** Change the priority of an item on a priority list |
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139 |
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140 @param aLink = pointer to the item to act on - must not be NULL |
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141 @param aNewPriority = new priority for the item |
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142 */ |
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143 EXPORT_C __NAKED__ void TPriListBase::ChangePriority(TPriListLink* /*aLink*/, TInt /*aNewPriority*/) |
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144 { |
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145 asm("ldrb r3, [r1, #8] "); // r3=old priority |
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146 asm("stmfd sp!, {r4-r6,lr} "); |
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147 asm("cmp r3, r2 "); |
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148 asm("ldmeqfd sp!, {r4-r6,pc} "); // if old priority=new, finished |
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149 asm("ldmia r1, {r4,r12} "); // r4=next, r12=prev |
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150 asm("ldmia r0!, {r6,lr} "); // lr:r6=present mask, r0=&iQueue[0] |
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151 asm("subs r5, r4, r1 "); // check if aLink is only one at that priority, r5=0 if it is |
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152 asm("beq change_pri_1 "); // branch if it is |
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153 asm("ldr r5, [r0, r3, lsl #2] "); // r5=iQueue[old priority] |
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154 asm("str r4, [r12, #0] "); // prev->next=next |
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155 asm("str r12, [r4, #4] "); // next->prev=prev |
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156 asm("cmp r5, r1 "); // was aLink first? |
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157 asm("streq r4, [r0, r3, lsl #2] "); // if it was, iQueue[old priority]=aLink->next |
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158 asm("b change_pri_2 "); |
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159 asm("change_pri_1: "); |
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160 asm("str r5, [r0, r3, lsl #2] "); // if empty, set iQueue[old priority]=NULL |
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161 asm("mov r12, #0x80000000 "); |
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162 asm("rsbs r3, r3, #31 "); // r3=31-priority |
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163 asm("bicmi lr, lr, r12, ror r3 "); // if pri>31, clear bit is MS word |
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164 asm("bicpl r6, r6, r12, ror r3 "); // if pri<=31, clear bit in LS word |
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165 asm("change_pri_2: "); |
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166 asm("ldr r4, [r0, r2, lsl #2] "); // r4=iQueue[new priority] |
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167 asm("strb r2, [r1, #8] "); // store new priority |
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168 asm("cmp r4, #0 "); // new priority queue empty? |
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169 asm("bne change_pri_3 "); // branch if not |
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170 asm("str r1, [r0, r2, lsl #2] "); // if new priority queue was empty, iQueue[new p]=aLink |
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171 asm("mov r12, #0x80000000 "); |
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172 asm("str r1, [r1, #0] "); // aLink->next=aLink |
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173 asm("rsbs r2, r2, #31 "); // r2=31-priority |
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174 asm("str r1, [r1, #4] "); // aLink->prev=aLink |
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175 asm("orrmi lr, lr, r12, ror r2 "); // if pri>31, set bit is MS word |
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176 asm("orrpl r6, r6, r12, ror r2 "); // if pri<=31, set bit in LS word |
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177 asm("stmdb r0!, {r6,lr} "); // store present mask and restore r0 |
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178 asm("ldmfd sp!, {r4-r6,pc} "); |
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179 asm("change_pri_3: "); |
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180 asm("ldr r12, [r4, #4] "); // r12->last link at this priority |
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181 asm("str r1, [r4, #4] "); // first->prev=aLink |
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182 asm("str r1, [r12, #0] "); // old last->next=aLink |
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183 asm("stmia r1, {r4,r12} "); // aLink->next=r3=first, aLink->prev=r12=old last |
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184 asm("stmdb r0!, {r6,lr} "); // store present mask and restore r0 |
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185 asm("ldmfd sp!, {r4-r6,pc} "); |
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186 } |
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187 #endif |
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188 |
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189 __NAKED__ void initialiseState(TInt /*aCpu*/, TSubScheduler* /*aSS*/) |
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190 { |
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191 SET_RWNO_TID(,r1); |
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192 __ASM_CLI_MODE(MODE_ABT); |
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193 asm("str sp, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_AbtStackTop)); |
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194 asm("mvn r3, #0 "); |
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195 asm("str r3, [sp, #%a0]" : : "i" _FOFF(SFullArmRegSet, iExcCode)); |
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196 asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_IrqNestCount)); |
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197 __ASM_CLI_MODE(MODE_UND); |
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198 asm("str sp, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_UndStackTop)); |
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199 __ASM_CLI_MODE(MODE_FIQ); |
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200 asm("str sp, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_FiqStackTop)); |
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201 __ASM_CLI_MODE(MODE_IRQ); |
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202 asm("str sp, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_IrqStackTop)); |
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203 __ASM_CLI_MODE(MODE_SVC); |
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204 asm("ldr r2, __TheScheduler "); |
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205 asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, i_ScuAddr)); |
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206 asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_ScuAddr)); |
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207 asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, i_GicDistAddr)); |
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208 asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicDistAddr)); |
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209 asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, i_GicCpuIfcAddr)); |
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210 asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicCpuIfcAddr)); |
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211 asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, i_LocalTimerAddr)); |
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212 asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_LocalTimerAddr)); |
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213 asm("mov r3, #0 "); |
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214 SET_RWRO_TID(,r3); |
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215 SET_RWRW_TID(,r3); |
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216 |
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217 __JUMP(,lr); |
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218 |
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219 asm("__TheScheduler: "); |
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220 asm(".word TheScheduler "); |
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221 } |
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222 |
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223 __NAKED__ TUint32 __mpid() |
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224 { |
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225 asm("mrc p15, 0, r0, c0, c0, 5 "); |
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226 __JUMP(,lr); |
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227 } |
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228 |
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229 /** @internalTechnology |
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230 |
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231 Called to indicate that the system has crashed and all CPUs should be |
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232 halted and should dump their registers. |
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233 |
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234 */ |
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235 __NAKED__ void NKern::NotifyCrash(const TAny* /*a0*/, TInt /*a1*/) |
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236 { |
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237 asm("stmfd sp!, {r0-r1} "); // save parameters |
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238 GET_RWNO_TID(,r0); |
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239 asm("cmp r0, #0 "); |
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240 asm("ldreq r0, __SS0 "); |
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241 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TSubScheduler,i_Regs)); |
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242 asm("cmp r0, #0 "); |
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243 asm("ldreq r0, __DefaultRegs "); |
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244 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iExcCode)); |
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245 asm("cmp r1, #0 "); // context already saved? |
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246 asm("bge state_already_saved "); // skip if so |
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247 asm("mov r1, lr "); |
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248 asm("bl " CSM_ZN3Arm9SaveStateER14SFullArmRegSet ); |
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249 asm("str r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iN.iR15)); |
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250 asm("ldmia sp!, {r2-r3} "); // original R0,R1 |
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251 asm("stmia r0, {r2-r3} "); // save original R0,R1 |
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252 asm("add r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode)); |
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253 asm("mov r4, r0 "); // save pointer to i_Regs |
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254 asm("stmib r1, {r2-r3} "); // save a0, a1 in iCrashArgs |
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255 asm("mov r1, #13 "); // r1 = regnum |
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256 asm("mrs r2, cpsr "); // r2 = mode |
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257 asm("bl " CSM_ZN3Arm3RegER14SFullArmRegSetim ); // r0 = pointer to exception mode R13 |
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258 asm("str sp, [r0] "); // save correct original value for exception mode R13 |
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259 asm("b state_save_complete "); |
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260 |
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261 asm("state_already_saved: "); |
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262 asm("ldmia sp!, {r2-r3} "); // original R0,R1 |
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263 asm("add r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode)); |
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264 asm("ldr r4, [r1, #4]! "); |
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265 asm("cmp r4, #0 "); |
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266 asm("stmeqia r1, {r2-r3} "); // save a0, a1 in iCrashArgs, provided iCrashArgs not already set |
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267 asm("mov r4, r0 "); // save pointer to i_Regs |
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268 asm("state_save_complete: "); |
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269 |
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270 __ASM_CLI_MODE(MODE_FIQ); // mode_fiq, interrupts off |
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271 GET_RWNO_TID(,r0); |
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272 asm("ldr r1, __CrashState "); |
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273 asm("cmp r0, #0 "); |
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274 asm("moveq r2, #1 "); |
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275 asm("streq r2, [r1] "); |
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276 asm("beq skip_other_cores "); // If subscheduler not yet set, don't bother with other cores |
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277 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, iCpuMask)); |
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278 asm("ldr r5, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicCpuIfcAddr)); |
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279 // asm("ldr r4, [r0, #%a0]" : : "i" _FOFF(TSubScheduler,i_Regs)); |
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280 asm("bic sp, sp, #4 "); // align stack to multiple of 8 |
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281 |
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282 __DATA_MEMORY_BARRIER_Z__(r6); |
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283 asm("1: "); |
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284 LDREX(3,1); |
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285 asm("orr r5, r3, r2 "); |
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286 STREX(12,5,1); // set bit in CrashState for this CPU |
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287 asm("cmp r12, #0 "); |
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288 asm("bne 1b "); |
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289 __DATA_MEMORY_BARRIER__(r6); |
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290 asm("cmp r3, #0 "); // were we first to crash? |
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291 asm("beq first_to_crash "); // branch if so |
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292 |
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293 // we weren't first to crash, so wait here for a crash IPI |
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294 // disable all interrupts except for CRASH_IPI |
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295 GET_RWNO_TID(,r0); |
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296 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicCpuIfcAddr)); |
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297 asm("mov r1, #0 "); |
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298 asm("1: "); |
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299 asm("add r1, r1, #1 "); |
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300 asm("str r1, [r0, #%a0]" : : "i" _FOFF(GicCpuIfc, iPriMask)); |
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301 __DATA_SYNC_BARRIER__(r6); |
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302 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(GicCpuIfc, iPriMask)); |
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303 asm("cmp r2, #0 "); |
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304 asm("beq 1b "); // loop until priority mask is nonzero |
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305 |
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306 asm("2: "); |
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307 __ASM_STI_MODE(MODE_ABT); |
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308 ARM_WFE; |
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309 asm("b 2b "); // loop until we get a CRASH_IPI |
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310 |
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311 // This CPU was first to crash |
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312 asm("first_to_crash: "); |
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313 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, iScheduler)); |
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314 asm("ldr r7, __CrashStateOut "); |
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315 asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, iActiveCpus1)); |
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316 asm("str r3, [r7] "); // mask of CPUs pending |
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317 asm("ldr r5, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicDistAddr)); |
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318 asm("ldr r1, __CrashIPIWord "); |
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319 __DATA_SYNC_BARRIER_Z__(r6); |
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320 asm("str r1, [r5, #%a0]" : : "i" _FOFF(GicDistributor, iSoftIrq)); // send CRASH_IPI to all other CPUs |
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321 __DATA_SYNC_BARRIER__(r6); |
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322 |
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323 asm("skip_other_cores: "); |
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324 asm("mov r0, #0 "); |
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325 asm("mov r1, #0 "); |
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326 asm("mov r2, #0 "); |
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327 asm("bl NKCrashHandler "); // call NKCrashHandler(0,0,0) |
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328 |
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329 __DATA_SYNC_BARRIER__(r6); |
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330 GET_RWNO_TID(,r0); |
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331 asm("cmp r0, #0 "); |
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332 asm("beq skip_other_cores2 "); // If subscheduler not yet set, don't bother with other cores |
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333 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, iCpuMask)); |
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334 asm("7: "); |
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335 LDREX(1,7); |
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336 asm("bic r1, r1, r2 "); |
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337 STREX(3,1,7); // atomic { CrashStateOut &= ~iCpuMask; } |
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338 asm("cmp r3, #0 "); |
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339 asm("bne 7b "); |
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340 asm("1: "); |
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341 asm("ldr r1, [r7] "); |
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342 asm("cmp r1, #0 "); // wait for all CPUs to acknowledge |
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343 asm("beq 2f "); |
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344 asm("adds r6, r6, #1 "); |
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345 asm("bne 1b "); // if not ACKed after 2^32 iterations give up waiting |
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346 asm("2: "); |
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347 __DATA_MEMORY_BARRIER_Z__(r0); |
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348 |
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349 asm("skip_other_cores2: "); |
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350 asm("mov r0, #1 "); |
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351 asm("ldr r1, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR0)); // original R0 = a0 parameter |
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352 asm("ldr r2, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR1)); // original R1 = a1 parameter |
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353 asm("bl NKCrashHandler "); // call NKCrashHandler(1,a0,a1) - shouldn't return |
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354 |
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355 // shouldn't get back here |
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356 __ASM_CRASH(); |
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357 |
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358 asm("__CrashState: "); |
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359 asm(".word %a0" : : "i" ((TInt)&CrashState)); |
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360 asm("__CrashStateOut: "); |
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361 asm(".word CrashStateOut "); |
|
362 asm("__CrashIPIWord: "); |
|
363 asm(".word %a0" : : "i" ( (TInt)GIC_IPI_OTHERS(CRASH_IPI_VECTOR) )); |
|
364 asm("__SS0: "); |
|
365 asm(".word %a0" : : "i" ((TInt)&TheSubSchedulers[0])); |
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366 asm("__DefaultRegs: "); |
|
367 asm(".word %a0" : : "i" ((TInt)&DefaultRegSet)); |
|
368 } |
|
369 |
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370 |
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371 #ifdef __USE_BTRACE_LOCK__ |
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372 #define __ASM_ACQUIRE_BTRACE_LOCK(regs) \ |
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373 asm("stmfd sp!, " regs); \ |
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374 asm("ldr r0, __BTraceLock "); \ |
|
375 asm("bl " CSM_ZN9TSpinLock11LockIrqSaveEv ); \ |
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376 asm("mov r4, r0 "); \ |
|
377 asm("ldmfd sp!, " regs) |
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378 |
|
379 #define __ASM_RELEASE_BTRACE_LOCK() \ |
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380 asm("stmfd sp!, {r0-r1} "); \ |
|
381 asm("ldr r0, __BTraceLock "); \ |
|
382 asm("mov r1, r4 "); \ |
|
383 asm("bl " CSM_ZN9TSpinLock16UnlockIrqRestoreEi ); \ |
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384 asm("ldmfd sp!, {r0-r1} ") |
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385 |
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386 #else |
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387 #define __ASM_ACQUIRE_BTRACE_LOCK(regs) |
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388 #define __ASM_RELEASE_BTRACE_LOCK() |
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389 #endif |
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390 |
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391 |
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392 __NAKED__ EXPORT_C TBool BTrace::Out(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3) |
|
393 { |
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394 asm("stmdb sp!, {r2,r3,r4,lr}"); |
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395 __ASM_ACQUIRE_BTRACE_LOCK("{r0-r1}"); |
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396 asm("ldr r12, __BTraceData"); |
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397 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
398 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
|
399 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
400 asm("ldr r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
|
401 asm("adr lr, 9f"); |
|
402 asm("cmp r2, #0"); |
|
403 asm("moveq r0, #0"); |
|
404 __JUMP(ne, r12); |
|
405 asm("9: "); |
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406 __ASM_RELEASE_BTRACE_LOCK(); |
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407 __POPRET("r2,r3,r4,"); |
|
408 } |
|
409 |
|
410 __NAKED__ EXPORT_C TBool BTrace::OutN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize) |
|
411 { |
|
412 asm("stmdb sp!, {r2,r3,r4,lr}"); |
|
413 __ASM_ACQUIRE_BTRACE_LOCK("{r0-r3}"); |
|
414 asm("ldr r12, __BTraceData"); |
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415 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
416 asm("ldr r14, [sp, #16]"); // r14 = aDataSize |
|
417 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
418 asm("ldr r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
|
419 asm("cmp r2, #0"); |
|
420 asm("moveq r0, #0"); |
|
421 asm("beq 0f "); |
|
422 |
|
423 asm("cmp r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
424 asm("movhi r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
425 asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8)))); |
|
426 asm("add r0, r0, r14"); |
|
427 asm("subs r14, r14, #1"); |
|
428 asm("ldrhs r2, [r3]"); // get first word of aData is aDataSize!=0 |
|
429 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
|
430 asm("cmp r14, #4"); |
|
431 asm("strlo r2, [sp, #4]"); // replace aData with first word if aDataSize is 1-4 |
|
432 |
|
433 asm("mov lr, pc"); |
|
434 __JUMP(, r12); |
|
435 asm("0: "); |
|
436 __ASM_RELEASE_BTRACE_LOCK(); |
|
437 __POPRET("r2,r3,r4,"); |
|
438 } |
|
439 |
|
440 __NAKED__ EXPORT_C TBool BTrace::OutX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3) |
|
441 { |
|
442 asm("stmdb sp!, {r2,r3,r4,lr}"); |
|
443 __ASM_ACQUIRE_BTRACE_LOCK("{r0-r1}"); |
|
444 asm("ldr r12, __BTraceData"); |
|
445 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
446 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
|
447 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
448 asm("mrs r14, cpsr "); |
|
449 asm("ldr r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
|
450 asm("cmp r2, #0"); // check category filter |
|
451 asm("moveq r0, #0"); |
|
452 asm("beq 0f "); // if category disabled, exit now |
|
453 __ASM_CLI(); |
|
454 asm("and r2, r14, #0x0f "); |
|
455 asm("cmp r2, #3 "); |
|
456 asm("movhi r2, #2 "); // r2 = context ID = 1 for FIQ, 2 for IRQ/ABT/UND/SYS |
|
457 asm("bne 1f "); |
|
458 GET_RWNO_TID(,r1); |
|
459 asm("movs r2, r1 "); // r2 = context ID = 0 for early boot, no threads |
|
460 asm("beq 1f "); |
|
461 asm("ldrb r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iInIDFC)); |
|
462 asm("cmp r2, #0 "); |
|
463 asm("ldreq r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread)); |
|
464 asm("movne r2, #3 "); // r2 = context ID = 3 for IDFC = NThread pointer for thread |
|
465 asm("1: "); |
|
466 asm("msr cpsr, r14 "); |
|
467 asm("mov lr, pc"); |
|
468 __JUMP(, r12); |
|
469 asm("0: "); |
|
470 __ASM_RELEASE_BTRACE_LOCK(); |
|
471 __POPRET("r2,r3,r4,"); |
|
472 } |
|
473 |
|
474 __NAKED__ EXPORT_C TBool BTrace::OutNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize) |
|
475 { |
|
476 asm("stmdb sp!, {r2,r3,r4,lr}"); |
|
477 __ASM_ACQUIRE_BTRACE_LOCK("{r0-r3}"); |
|
478 asm("ldr r12, __BTraceData"); |
|
479 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
480 asm("ldr r14, [sp, #16]"); // r14 = aDataSize |
|
481 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
482 asm("ldr r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
|
483 asm("cmp r2, #0"); // check category filter |
|
484 asm("moveq r0, #0"); |
|
485 asm("beq 0f "); // if category disabled, exit now |
|
486 |
|
487 asm("cmp r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
488 asm("movhi r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
489 asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8)))); |
|
490 asm("add r0, r0, r14"); |
|
491 asm("subs r14, r14, #1"); |
|
492 asm("ldrhs r2, [r3]"); // get first word of aData is aDataSize!=0 |
|
493 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
|
494 asm("cmp r14, #4"); |
|
495 asm("strlo r2, [sp, #4]"); // replace aData with first word if aDataSize is 1-4 |
|
496 |
|
497 asm("mrs r14, cpsr "); |
|
498 __ASM_CLI(); |
|
499 asm("and r2, r14, #0x0f "); |
|
500 asm("cmp r2, #3 "); |
|
501 asm("movhi r2, #2 "); // r2 = context ID = 1 for FIQ, 2 for IRQ/ABT/UND/SYS |
|
502 asm("bne 1f "); |
|
503 GET_RWNO_TID(,r1); |
|
504 asm("movs r2, r1 "); // r2 = context ID = 0 for early boot, no threads |
|
505 asm("beq 1f "); |
|
506 asm("ldrb r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iInIDFC)); |
|
507 asm("cmp r2, #0 "); |
|
508 asm("ldreq r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread)); |
|
509 asm("movne r2, #3 "); // r2 = context ID = 3 for IDFC = NThread pointer for thread |
|
510 asm("1: "); |
|
511 asm("msr cpsr, r14 "); |
|
512 |
|
513 asm("mov lr, pc"); |
|
514 __JUMP(, r12); |
|
515 asm("0: "); |
|
516 __ASM_RELEASE_BTRACE_LOCK(); |
|
517 __POPRET("r2,r3,r4,"); |
|
518 } |
|
519 |
|
520 __NAKED__ EXPORT_C TBool BTrace::OutBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize) |
|
521 { |
|
522 asm("stmdb sp!, {r4,lr}"); |
|
523 asm("ldr r12, __BTraceData"); |
|
524 asm("str lr, [sp, #-4]! "); // PC |
|
525 asm("and r14, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
526 asm("ldrb r14, [r12, r14, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
527 asm("cmp r14, #0"); // check category filter |
|
528 asm("addeq sp, sp, #4 "); |
|
529 asm("moveq r0, #0 "); |
|
530 asm("beq 0f "); // if category disabled, exit now |
|
531 |
|
532 asm("mrs r14, cpsr "); |
|
533 __ASM_CLI(); |
|
534 asm("and r12, r14, #0x0f "); |
|
535 asm("cmp r12, #3 "); |
|
536 asm("movhi r12, #2 "); // r12 = context ID = 1 for FIQ, 2 for IRQ/ABT/UND/SYS |
|
537 asm("bne 1f "); |
|
538 GET_RWNO_TID(,r12); |
|
539 asm("cmp r12, #0 "); // r2 = context ID = 0 for early boot, no threads |
|
540 asm("beq 1f "); |
|
541 asm("ldrb r12, [r12, #%a0]" : : "i" _FOFF(TSubScheduler,iInIDFC)); |
|
542 asm("cmp r12, #0 "); |
|
543 GET_RWNO_TID(eq,r12); |
|
544 asm("ldreq r12, [r12, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread)); |
|
545 asm("movne r12, #3 "); // r12 = context ID = 3 for IDFC = NThread pointer for thread |
|
546 asm("1: "); |
|
547 asm("msr cpsr, r14 "); |
|
548 asm("str r12, [sp, #-4]! "); // context ID |
|
549 asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm); |
|
550 asm("add sp, sp, #8"); |
|
551 asm("0: "); |
|
552 __POPRET("r4,"); |
|
553 |
|
554 asm("__BTraceLock: "); |
|
555 asm(".word %a0" : : "i" ((TInt)&BTraceLock)); |
|
556 asm("__BTraceData: "); |
|
557 asm(".word BTraceData "); |
|
558 } |
|
559 |
|
560 |
|
561 __NAKED__ EXPORT_C TBool BTrace::OutFiltered(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3) |
|
562 { |
|
563 // fall through to OutFilteredX... |
|
564 } |
|
565 |
|
566 __NAKED__ EXPORT_C TBool BTrace::OutFilteredX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3) |
|
567 { |
|
568 asm("stmdb sp!, {r2,r3,r4,lr}"); |
|
569 asm("ldr r12, __BTraceData"); |
|
570 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
571 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
|
572 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
573 asm("cmp r2, #0"); |
|
574 asm("moveq r0, #0"); |
|
575 asm("beq 9f "); |
|
576 |
|
577 // r0=header, r1=a1=secondary filter UID, r2=unused, r3=a1, r12->SBTraceData |
|
578 // if trace enabled return r0,r1,r3 unmodified, r2=context value r12->handler, Z=0 |
|
579 // if trace disabled return r0=0 Z=1 |
|
580 asm("bl btrace_check_filter2 "); |
|
581 asm("beq 9f "); |
|
582 __ASM_ACQUIRE_BTRACE_LOCK("{r0,r2,r3,r12}"); |
|
583 asm("adr lr, 1f "); |
|
584 __JUMP(, r12); |
|
585 asm("1: "); |
|
586 __ASM_RELEASE_BTRACE_LOCK(); |
|
587 asm("9: "); |
|
588 __POPRET("r2,r3,r4,"); |
|
589 |
|
590 asm("btrace_check_filter2: "); |
|
591 asm("stmfd sp!, {r0,r1,r3,r4,r12,lr} "); |
|
592 asm("mov r0, r12 "); |
|
593 asm("bl CheckFilter2__11SBTraceDataUl "); |
|
594 asm("cmp r0, #0 "); |
|
595 asm("beq 0f "); |
|
596 asm("mrs r14, cpsr "); |
|
597 __ASM_CLI(); |
|
598 asm("and r2, r14, #0x0f "); |
|
599 asm("cmp r2, #3 "); |
|
600 asm("movhi r2, #2 "); // r2 = context ID = 1 for FIQ, 2 for IRQ/ABT/UND/SYS |
|
601 asm("bne 1f "); |
|
602 GET_RWNO_TID(,r4); |
|
603 asm("movs r2, r4 "); // r2 = context ID = 0 for early boot, no threads |
|
604 asm("beq 1f "); |
|
605 asm("ldrb r2, [r4, #%a0]" : : "i" _FOFF(TSubScheduler,iInIDFC)); |
|
606 asm("cmp r2, #0 "); |
|
607 asm("ldreq r2, [r4, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread)); |
|
608 asm("movne r2, #3 "); // r2 = context ID = 3 for IDFC = NThread pointer for thread |
|
609 asm("1: "); |
|
610 asm("msr cpsr, r14 "); |
|
611 asm("0: "); |
|
612 asm("ldmfd sp!, {r0,r1,r3,r4,r12,lr} "); |
|
613 asm("moveq r0, #0 "); |
|
614 asm("ldrne r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
|
615 __JUMP(,lr); |
|
616 } |
|
617 |
|
618 __NAKED__ EXPORT_C TBool BTrace::OutFilteredN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize) |
|
619 { |
|
620 // fall through to OutFilteredNX... |
|
621 } |
|
622 |
|
623 __NAKED__ EXPORT_C TBool BTrace::OutFilteredNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize) |
|
624 { |
|
625 asm("stmdb sp!, {r2,r3,r4,lr}"); |
|
626 asm("ldr r12, __BTraceData"); |
|
627 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
628 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
629 asm("cmp r2, #0"); |
|
630 asm("moveq r0, #0"); |
|
631 asm("beq 9f "); |
|
632 |
|
633 // r0=header, r1=a1=secondary filter UID, r2=unused, r3=aData, r12->SBTraceData |
|
634 // if trace enabled return r0,r1,r3 unmodified, r2=context value r12->handler, Z=0 |
|
635 // if trace disabled return r0=0 Z=1 |
|
636 asm("bl btrace_check_filter2 "); |
|
637 asm("beq 9f "); |
|
638 |
|
639 __ASM_ACQUIRE_BTRACE_LOCK("{r0-r3,r11,r12}"); |
|
640 asm("ldr r14, [sp, #16] "); // r14 = aDataSize |
|
641 asm("cmp r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
642 asm("movhi r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
643 asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8)))); |
|
644 asm("add r0, r0, r14 "); |
|
645 asm("subs r14, r14, #1 "); |
|
646 asm("ldrhs r3, [r3] "); // get first word of aData if aDataSize!=0 |
|
647 asm("cmp r14, #4 "); |
|
648 asm("strlo r3, [sp, #4] "); // replace aData with first word if aDataSize is 1-4 |
|
649 asm("mov r3, r1 "); // r3 = a1 (ready for call to handler) |
|
650 asm("adr lr, 1f "); |
|
651 __JUMP(, r12); |
|
652 asm("1: "); |
|
653 __ASM_RELEASE_BTRACE_LOCK(); |
|
654 asm("9: "); |
|
655 __POPRET("r2,r3,r4,"); |
|
656 } |
|
657 |
|
658 __NAKED__ EXPORT_C TBool BTrace::OutFilteredBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize) |
|
659 { |
|
660 asm("stmdb sp!, {r4,lr} "); |
|
661 asm("ldr r12, __BTraceData "); |
|
662 asm("stmfd sp!, {r2,lr} "); // save aData, PC |
|
663 asm("and r14, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
664 asm("ldrb r14, [r12, r14, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
665 asm("cmp r14, #0 "); // check category filter |
|
666 asm("blne btrace_check_filter2 "); // if enabled, check secondary filter |
|
667 asm("addeq sp, sp, #8 "); |
|
668 asm("moveq r0, #0 "); |
|
669 asm("beq 9f "); // if category or secondary filter disabled, exit now |
|
670 asm("mov r12, r2 "); |
|
671 asm("ldr r2, [sp, #0] "); // restore aData into r2 |
|
672 asm("str r12, [sp, #0] "); // Context ID |
|
673 asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm); |
|
674 asm("add sp, sp, #8 "); |
|
675 asm("9: "); |
|
676 __POPRET("r4,"); |
|
677 } |
|
678 |
|
679 |
|
680 /******************************************************************************/ |
|
681 |
|
682 /** Save all the ARM registers |
|
683 |
|
684 @internalTechnology |
|
685 */ |
|
686 __NAKED__ void Arm::SaveState(SFullArmRegSet&) |
|
687 { |
|
688 asm("stmia r0, {r0-r14}^ "); // save R0-R7, R8_usr-R14_usr |
|
689 asm("str lr, [r0, #60]! "); // save R15 |
|
690 asm("mrs r1, cpsr "); |
|
691 asm("str r1, [r0, #4]! "); // save CPSR |
|
692 asm("bic r2, r1, #0x1f "); |
|
693 asm("orr r2, r2, #0xd3 "); // mode_svc, all interrupts off |
|
694 asm("msr cpsr, r2 "); |
|
695 asm("stmib r0!, {r13,r14} "); // save R13_svc, R14_svc |
|
696 asm("mrs r3, spsr "); |
|
697 asm("str r3, [r0, #4]! "); // save SPSR_svc |
|
698 asm("bic r2, r1, #0x1f "); |
|
699 asm("orr r2, r2, #0xd7 "); // mode_abt, all interrupts off |
|
700 asm("msr cpsr, r2 "); |
|
701 asm("stmib r0!, {r13,r14} "); // save R13_abt, R14_abt |
|
702 asm("mrs r3, spsr "); |
|
703 asm("str r3, [r0, #4]! "); // save SPSR_abt |
|
704 asm("bic r2, r1, #0x1f "); |
|
705 asm("orr r2, r2, #0xdb "); // mode_und, all interrupts off |
|
706 asm("msr cpsr, r2 "); |
|
707 asm("stmib r0!, {r13,r14} "); // save R13_und, R14_und |
|
708 asm("mrs r3, spsr "); |
|
709 asm("str r3, [r0, #4]! "); // save SPSR_und |
|
710 asm("bic r2, r1, #0x1f "); |
|
711 asm("orr r2, r2, #0xd2 "); // mode_irq, all interrupts off |
|
712 asm("msr cpsr, r2 "); |
|
713 asm("stmib r0!, {r13,r14} "); // save R13_irq, R14_irq |
|
714 asm("mrs r3, spsr "); |
|
715 asm("str r3, [r0, #4]! "); // save SPSR_irq |
|
716 asm("bic r2, r1, #0x1f "); |
|
717 asm("orr r2, r2, #0xd1 "); // mode_fiq, all interrupts off |
|
718 asm("msr cpsr, r2 "); |
|
719 asm("stmib r0!, {r8-r14} "); // save R8_fiq ... R14_fiq |
|
720 asm("mrs r3, spsr "); |
|
721 asm("str r3, [r0, #4]! "); // save SPSR_fiq |
|
722 asm("bic r2, r1, #0x1f "); |
|
723 asm("orr r2, r2, #0xd3 "); // mode_svc, all interrupts off |
|
724 asm("msr cpsr, r2 "); |
|
725 |
|
726 asm("mov r4, #0 "); |
|
727 asm("mov r5, #0 "); |
|
728 asm("mov r6, #0 "); |
|
729 asm("mov r7, #0 "); |
|
730 asm("mov r8, #0 "); |
|
731 asm("mov r9, #0 "); |
|
732 asm("mov r10, #0 "); |
|
733 asm("mov r11, #0 "); |
|
734 |
|
735 // monitor mode - skip for now |
|
736 asm("mov r3, #0 "); |
|
737 asm("stmib r0!, {r4-r6} "); // R13_mon, R14_mon, SPSR_mon |
|
738 |
|
739 // zero spare words |
|
740 asm("mov r3, #0 "); |
|
741 asm("stmib r0!, {r4-r11} "); |
|
742 asm("add r0, r0, #4 "); // r0 = &a.iA |
|
743 |
|
744 #ifdef __CPU_ARMV7 |
|
745 asm("mrc p14, 6, r3, c1, c0, 0 "); |
|
746 #else |
|
747 asm("mov r3, #0 "); |
|
748 #endif |
|
749 asm("str r3, [r0], #4 "); // TEEHBR |
|
750 #ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG |
|
751 GET_CAR(,r3); |
|
752 #else |
|
753 asm("mov r3, #0 "); |
|
754 #endif |
|
755 asm("str r3, [r0], #4 "); // CPACR |
|
756 |
|
757 // skip SCR, SDER, NSACR, PMCR, MVBAR for now |
|
758 asm("mov r3, #0 "); |
|
759 asm("stmia r0!, {r4-r8} "); // SCR, SDER, NSACR, PMCR, MVBAR |
|
760 |
|
761 // zero spare words |
|
762 asm("mov r3, #0 "); |
|
763 asm("stmia r0!, {r3-r11} "); // r0 = &a.iB[0] |
|
764 |
|
765 // just fill in iB[0] |
|
766 #ifdef __CPU_HAS_MMU |
|
767 asm("mrc p15, 0, r3, c1, c0, 0 "); |
|
768 asm("str r3, [r0], #4 "); // SCTLR |
|
769 #ifdef __CPU_HAS_ACTLR |
|
770 asm("mrc p15, 0, r3, c1, c0, 1 "); |
|
771 #else |
|
772 asm("mov r3, #0 "); |
|
773 #endif |
|
774 asm("str r3, [r0], #4 "); // ACTLR |
|
775 asm("mrc p15, 0, r3, c2, c0, 0 "); |
|
776 asm("str r3, [r0], #4 "); // TTBR0 |
|
777 #ifdef __CPU_HAS_TTBR1 |
|
778 asm("mrc p15, 0, r2, c2, c0, 1 "); |
|
779 asm("mrc p15, 0, r3, c2, c0, 2 "); |
|
780 #else |
|
781 asm("mov r2, #0 "); |
|
782 asm("mov r3, #0 "); |
|
783 #endif |
|
784 asm("stmia r0!, {r2,r3} "); // TTBR1, TTBCR |
|
785 asm("mrc p15, 0, r3, c3, c0, 0 "); |
|
786 asm("str r3, [r0], #4 "); // DACR |
|
787 #ifdef __CPU_MEMORY_TYPE_REMAPPING |
|
788 asm("mrc p15, 0, r2, c10, c2, 0 "); |
|
789 asm("mrc p15, 0, r3, c10, c2, 1 "); |
|
790 #else |
|
791 asm("mov r2, #0 "); |
|
792 asm("mov r3, #0 "); |
|
793 #endif |
|
794 asm("stmia r0!, {r2,r3} "); // PRRR, NMRR |
|
795 #ifdef __CPU_ARMV7 |
|
796 asm("mrc p15, 0, r3, c12, c0, 0 "); |
|
797 #else |
|
798 asm("mov r3, #0 "); |
|
799 #endif |
|
800 asm("str r3, [r0], #4 "); // VBAR |
|
801 #if defined(__CPU_SA1) || defined(__CPU_ARM920T) || defined(__CPU_ARM925T) || defined(__CPU_ARMV5T) || defined(__CPU_ARMV6) || defined(__CPU_ARMV7) |
|
802 asm("mrc p15, 0, r3, c13, c0, 0 "); |
|
803 #else |
|
804 asm("mov r3, #0 "); |
|
805 #endif |
|
806 asm("str r3, [r0], #4 "); // FCSEIDR |
|
807 #if defined(__CPU_ARMV6) || defined(__CPU_ARMV7) |
|
808 asm("mrc p15, 0, r3, c13, c0, 1 "); |
|
809 #else |
|
810 asm("mov r3, #0 "); |
|
811 #endif |
|
812 asm("str r3, [r0], #4 "); // CONTEXTIDR |
|
813 #ifdef __CPU_HAS_CP15_THREAD_ID_REG |
|
814 GET_RWRW_TID(,r2); |
|
815 GET_RWRO_TID(,r3); |
|
816 GET_RWNO_TID(,r12); |
|
817 #else |
|
818 asm("mov r2, #0 "); |
|
819 asm("mov r3, #0 "); |
|
820 asm("mov r12, #0 "); |
|
821 #endif |
|
822 asm("stmia r0!, {r2,r3,r12} "); // RWRWTID, RWROTID, RWNOTID |
|
823 asm("mrc p15, 0, r2, c5, c0, 0 "); // DFSR |
|
824 #ifdef __CPU_ARM_HAS_SPLIT_FSR |
|
825 asm("mrc p15, 0, r3, c5, c0, 1 "); // IFSR |
|
826 #else |
|
827 asm("mov r3, #0 "); |
|
828 #endif |
|
829 asm("stmia r0!, {r2,r3} "); // DFSR, IFSR |
|
830 #ifdef __CPU_ARMV7 |
|
831 asm("mrc p15, 0, r2, c5, c1, 0 "); // ADFSR |
|
832 asm("mrc p15, 0, r3, c5, c1, 1 "); // AIFSR |
|
833 #else |
|
834 asm("mov r2, #0 "); |
|
835 asm("mov r3, #0 "); |
|
836 #endif |
|
837 asm("stmia r0!, {r2,r3} "); // ADFSR, AIFSR |
|
838 asm("mrc p15, 0, r2, c6, c0, 0 "); // DFAR |
|
839 #ifdef __CPU_ARM_HAS_CP15_IFAR |
|
840 asm("mrc p15, 0, r3, c6, c0, 2 "); // IFAR |
|
841 #else |
|
842 asm("mov r3, #0 "); |
|
843 #endif |
|
844 asm("stmia r0!, {r2,r3} "); // DFAR, IFAR |
|
845 |
|
846 // zero spare words |
|
847 asm("stmia r0!, {r4-r7} "); |
|
848 asm("stmia r0!, {r4-r11} "); |
|
849 #else // __CPU_HAS_MMU |
|
850 asm("stmia r0!, {r4-r11} "); // no MMU so zero fill |
|
851 asm("stmia r0!, {r4-r11} "); // no MMU so zero fill |
|
852 asm("stmia r0!, {r4-r11} "); // no MMU so zero fill |
|
853 asm("stmia r0!, {r4-r11} "); // no MMU so zero fill |
|
854 #endif // __CPU_HAS_MMU |
|
855 |
|
856 // zero iB[1] |
|
857 asm("stmia r0!, {r4-r11} "); |
|
858 asm("stmia r0!, {r4-r11} "); |
|
859 asm("stmia r0!, {r4-r11} "); |
|
860 asm("stmia r0!, {r4-r11} "); // r0 = &a.iMore[0] |
|
861 asm("add r1, r0, #62*8 "); // r1 = &a.iExcCode |
|
862 |
|
863 // Save VFP state |
|
864 // Save order: |
|
865 // FPEXC FPSCR |
|
866 // VFPv2 ONLY: FPINST FPINST2 |
|
867 // D0-D3 D4-D7 D8-D11 D12-D15 |
|
868 // VFPv3 ONLY: D16-D19 D20-D23 D24-D27 D28-D31 |
|
869 #ifdef __CPU_HAS_VFP |
|
870 GET_CAR(,r2); |
|
871 asm("bic r2, r2, #0x00f00000 "); |
|
872 #ifdef __VFP_V3 |
|
873 asm("bic r2, r2, #0xc0000000 "); // mask off ASEDIS, D32DIS |
|
874 #endif |
|
875 asm("orr r2, r2, #0x00500000 "); // enable privileged access to CP10, CP11 |
|
876 SET_CAR(,r2); |
|
877 VFP_FMRX(,2,VFP_XREG_FPEXC); // r2=FPEXC |
|
878 asm("orr r3, r2, #%a0" : : "i" ((TInt)VFP_FPEXC_EN)); |
|
879 VFP_FMXR(,VFP_XREG_FPEXC,3); // enable VFP |
|
880 __DATA_SYNC_BARRIER__(r4); |
|
881 __INST_SYNC_BARRIER__(r4); |
|
882 VFP_FMRX(,3,VFP_XREG_FPSCR); // r3=FPSCR |
|
883 asm("stmia r0!, {r2,r3} "); // |
|
884 #ifdef __VFP_V3 |
|
885 VFP_FSTMIADW(CC_AL,0,0,16); // save D0 - D15 |
|
886 VFP_FMRX(,3,VFP_XREG_MVFR0); |
|
887 asm("tst r3, #%a0" : : "i" ((TInt)VFP_MVFR0_ASIMD32)); // check to see if all 32 Advanced SIMD registers are present |
|
888 VFP_FSTMIADW(CC_NE,0,16,16); // if so then save D15 - D31 (don't need to check CPACR.D32DIS as it is cleared above) |
|
889 #else |
|
890 VFP_FMRX(,2,VFP_XREG_FPINST); |
|
891 VFP_FMRX(,3,VFP_XREG_FPINST2); |
|
892 asm("stmia r0!, {r2,r3} "); // FPINST, FPINST2 |
|
893 VFP_FSTMIADW(CC_AL,0,0,16); // save D0 - D15 |
|
894 #endif |
|
895 #endif // __CPU_HAS_VFP |
|
896 asm("1: "); |
|
897 asm("cmp r0, r1 "); |
|
898 asm("strlo r4, [r0], #4 "); // clear up to end of iMore[61] |
|
899 asm("blo 1b "); |
|
900 asm("mov r1, #%a0" : : "i" ((TInt)KMaxTInt)); |
|
901 asm("stmia r0!, {r1,r5-r7} "); // iExcCode=KMaxTInt, iCrashArgs[0...2]=0 |
|
902 asm("sub r0, r0, #1024 "); // r0 = &a |
|
903 #ifdef __CPU_HAS_VFP |
|
904 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iMore[0])); |
|
905 VFP_FMXR(,VFP_XREG_FPEXC,2); // restore FPEXC |
|
906 __DATA_SYNC_BARRIER__(r4); |
|
907 __INST_SYNC_BARRIER__(r4); |
|
908 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iA.iCPACR)); |
|
909 SET_CAR(,r2); // restore CPACR |
|
910 #endif |
|
911 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags)); |
|
912 asm("orr r1, r1, #0xC0 "); // interrupts off |
|
913 asm("msr cpsr, r1 "); // restore CPSR with interrupts off |
|
914 asm("ldmia r0, {r0-r11} "); // restore R4-R11 |
|
915 __JUMP(,lr); |
|
916 } |
|
917 |
|
918 |
|
919 /** Update the saved ARM registers with information from an exception |
|
920 |
|
921 @internalTechnology |
|
922 */ |
|
923 __NAKED__ void Arm::UpdateState(SFullArmRegSet&, TArmExcInfo&) |
|
924 { |
|
925 asm("ldr r2, [r1, #%a0]" : : "i" _FOFF(TArmExcInfo, iExcCode)); |
|
926 asm("cmp r2, #%a0 " : : "i" ((TInt)EArmExceptionPrefetchAbort)); |
|
927 asm("ldmia r1!, {r2,r3,r12} "); |
|
928 asm("streq r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFAR)); |
|
929 asm("strne r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFAR)); |
|
930 asm("streq r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFSR)); |
|
931 asm("strne r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFSR)); |
|
932 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iSpsrSvc)); |
|
933 asm("add r1, r1, #4 "); |
|
934 asm("ldmia r1!, {r2,r3,r12} "); |
|
935 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13Svc)); |
|
936 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14Svc)); |
|
937 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR0)); |
|
938 asm("ldmia r1!, {r2,r3,r12} "); |
|
939 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR1)); |
|
940 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR2)); |
|
941 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR3)); |
|
942 asm("ldmia r1!, {r2,r3,r12} "); |
|
943 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR4)); |
|
944 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR5)); |
|
945 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR6)); |
|
946 asm("ldmia r1!, {r2,r3,r12} "); |
|
947 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR7)); |
|
948 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR8)); |
|
949 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR9)); |
|
950 asm("ldmia r1!, {r2,r3,r12} "); |
|
951 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR10)); |
|
952 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR11)); |
|
953 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR12)); |
|
954 asm("ldmia r1!, {r2,r3,r12} "); |
|
955 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13)); |
|
956 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14)); |
|
957 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iExcCode)); |
|
958 asm("ldmia r1!, {r2,r3} "); |
|
959 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR15)); |
|
960 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags)); |
|
961 __JUMP(,lr); |
|
962 } |
|
963 |
|
964 |
|
965 /** Get a pointer to a stored integer register, accounting for registers which |
|
966 are banked across modes. |
|
967 |
|
968 @param a Pointer to saved register block |
|
969 @param aRegNum Number of register required, 0-15 or -1 (indicates SPSR) |
|
970 @param aMode Bottom 5 bits indicate which processor mode |
|
971 Other bits of aMode are ignored |
|
972 @return Pointer to the required saved register value |
|
973 |
|
974 @internalTechnology |
|
975 */ |
|
976 __NAKED__ TArmReg* Arm::Reg(SFullArmRegSet& /*a*/, TInt /*aRegNum*/, TArmReg /*aMode*/) |
|
977 { |
|
978 asm("cmp r1, #8 "); // register number < 8 ? |
|
979 asm("addlo r0, r0, r1, lsl #2 "); // register R0-R7 are not banked |
|
980 asm("blo 0f "); |
|
981 asm("cmp r1, #15 "); // register number = 15 ? |
|
982 asm("addeq r0, r0, r1, lsl #2 "); // register R15 not banked |
|
983 asm("movgt r0, #0 "); // no registers > 15 |
|
984 asm("bge 0f "); |
|
985 asm("cmn r1, #1 "); |
|
986 asm("movlt r0, #0 "); // no registers < -1 |
|
987 asm("blt 0f "); |
|
988 asm("and r12, r2, #0x1F "); |
|
989 asm("cmp r12, #0x11 "); // mode_fiq? |
|
990 asm("beq 1f "); // skip if it is |
|
991 asm("cmp r1, #13 "); |
|
992 asm("addlo r0, r0, r1, lsl #2 "); // register R8-R12 are only banked in mode_fiq |
|
993 asm("blo 0f "); |
|
994 asm("cmp r12, #0x10 "); // mode_usr ? |
|
995 asm("cmpne r12, #0x1F "); // if not, mode_sys ? |
|
996 asm("bne 2f "); // skip if neither |
|
997 asm("cmp r1, #16 "); |
|
998 asm("addlo r0, r0, r1, lsl #2 "); // handle R13_usr, R14_usr |
|
999 asm("movhs r0, #0 "); // no SPSR in mode_usr or mode_sys |
|
1000 asm("blo 0f "); |
|
1001 asm("1: "); // mode_fiq, regnum = 8-12 |
|
1002 asm("2: "); // exception mode, regnum not 0-12 or 15 |
|
1003 asm("cmn r1, #1 "); // regnum = -1 ? |
|
1004 asm("moveq r1, #15 "); // if so, change to 15 |
|
1005 asm("sub r1, r1, #13 "); |
|
1006 asm("add r0, r0, r1, lsl #2 "); // add 0 for R13, 4 for R14, 8 for SPSR |
|
1007 asm("cmp r12, #0x16 "); |
|
1008 asm("addeq r0, r0, #12 "); // if mon, add offset from R13Fiq to R13Mon |
|
1009 asm("cmpne r12, #0x11 "); |
|
1010 asm("addeq r0, r0, #32 "); // if valid but not svc/abt/und/irq, add offset from R13Irq to R13Fiq |
|
1011 asm("cmpne r12, #0x12 "); |
|
1012 asm("addeq r0, r0, #12 "); // if valid but not svc/abt/und, add offset from R13Und to R13Irq |
|
1013 asm("cmpne r12, #0x1b "); |
|
1014 asm("addeq r0, r0, #12 "); // if valid but not svc/abt, add offset from R13Abt to R13Und |
|
1015 asm("cmpne r12, #0x17 "); |
|
1016 asm("addeq r0, r0, #12 "); // if valid but not svc, add offset from R13Svc to R13Abt |
|
1017 asm("cmpne r12, #0x13 "); |
|
1018 asm("addeq r0, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iN.iR13Svc)); // if valid mode add offset to R13Svc |
|
1019 asm("movne r0, #0 "); |
|
1020 asm("0: "); |
|
1021 __JUMP(,lr); |
|
1022 } |
|
1023 |
|
1024 |
|
1025 /** Restore all the ARM registers |
|
1026 |
|
1027 @internalTechnology |
|
1028 */ |
|
1029 __NAKED__ void Arm::RestoreState(SFullArmRegSet&) |
|
1030 { |
|
1031 } |
|
1032 |
|
1033 __NAKED__ EXPORT_C TBool BTrace::OutFilteredPcFormatBig(TUint32 a0, TUint32 aModuleUid, TUint32 aPc, TUint16 aFormatId, const TAny* aData, TInt aDataSize) |
|
1034 { |
|
1035 asm("mov r0, #0"); //Kernel side not implemented yet |
|
1036 } |
|
1037 |
|
1038 |
|
1039 |
|
1040 |
|
1041 |