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Adaptation/GUID-D2163920-D448-5BFC-B655-B654FD657A94.dita
author Graeme Price <GRAEME.PRICE@NOKIA.COM>
Fri, 15 Oct 2010 14:32:18 +0100
changeset 15 307f4279f433
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<?xml version="1.0" encoding="utf-8"?>
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<!-- Copyright (c) 2007-2010 Nokia Corporation and/or its subsidiary(-ies) All rights reserved. -->
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<!-- This component and the accompanying materials are made available under the terms of the License
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"Eclipse Public License v1.0" which accompanies this distribution,
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and is available at the URL "http://www.eclipse.org/legal/epl-v10.html". -->
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<!-- Initial Contributors:
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    Nokia Corporation - initial contribution.
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Contributors:
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-->
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<!DOCTYPE concept
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  PUBLIC "-//OASIS//DTD DITA Concept//EN" "concept.dtd">
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<concept id="GUID-D2163920-D448-5BFC-B655-B654FD657A94" xml:lang="en"><title>Level
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2 Cache</title><shortdesc>Level 2 cache is cache memory that is external to the microprocessor.
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The kernel provides functions to perform operations on this cache. </shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>
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<p>In general, the presence of Level 2 cache is transparent to device drivers.
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The cache is physically indexed and physically tagged, and this means that
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L2 cache is not affected by the remapping of virtual-to-physical addresses
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in the MMU. </p>
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<p>However, where data is being transferred using DMA, then cached information
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in the data buffers involved in a DMA transfer must be flushed before a DMA
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write operation, for example when transferring data from memory to a peripheral,
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and both before and after a DMA read operation, for example when transferring
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data from a peripheral into memory. </p>
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<p>The kernel provides three functions for this: </p>
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<ul>
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<li id="GUID-031134D4-1CF6-503F-9DBD-75836242A0BD"><p> <xref href="GUID-4425E698-EE8A-369B-92CD-09B1CBD2911F.dita#GUID-4425E698-EE8A-369B-92CD-09B1CBD2911F/GUID-5F08DEAA-1237-32DE-AE41-CE7B18230972"><apiname>Cache::SyncMemoryBeforeDmaWrite()</apiname></xref>  </p> </li>
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<li id="GUID-0E0BBB26-1F1C-5A64-A9D3-506B5D6783EA"><p> <xref href="GUID-4425E698-EE8A-369B-92CD-09B1CBD2911F.dita#GUID-4425E698-EE8A-369B-92CD-09B1CBD2911F/GUID-3FF3C567-C1BD-3D4E-97E1-B036456A374E"><apiname> Cache::SyncMemoryBeforeDmaRead()</apiname></xref>  </p> </li>
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<li id="GUID-DB3947C1-1BB7-5678-A337-48C74B903496"><p> <xref href="GUID-4425E698-EE8A-369B-92CD-09B1CBD2911F.dita#GUID-4425E698-EE8A-369B-92CD-09B1CBD2911F/GUID-78E6DE46-61F0-3840-B555-6926D21141BF"><apiname> Cache::SyncMemoryAfterDmaRead()</apiname></xref>  </p> </li>
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</ul>
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<p>All three functions are defined and implemented as part of the <xref href="GUID-4425E698-EE8A-369B-92CD-09B1CBD2911F.dita"><apiname>Cache</apiname></xref> class,
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defined in <filepath>...\e32\e32\include\kernel\cache.h.</filepath>  </p>
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<p>See also <xref href="GUID-18EFC99D-68B6-51E1-8520-272DC278E82A.dita#GUID-18EFC99D-68B6-51E1-8520-272DC278E82A/GUID-F9DA4E5B-5675-55D3-9793-0D8404FAA7B6"> DMA
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buffers</xref> in the <xref href="GUID-18EFC99D-68B6-51E1-8520-272DC278E82A.dita">Device
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Driver Tutorial</xref>. </p>
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</conbody></concept>
MCL/sftools/depl/docscontent