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<concept id="GUID-7ECDCF7B-3B2A-561F-9136-04BC4DAE46E4" xml:lang="en"><title>ARM
Exception Types, Fault Status Register Values, and Processor Mode Values</title><shortdesc>Reference for users of the debug monitor tool to ARM exception
types, fault status register values, and processor mode values. </shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>
<section id="GUID-567330BE-A308-50CD-9EB8-891E45FA8294"><title>ARM exception
types</title> <p>The numeric value in the left hand column is the value of
the <codeph>ExcId</codeph> field displayed as a result of entering an <xref href="GUID-08E14B34-5144-5AA8-AA55-7AF03671676C.dita#GUID-08E14B34-5144-5AA8-AA55-7AF03671676C/GUID-D5F2E0AF-EF03-5150-813B-DF989F12C47B">f</xref> command
in the debug monitor. </p> <table id="GUID-D87BD88D-734C-571F-A02F-039AB98B3906">
<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>
<tbody>
<row>
<entry><p> <codeph>00000000</codeph>  </p> </entry>
<entry><p>Prefetch abort </p> </entry>
</row>
<row>
<entry><p> <codeph>00000001</codeph>  </p> </entry>
<entry><p>Data abort </p> </entry>
</row>
<row>
<entry><p> <codeph>00000002</codeph>  </p> </entry>
<entry><p>Undefined instruction </p> </entry>
</row>
</tbody>
</tgroup>
</table> </section>
<section id="GUID-E55E7DA9-61DC-57D9-9678-05D490FEE604"><title>Fault status
register values (FSR register)</title> <p>The lowest 4-bits of the FSR register
indicates the fault generated by the MMU. The FSR register value is displayed
as a result of entering an <xref href="GUID-08E14B34-5144-5AA8-AA55-7AF03671676C.dita#GUID-08E14B34-5144-5AA8-AA55-7AF03671676C/GUID-D5F2E0AF-EF03-5150-813B-DF989F12C47B">f</xref> command
in the debug monitor. </p> <table id="GUID-502176DF-8084-5D06-8443-29D64B2BDC33">
<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>
<tbody>
<row>
<entry><p> <codeph>0</codeph>  </p> </entry>
<entry><p>Vector exception </p> </entry>
</row>
<row>
<entry><p> <codeph>1</codeph>  </p> </entry>
<entry><p>Alignment fault </p> </entry>
</row>
<row>
<entry><p> <codeph>2</codeph>  </p> </entry>
<entry><p>Terminal exception </p> </entry>
</row>
<row>
<entry><p> <codeph>3</codeph>  </p> </entry>
<entry><p>Alignment fault </p> </entry>
</row>
<row>
<entry><p> <codeph>4</codeph>  </p> </entry>
<entry><p>External abort on linefetch for section translation </p> </entry>
</row>
<row>
<entry><p> <codeph>5</codeph>  </p> </entry>
<entry><p>Section translation fault (unmapped virtual address) </p> </entry>
</row>
<row>
<entry><p> <codeph>6</codeph>  </p> </entry>
<entry><p>External abort on linefetch for page translation </p> </entry>
</row>
<row>
<entry><p> <codeph>7</codeph>  </p> </entry>
<entry><p>Page translation fault (unmapped virtual address) </p> </entry>
</row>
<row>
<entry><p> <codeph>8</codeph>  </p> </entry>
<entry><p>External abort on non-linefetch for section translation </p> </entry>
</row>
<row>
<entry><p> <codeph>9</codeph>  </p> </entry>
<entry><p>Domain fault on section translation (i.e. accessing invalid domain) </p> </entry>
</row>
<row>
<entry><p> <codeph>A</codeph>  </p> </entry>
<entry><p>External abort on non-linefetch for page translation </p> </entry>
</row>
<row>
<entry><p> <codeph>B</codeph>  </p> </entry>
<entry><p>Domain fault on page translation (i.e. accessing invalid domain) </p> </entry>
</row>
<row>
<entry><p> <codeph>C</codeph>  </p> </entry>
<entry><p>External abort on first level translation </p> </entry>
</row>
<row>
<entry><p> <codeph>D</codeph>  </p> </entry>
<entry><p>Permission fault on section (i.e. no permission to access virtual
address) </p> </entry>
</row>
<row>
<entry><p> <codeph>E</codeph>  </p> </entry>
<entry><p>External abort on second level translation </p> </entry>
</row>
<row>
<entry><p> <codeph>F</codeph>  </p> </entry>
<entry><p>Permission fault on page (i.e. no permission to access virtual address) </p> </entry>
</row>
</tbody>
</tgroup>
</table> </section>
<section id="GUID-BFA2235C-1598-59E6-9F1F-A8281F13A957"><title>ARM processor
modes (CPSR register)</title> <p>The 5 least-significant bits of the CPSR
register indicate the ARM processor mode. The CPSR register value is displayed
as a result of entering an <xref href="GUID-08E14B34-5144-5AA8-AA55-7AF03671676C.dita#GUID-08E14B34-5144-5AA8-AA55-7AF03671676C/GUID-D5F2E0AF-EF03-5150-813B-DF989F12C47B">f</xref> command
in the debug monitor. </p> <table id="GUID-6B7CF34F-384D-52BF-9C72-C4D8E8B42633">
<tgroup cols="3"><colspec colname="col0"/><colspec colname="col1"/><colspec colname="col2"/>
<tbody>
<row>
<entry><p> <b>CPSR[4:0]</b>  </p> </entry>
<entry><p> <b>Mode</b>  </p> </entry>
<entry><p> <b>Register set</b>  </p> </entry>
</row>
<row>
<entry><p>10000 </p> </entry>
<entry><p>User </p> </entry>
<entry><p>PC, R14..R0, CPSR </p> </entry>
</row>
<row>
<entry><p>10001 </p> </entry>
<entry><p>FIQ </p> </entry>
<entry><p>PC, R14_fiq..R8_fiq, R7-R0, CPSR, SPSR_fiq </p> </entry>
</row>
<row>
<entry><p>10010 </p> </entry>
<entry><p>IRQ </p> </entry>
<entry><p>PC, R14_irq, R13_irq, R12-R0, CPSR, SPSR_irq </p> </entry>
</row>
<row>
<entry><p>10011 </p> </entry>
<entry><p>SVC </p> </entry>
<entry><p>PC, R14_svc, R13_svc, R12-R0, CPSR, SPSR_sv </p> </entry>
</row>
<row>
<entry><p>10111 </p> </entry>
<entry><p>Abort </p> </entry>
<entry><p>PC, R14_abt, R13_abt, R12-R0, CPSR, SPSR_abt </p> </entry>
</row>
<row>
<entry><p>11011 </p> </entry>
<entry><p>Undef </p> </entry>
<entry><p>PC, R14_und, R13_und, R12-R0, CPSR, SPSR_und </p> </entry>
</row>
<row>
<entry><p>11111 </p> </entry>
<entry><p>System </p> </entry>
<entry><p>PC, R14..R0, CPSR </p> </entry>
</row>
</tbody>
</tgroup>
</table> </section>
</conbody></concept>