Adaptation/GUID-7ECDCF7B-3B2A-561F-9136-04BC4DAE46E4.dita
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     1 <?xml version="1.0" encoding="utf-8"?>
       
     2 <!-- Copyright (c) 2007-2010 Nokia Corporation and/or its subsidiary(-ies) All rights reserved. -->
       
     3 <!-- This component and the accompanying materials are made available under the terms of the License 
       
     4 "Eclipse Public License v1.0" which accompanies this distribution, 
       
     5 and is available at the URL "http://www.eclipse.org/legal/epl-v10.html". -->
       
     6 <!-- Initial Contributors:
       
     7     Nokia Corporation - initial contribution.
       
     8 Contributors: 
       
     9 -->
       
    10 <!DOCTYPE concept
       
    11   PUBLIC "-//OASIS//DTD DITA Concept//EN" "concept.dtd">
       
    12 <concept id="GUID-7ECDCF7B-3B2A-561F-9136-04BC4DAE46E4" xml:lang="en"><title>ARM
       
    13 Exception Types, Fault Status Register Values, and Processor Mode Values</title><shortdesc>Reference for users of the debug monitor tool to ARM exception
       
    14 types, fault status register values, and processor mode values. </shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>
       
    15 <section id="GUID-567330BE-A308-50CD-9EB8-891E45FA8294"><title>ARM exception
       
    16 types</title> <p>The numeric value in the left hand column is the value of
       
    17 the <codeph>ExcId</codeph> field displayed as a result of entering an <xref href="GUID-08E14B34-5144-5AA8-AA55-7AF03671676C.dita#GUID-08E14B34-5144-5AA8-AA55-7AF03671676C/GUID-D5F2E0AF-EF03-5150-813B-DF989F12C47B">f</xref> command
       
    18 in the debug monitor. </p> <table id="GUID-D87BD88D-734C-571F-A02F-039AB98B3906">
       
    19 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>
       
    20 <tbody>
       
    21 <row>
       
    22 <entry><p> <codeph>00000000</codeph>  </p> </entry>
       
    23 <entry><p>Prefetch abort </p> </entry>
       
    24 </row>
       
    25 <row>
       
    26 <entry><p> <codeph>00000001</codeph>  </p> </entry>
       
    27 <entry><p>Data abort </p> </entry>
       
    28 </row>
       
    29 <row>
       
    30 <entry><p> <codeph>00000002</codeph>  </p> </entry>
       
    31 <entry><p>Undefined instruction </p> </entry>
       
    32 </row>
       
    33 </tbody>
       
    34 </tgroup>
       
    35 </table> </section>
       
    36 <section id="GUID-E55E7DA9-61DC-57D9-9678-05D490FEE604"><title>Fault status
       
    37 register values (FSR register)</title> <p>The lowest 4-bits of the FSR register
       
    38 indicates the fault generated by the MMU. The FSR register value is displayed
       
    39 as a result of entering an <xref href="GUID-08E14B34-5144-5AA8-AA55-7AF03671676C.dita#GUID-08E14B34-5144-5AA8-AA55-7AF03671676C/GUID-D5F2E0AF-EF03-5150-813B-DF989F12C47B">f</xref> command
       
    40 in the debug monitor. </p> <table id="GUID-502176DF-8084-5D06-8443-29D64B2BDC33">
       
    41 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>
       
    42 <tbody>
       
    43 <row>
       
    44 <entry><p> <codeph>0</codeph>  </p> </entry>
       
    45 <entry><p>Vector exception </p> </entry>
       
    46 </row>
       
    47 <row>
       
    48 <entry><p> <codeph>1</codeph>  </p> </entry>
       
    49 <entry><p>Alignment fault </p> </entry>
       
    50 </row>
       
    51 <row>
       
    52 <entry><p> <codeph>2</codeph>  </p> </entry>
       
    53 <entry><p>Terminal exception </p> </entry>
       
    54 </row>
       
    55 <row>
       
    56 <entry><p> <codeph>3</codeph>  </p> </entry>
       
    57 <entry><p>Alignment fault </p> </entry>
       
    58 </row>
       
    59 <row>
       
    60 <entry><p> <codeph>4</codeph>  </p> </entry>
       
    61 <entry><p>External abort on linefetch for section translation </p> </entry>
       
    62 </row>
       
    63 <row>
       
    64 <entry><p> <codeph>5</codeph>  </p> </entry>
       
    65 <entry><p>Section translation fault (unmapped virtual address) </p> </entry>
       
    66 </row>
       
    67 <row>
       
    68 <entry><p> <codeph>6</codeph>  </p> </entry>
       
    69 <entry><p>External abort on linefetch for page translation </p> </entry>
       
    70 </row>
       
    71 <row>
       
    72 <entry><p> <codeph>7</codeph>  </p> </entry>
       
    73 <entry><p>Page translation fault (unmapped virtual address) </p> </entry>
       
    74 </row>
       
    75 <row>
       
    76 <entry><p> <codeph>8</codeph>  </p> </entry>
       
    77 <entry><p>External abort on non-linefetch for section translation </p> </entry>
       
    78 </row>
       
    79 <row>
       
    80 <entry><p> <codeph>9</codeph>  </p> </entry>
       
    81 <entry><p>Domain fault on section translation (i.e. accessing invalid domain) </p> </entry>
       
    82 </row>
       
    83 <row>
       
    84 <entry><p> <codeph>A</codeph>  </p> </entry>
       
    85 <entry><p>External abort on non-linefetch for page translation </p> </entry>
       
    86 </row>
       
    87 <row>
       
    88 <entry><p> <codeph>B</codeph>  </p> </entry>
       
    89 <entry><p>Domain fault on page translation (i.e. accessing invalid domain) </p> </entry>
       
    90 </row>
       
    91 <row>
       
    92 <entry><p> <codeph>C</codeph>  </p> </entry>
       
    93 <entry><p>External abort on first level translation </p> </entry>
       
    94 </row>
       
    95 <row>
       
    96 <entry><p> <codeph>D</codeph>  </p> </entry>
       
    97 <entry><p>Permission fault on section (i.e. no permission to access virtual
       
    98 address) </p> </entry>
       
    99 </row>
       
   100 <row>
       
   101 <entry><p> <codeph>E</codeph>  </p> </entry>
       
   102 <entry><p>External abort on second level translation </p> </entry>
       
   103 </row>
       
   104 <row>
       
   105 <entry><p> <codeph>F</codeph>  </p> </entry>
       
   106 <entry><p>Permission fault on page (i.e. no permission to access virtual address) </p> </entry>
       
   107 </row>
       
   108 </tbody>
       
   109 </tgroup>
       
   110 </table> </section>
       
   111 <section id="GUID-BFA2235C-1598-59E6-9F1F-A8281F13A957"><title>ARM processor
       
   112 modes (CPSR register)</title> <p>The 5 least-significant bits of the CPSR
       
   113 register indicate the ARM processor mode. The CPSR register value is displayed
       
   114 as a result of entering an <xref href="GUID-08E14B34-5144-5AA8-AA55-7AF03671676C.dita#GUID-08E14B34-5144-5AA8-AA55-7AF03671676C/GUID-D5F2E0AF-EF03-5150-813B-DF989F12C47B">f</xref> command
       
   115 in the debug monitor. </p> <table id="GUID-6B7CF34F-384D-52BF-9C72-C4D8E8B42633">
       
   116 <tgroup cols="3"><colspec colname="col0"/><colspec colname="col1"/><colspec colname="col2"/>
       
   117 <tbody>
       
   118 <row>
       
   119 <entry><p> <b>CPSR[4:0]</b>  </p> </entry>
       
   120 <entry><p> <b>Mode</b>  </p> </entry>
       
   121 <entry><p> <b>Register set</b>  </p> </entry>
       
   122 </row>
       
   123 <row>
       
   124 <entry><p>10000 </p> </entry>
       
   125 <entry><p>User </p> </entry>
       
   126 <entry><p>PC, R14..R0, CPSR </p> </entry>
       
   127 </row>
       
   128 <row>
       
   129 <entry><p>10001 </p> </entry>
       
   130 <entry><p>FIQ </p> </entry>
       
   131 <entry><p>PC, R14_fiq..R8_fiq, R7-R0, CPSR, SPSR_fiq </p> </entry>
       
   132 </row>
       
   133 <row>
       
   134 <entry><p>10010 </p> </entry>
       
   135 <entry><p>IRQ </p> </entry>
       
   136 <entry><p>PC, R14_irq, R13_irq, R12-R0, CPSR, SPSR_irq </p> </entry>
       
   137 </row>
       
   138 <row>
       
   139 <entry><p>10011 </p> </entry>
       
   140 <entry><p>SVC </p> </entry>
       
   141 <entry><p>PC, R14_svc, R13_svc, R12-R0, CPSR, SPSR_sv </p> </entry>
       
   142 </row>
       
   143 <row>
       
   144 <entry><p>10111 </p> </entry>
       
   145 <entry><p>Abort </p> </entry>
       
   146 <entry><p>PC, R14_abt, R13_abt, R12-R0, CPSR, SPSR_abt </p> </entry>
       
   147 </row>
       
   148 <row>
       
   149 <entry><p>11011 </p> </entry>
       
   150 <entry><p>Undef </p> </entry>
       
   151 <entry><p>PC, R14_und, R13_und, R12-R0, CPSR, SPSR_und </p> </entry>
       
   152 </row>
       
   153 <row>
       
   154 <entry><p>11111 </p> </entry>
       
   155 <entry><p>System </p> </entry>
       
   156 <entry><p>PC, R14..R0, CPSR </p> </entry>
       
   157 </row>
       
   158 </tbody>
       
   159 </tgroup>
       
   160 </table> </section>
       
   161 </conbody></concept>