author | Lukasz Forynski <lukasz.forynski@gmail.com> |
Mon, 23 Aug 2010 02:29:41 +0100 | |
changeset 51 | 254b9435d75e |
parent 22 | b7e488c49d0d |
child 84 | 09e266454dcf |
permissions | -rwxr-xr-x |
0 | 1 |
; Copyright (c) 2003-2009 Nokia Corporation and/or its subsidiary(-ies). |
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; All rights reserved. |
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; This component and the accompanying materials are made available |
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; under the terms of the License "Eclipse Public License v1.0" |
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; which accompanies this distribution, and is available |
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; at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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; |
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; Initial Contributors: |
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; Nokia Corporation - initial contribution. |
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; |
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; Contributors: |
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; |
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; Description: |
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; omap3530/beagleboard/bootstrap/beagle.s |
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; Template for platform specific boot code |
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; |
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GBLL __VARIANT_S__ ; indicates that this is platform-specific code |
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GBLL __BEAGLEBOARD_S__ ; indicates which source file this is |
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INCLUDE bootcpu.inc |
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; |
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;******************************************************************************* |
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; |
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; Platform specific constant definitions |
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b7e488c49d0d
Increasing default RAM size to 256 mb and fixing the superfile overlap issue for UI images
arunabha
parents:
0
diff
changeset
|
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DRamBankBase EQU 0x80000000 ; 256M of DRAM |
b7e488c49d0d
Increasing default RAM size to 256 mb and fixing the superfile overlap issue for UI images
arunabha
parents:
0
diff
changeset
|
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DRamBankMaxSize EQU 0x10000000 |
0 | 30 |
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; HW used by bootstrap |
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Serial0PhysBase EQU 0x4806A000 |
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Serial1PhysBase EQU 0x4806C000 |
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Serial2PhysBase EQU 0x49020000 |
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PrimaryIOBase EQU 0xC6000000 ; c.f. KPrimaryIOBase in mmboot.h |
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Serial0LinBase EQU PrimaryIOBase + 0x0006A000 |
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Serial1LinBase EQU PrimaryIOBase + 0x0006C000 |
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Serial2LinBase EQU PrimaryIOBase + 0x00420000 |
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22
b7e488c49d0d
Increasing default RAM size to 256 mb and fixing the superfile overlap issue for UI images
arunabha
parents:
0
diff
changeset
|
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SuperPageAddr EQU 0x8c000000 ; boot stack goes just after this |
0 | 41 |
TheHwvd EQU 0x09080001 ; this is arbitary 0908 are CPU and ASSP 01 is variant |
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22
b7e488c49d0d
Increasing default RAM size to 256 mb and fixing the superfile overlap issue for UI images
arunabha
parents:
0
diff
changeset
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0 | 44 |
; |
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;******************************************************************************* |
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; |
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AREA |Boot$$Code|, CODE, READONLY, ALIGN=6 |
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; |
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;******************************************************************************* |
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; |
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;******************************************************************************* |
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; Initialise Hardware |
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; Initialise CPU registers |
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; Determine the hardware configuration |
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; Determine the reset reason. If it is wakeup from a low power mode, perform |
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; whatever reentry sequence is required and jump back to the kernel. |
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; Set up the memory controller so that at least some RAM is available |
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; Set R10 to point to the super page or to a temporary version of the super page |
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; with at least the following fields valid: |
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; iBootTable, iCodeBase, iActiveVariant, iCpuId |
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; In debug builds initialise the debug serial port |
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; |
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; Enter with: |
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; R12 points to TRomHeader |
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; NO STACK |
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; R14 = return address (as usual) |
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; |
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; All registers may be modified by this call |
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;******************************************************************************* |
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IF CFG_BootLoader |
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; For bootloader we only get here on a full reset |
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; Other resets will simply jump back into the previously-loaded image |
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EXPORT DoInitialiseHardware |
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DoInitialiseHardware ROUT |
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ELSE |
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EXPORT InitialiseHardware |
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InitialiseHardware ROUT |
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ENDIF |
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MOV r13, lr ; save return address |
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ADRL r1, ParameterTable ; pass address of parameter table |
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BL InitCpu ; initialise CPU/MMU registers |
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; Put your hardware initialising code here |
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IF CFG_DebugBootRom |
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BL InitDebugPort |
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ENDIF |
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; Set up the required super page values |
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LDR r10, =SuperPageAddr ; initial super page |
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LDR r0, =TheHwvd ; variant code |
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STR r0, [r10, #SSuperPageBase_iActiveVariant] |
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STR r0, [r10, #SSuperPageBase_iHwStartupReason] ; reset reason (from hardware) |
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ADD r1, r10, #CpuPageOffset |
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STR r1, [r10, #SSuperPageBase_iMachineData] |
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ADRL r0, BootTable |
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STR r0, [r10, #SSuperPageBase_iBootTable] ; Set the boot function table |
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STR r12, [r10, #SSuperPageBase_iCodeBase] ; Set the base address of bootstrap code |
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MRC p15, 0, r0, c0, c0, 0 ; read CPU ID from CP15 (remove if no CP15) |
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STR r0, [r10, #SSuperPageBase_iCpuId] |
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MOV pc, r13 ; return |
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;******************************************************************************* |
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; Notify an unrecoverable error during the boot process |
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; |
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; Enter with: |
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; R14 = address at which fault detected |
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; |
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; Don't return |
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;******************************************************************************* |
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EXPORT Fault |
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Fault ROUT |
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B BasicFaultHandler ; generic handler dumps registers via debug |
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; serial port |
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;******************************************************************************* |
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; Reboot the system |
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; |
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; Enter with: |
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; R0 = reboot reason code |
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; |
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; Don't return (of course) |
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;******************************************************************************* |
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ALIGN 32, 0 |
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EXPORT RestartEntry |
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RestartEntry ROUT |
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; save R0 parameter in HW dependent register which is preserved over reset |
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; put HW specific code here to reset system |
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SUB pc, pc, #8 |
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;******************************************************************************* |
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; Get a pointer to the list of RAM banks |
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; |
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; The pointer returned should point to a list of {BASE; MAXSIZE;} pairs, where |
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; BASE is the physical base address of the bank and MAXSIZE is the maximum |
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; amount of RAM which may be present in that bank. MAXSIZE should be a power of |
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; 2 and BASE should be a multiple of MAXSIZE. The generic code will examine the |
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; specified range of addresses and determine the actual amount of RAM if any |
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; present in the bank. The list is terminated by an entry with zero size. |
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; |
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; The pointer returned will usually be to constant data, but could equally well |
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; point to RAM if dynamic determination of the list is required. |
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; |
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; Enter with : |
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; R10 points to super page |
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; R12 points to ROM header |
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; R13 points to valid stack |
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; |
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; Leave with : |
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; R0 = pointer |
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; Nothing else modified |
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;******************************************************************************* |
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GetRamBanks ROUT |
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ADR r0, %FT1 |
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MOV pc, lr |
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1 |
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; DRAM has been set-up by boot loader so no need to configure or probe |
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51
254b9435d75e
Fixed build warnings
Lukasz Forynski <lukasz.forynski@gmail.com>
parents:
22
diff
changeset
|
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DCD DRamBankBase :OR: RAM_VERBATIM, DRamBankMaxSize |
0 | 178 |
DCD 0,0 ; terminator |
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;******************************************************************************* |
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; Get a pointer to the list of ROM banks |
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; |
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; The pointer returned should point to a list of entries of SRomBank structures, |
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; usually declared with the ROM_BANK macro. |
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; The list is terminated by a zero size entry (four zero words) |
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; |
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; ROM_BANK PB, SIZE, LB, W, T, RS, SS |
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; PB = physical base address of bank |
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; SIZE = size of bank |
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; LB = linear base if override required - usually set this to 0 |
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; W = bus width (ROM_WIDTH_8, ROM_WIDTH_16, ROM_WIDTH_32) |
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; T = type (see TRomType enum in kernboot.h) |
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; RS = random speed |
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; SS = sequential speed |
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; |
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; Only PB, SIZE, LB are used by the rest of the bootstrap. |
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; The information given here can be modified by the SetupRomBank call, if |
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; dynamic detection and sizing of ROMs is required. |
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; |
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; Enter with : |
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; R10 points to super page |
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; R12 points to ROM header |
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; R13 points to valid stack |
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; |
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; Leave with : |
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; R0 = pointer |
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; Nothing else modified |
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;******************************************************************************* |
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GetRomBanks ROUT |
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ADR r0, %FT1 |
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MOV pc, lr |
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1 |
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DCD 0,0,0,0 ; terminator |
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219 |
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;******************************************************************************* |
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; Get a pointer to the list of hardware banks |
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; |
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; The pointer returned should point to a list of hardware banks declared with |
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; the HW_MAPPING and/or HW_MAPPING_EXT macros. A zero word terminates the list. |
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; For the direct memory model, all hardware on the system should be mapped here |
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; and the mapping will set linear address = physical address. |
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; For the moving or multiple model, only the hardware required to boot the kernel |
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; and do debug tracing needs to be mapped here. The linear addresses used will |
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; start at KPrimaryIOBase and step up as required with the order of banks in |
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; the list being maintained in the linear addresses used. |
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; |
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; HW_MAPPING PB, SIZE, MULT |
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; This declares a block of I/O with physical base PB and address range SIZE |
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; blocks each of which has a size determined by MULT. The page size used for |
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; the mapping is determined by MULT. The linear address base of the mapping |
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; will be the next free linear address rounded up to the size specified by |
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; MULT. |
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; The permissions used for the mapping are the standard I/O permissions (BTP_Hw). |
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; |
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; HW_MAPPING_EXT PB, SIZE, MULT |
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; This declares a block of I/O with physical base PB and address range SIZE |
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; blocks each of which has a size determined by MULT. The page size used for |
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; the mapping is determined by MULT. The linear address base of the mapping |
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; will be the next free linear address rounded up to the size specified by |
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; MULT. |
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; The permissions used for the mapping are determined by a BTP_ENTRY macro |
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; immediately following this macro in the HW bank list or by a DCD directive |
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; specifying a different standard permission type. |
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; |
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; HW_MAPPING_EXT2 PB, SIZE, MULT, LIN |
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; This declares a block of I/O with physical base PB and address range SIZE |
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; blocks each of which has a size determined by MULT. The page size used for |
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; the mapping is determined by MULT. The linear address base of the mapping |
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; is specified by the LIN parameter. |
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; The permissions used for the mapping are the standard I/O permissions (BTP_Hw). |
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; |
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; HW_MAPPING_EXT3 PB, SIZE, MULT, LIN |
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; This declares a block of I/O with physical base PB and address range SIZE |
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; blocks each of which has a size determined by MULT. The page size used for |
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; the mapping is determined by MULT. The linear address base of the mapping |
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; is specified by the LIN parameter. |
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; The permissions used for the mapping are determined by a BTP_ENTRY macro |
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; immediately following this macro in the HW bank list or by a DCD directive |
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; specifying a different standard permission type. |
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; |
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; Configurations without an MMU need not implement this function. |
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; |
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; Enter with : |
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; R10 points to super page |
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; R12 points to ROM header |
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; R13 points to valid stack |
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; |
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; Leave with : |
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; R0 = pointer |
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; Nothing else modified |
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;******************************************************************************* |
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GetHwBanks ROUT |
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ADR r0, %FT1 |
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MOV pc, lr |
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1 |
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HW_MAPPING 0x48000000, 4, HW_MULT_1M ; L4-Core KPrimaryIOBase |
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HW_MAPPING 0x49000000, 1, HW_MULT_1M ; L4-Per KPrimaryIOBase + 0x00400000 |
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HW_MAPPING 0x50000000, 1, HW_MULT_64K ; SGX Graphic accelerator slave port KPrimaryIOBase + 0x00500000 |
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HW_MAPPING 0x54000000, 8, HW_MULT_1M ; L4-Emu KPrimaryIOBase + 0x00600000 |
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HW_MAPPING 0x68000000, 1, HW_MULT_1M ; L3 Control Registers KPrimaryIOBase + 0x00E00000 |
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HW_MAPPING 0x6E000000, 1, HW_MULT_1M ; GPMC registers KPrimaryIOBase + 0x00F00000 |
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; HW_MAPPING 0x5C000000, 48, HW_MULT_1M ; IVA2.2 SS KPrimaryIOBase + 0x01910000 |
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; HW_MAPPING 0x70000000,128, HW_MULT_1M ; SDRC-SMS virtual address space 0 KPrimaryIOBase + 0x08910000 |
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; HW_MAPPING 0x78000000,128, HW_MULT_1M ; Continued |
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DCD 0 ; terminator |
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;******************************************************************************* |
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; Set up RAM bank |
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; |
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; Do any additional RAM controller initialisation for each RAM bank which wasn't |
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; done by InitialiseHardware. |
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; Called twice for each RAM bank :- |
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; First with R3 = 0xFFFFFFFF before bank has been probed |
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; Then, if RAM is present, with R3 indicating validity of each byte lane, ie |
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; R3 bit 0=1 if D0-7 are valid, bit1=1 if D8-15 are valid etc. |
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; For each call R1 specifies the bank physical base address. |
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; |
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; Enter with : |
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; R10 points to super page |
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; R12 points to ROM header |
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; R13 points to stack |
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; R1 = physical base address of bank |
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; R3 = width (bottom 4 bits indicate validity of byte lanes) |
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; 0xffffffff = preliminary initialise |
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; |
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; Leave with : |
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; No registers modified |
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;******************************************************************************* |
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SetupRamBank ROUT |
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MOV pc, lr |
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321 |
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322 |
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323 |
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324 |
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325 |
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;******************************************************************************* |
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; Set up ROM bank |
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328 |
; |
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; Do any required autodetection and autosizing of ROMs and any additional memory |
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; controller initialisation for each ROM bank which wasn't done by |
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; InitialiseHardware. |
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; |
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; The first time this function is called R11=0 and R0 points to the list of |
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; ROM banks returned by the BTF_RomBanks call. This allows any preliminary setup |
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; before autodetection begins. |
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; |
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; This function is subsequently called once for each ROM bank with R11 pointing |
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; to the current information held about that ROM bank (SRomBank structure). |
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; The structure pointed to by R11 should be updated with the size and width |
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; determined. The size should be set to zero if there is no ROM present in the |
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; bank. |
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342 |
; |
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; Enter with : |
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344 |
; R10 points to super page |
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; R12 points to ROM header |
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; R13 points to stack |
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; R11 points to SRomBank info for this bank |
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; R11 = 0 for preliminary initialise (all banks) |
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; |
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350 |
; Leave with : |
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; Update SRomBank info with detected size/width |
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; Set the size field to 0 if the ROM bank is absent |
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; Can modify R0-R4 but not other registers |
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; |
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;******************************************************************************* |
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356 |
SetupRomBank ROUT |
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357 |
MOV pc, lr |
|
358 |
||
359 |
||
360 |
||
361 |
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362 |
||
363 |
;******************************************************************************* |
|
364 |
; Reserve physical memory |
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365 |
; |
|
366 |
; Reserve any physical RAM needed for platform-specific purposes before the |
|
367 |
; bootstrap begins allocating RAM for page tables/kernel data etc. |
|
368 |
; |
|
369 |
; There are two methods for this: |
|
370 |
; 1. The function ExciseRamArea may be used. This will remove a contiguous |
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371 |
; region of physical RAM from the RAM bank list. That region will never |
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; again be identified as RAM. |
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373 |
; 2. A list of excluded physical address ranges may be written at [R11]. |
|
374 |
; This should be a list of (base,size) pairs terminated by a (0,0) entry. |
|
375 |
; This RAM will still be identified as RAM by the kernel but will not |
|
376 |
; be allocated by the bootstrap and will subsequently be marked as |
|
377 |
; allocated by the kernel immediately after boot. |
|
378 |
; |
|
379 |
; Enter with : |
|
380 |
; R10 points to super page |
|
381 |
; R11 indicates where preallocated RAM list should be written. |
|
382 |
; R12 points to ROM header |
|
383 |
; R13 points to stack |
|
384 |
; |
|
385 |
; Leave with : |
|
386 |
; R0-R3 may be modified. Other registers should be preserved. |
|
387 |
;******************************************************************************* |
|
388 |
ReservePhysicalMemory ROUT |
|
389 |
MOV pc, lr |
|
390 |
||
391 |
||
392 |
||
393 |
||
394 |
||
395 |
;******************************************************************************* |
|
396 |
; Return parameter specified by R0 (see TBootParam enum) |
|
397 |
; |
|
398 |
; Enter with : |
|
399 |
; R0 = parameter number |
|
400 |
; |
|
401 |
; Leave with : |
|
402 |
; If parameter value is supplied, R0 = value and N flag clear |
|
403 |
; If parameter value is not supplied, N flag set. In this case the |
|
404 |
; parameter may be defaulted or the system may fault. |
|
405 |
; R0,R1,R2 modified. No other registers modified. |
|
406 |
; |
|
407 |
;******************************************************************************* |
|
408 |
GetParameters ROUT |
|
409 |
ADR r1, ParameterTable |
|
410 |
B FindParameter |
|
411 |
ParameterTable |
|
412 |
; Include any parameters specified in TBootParam enum here |
|
413 |
; if you want to override them. |
|
414 |
DCD BPR_UncachedLin, 0 ; parameter number, parameter value |
|
415 |
IF :DEF: CFG_CPU_ARM1136 :LAND: (:LNOT: :DEF: CFG_CPU_ARM1136_ERRATUM_364296_FIXED) |
|
416 |
DCD BPR_FinalMMUCRSet, ExtraMMUCR + MMUCR_FI |
|
417 |
DCD BPR_AuxCRSet, DefaultAuxCRSet + 0x80000000 |
|
418 |
ENDIF |
|
419 |
DCD -1 ; terminator |
|
420 |
||
421 |
||
422 |
||
423 |
||
424 |
||
425 |
;******************************************************************************* |
|
426 |
; Do final platform-specific initialisation before booting the kernel |
|
427 |
; |
|
428 |
; Typical uses for this call would be: |
|
429 |
; 1. Mapping cache flushing areas |
|
430 |
; 2. Setting up pointers to routines in the bootstrap which are used by |
|
431 |
; the variant or drivers (eg idle code). |
|
432 |
; |
|
433 |
; Enter with : |
|
434 |
; R10 points to super page |
|
435 |
; R11 points to TRomImageHeader for the kernel |
|
436 |
; R12 points to ROM header |
|
437 |
; R13 points to stack |
|
438 |
; |
|
439 |
; Leave with : |
|
440 |
; R0-R9 may be modified. Other registers should be preserved. |
|
441 |
; |
|
442 |
;******************************************************************************* |
|
443 |
FinalInitialise ROUT |
|
444 |
STMFD sp!, {lr} |
|
445 |
LDMFD sp!, {pc} |
|
446 |
||
447 |
||
448 |
||
449 |
||
450 |
KHwUartSsr EQU 0x44 ; Supplementary status register |
|
451 |
KTxFifoFullMask EQU 0x01 |
|
452 |
KHwUartThr EQU 0x00 ; Transmit holding register |
|
453 |
||
454 |
KHwUartSysC EQU 0x54 ; System configuration register |
|
455 |
KSoftResetMask EQU 0x02 |
|
456 |
KHwUartLcr EQU 0x0C ; Line control register |
|
457 |
KConfigurationModeB EQU 0xBF |
|
458 |
KConfigurationModeA EQU 0x80 |
|
459 |
KOperationMode EQU 0x00 |
|
460 |
K8BitsNoParity1Stop EQU 0x03 |
|
461 |
KHwUartEfr EQU 0x08 ; Enhanced feature register |
|
462 |
KEnhancedEnMask EQU 0x10 |
|
463 |
KHwUartMcr EQU 0x10 |
|
464 |
KTcrTlr EQU 0x40 |
|
465 |
KHwUartFcr EQU 0x08 |
|
466 |
KFifoConfiguration EQU 0x01 ; 8 deep Rx, 8 deep Tx, FIFO Enable |
|
467 |
KHwUartDll EQU 0x00 ; Divisor latch low |
|
468 |
K115k2L EQU 0x1A |
|
469 |
K230k4L EQU 0x0D |
|
470 |
K460k8L EQU 0x08 |
|
471 |
K921k6L EQU 0x04 |
|
472 |
KHwUartMdr1 EQU 0x20 ; Mode definition register 1 |
|
473 |
KUART16XMode EQU 0x00 |
|
474 |
||
475 |
;******************************************************************************* |
|
476 |
; Output a character to the debug port |
|
477 |
; |
|
478 |
; Enter with : |
|
479 |
; R0 = character to output |
|
480 |
; R13 points to valid stack |
|
481 |
; |
|
482 |
; Leave with : |
|
483 |
; nothing modified |
|
484 |
;******************************************************************************* |
|
485 |
DoWriteC ROUT |
|
486 |
IF CFG_DebugBootRom |
|
487 |
STMFD sp!, {r1,lr} |
|
488 |
BL GetDebugPortBase |
|
489 |
||
490 |
1 LDR lr, [r1, #KHwUartSsr] ; Check status |
|
491 |
TST lr, #KTxFifoFullMask ; If transmit data full, wait |
|
492 |
BNE %BT1 |
|
493 |
STR r0, [r1, #KHwUartThr] ; Store to data register |
|
494 |
||
495 |
LDMFD sp!, {r1,pc} |
|
496 |
ELSE |
|
497 |
MOV pc, lr |
|
498 |
ENDIF |
|
499 |
||
500 |
IF CFG_DebugBootRom |
|
501 |
||
502 |
;******************************************************************************* |
|
503 |
; Initialise the debug port |
|
504 |
; |
|
505 |
; Enter with : |
|
506 |
; R12 points to ROM header |
|
507 |
; There is no valid stack |
|
508 |
; |
|
509 |
; Leave with : |
|
510 |
; R0-R2 modified |
|
511 |
; Other registers unmodified |
|
512 |
;******************************************************************************* |
|
513 |
InitDebugPort ROUT ; Based on the OMAP3530TRM 17.5.1.1 Quick Start |
|
514 |
MOV r0, lr |
|
515 |
BL GetDebugPortBase ; r1 = base address of debug port |
|
516 |
MOV lr, r0 |
|
517 |
||
518 |
MOV r2, #KSoftResetMask |
|
519 |
STR r2, [r1, #KHwUartSysC] ; Perform a soft reset of the UART |
|
520 |
||
521 |
MOV r2, #KConfigurationModeB |
|
522 |
STR r2, [r1, #KHwUartLcr] ; UART to configuration mode B |
|
523 |
||
524 |
LDR r2, [r1, #KHwUartEfr] |
|
525 |
ORR r2, #KEnhancedEnMask |
|
526 |
STR r2, [r1, #KHwUartEfr] ; Enable the IER, FCR, MCR |
|
527 |
||
528 |
MOV r2, #KConfigurationModeA |
|
529 |
STR r2, [r1, #KHwUartLcr] ; UART to configuration mode A |
|
530 |
||
531 |
LDR r2, [r1, #KHwUartMcr] |
|
532 |
ORR r2, #KTcrTlr |
|
533 |
STR r2, [r1, #KHwUartMcr] ; Enable the TCR, TLR |
|
534 |
||
535 |
MOV r2, #KFifoConfiguration |
|
536 |
STR r2, [r1, #KHwUartFcr] ; FIFO |
|
537 |
||
538 |
MOV r2, #KConfigurationModeB |
|
539 |
STR r2, [r1, #KHwUartLcr] ; UART to configuration mode B |
|
540 |
||
541 |
LDR r2, [r1, #KHwUartEfr] |
|
542 |
AND r2, #~KEnhancedEnMask |
|
543 |
STR r2, [r1, #KHwUartEfr] ; Disable the IER, FCR, MCR |
|
544 |
||
545 |
MOV r2, #KConfigurationModeA |
|
546 |
STR r2, [r1, #KHwUartLcr] ; UART to configuration mode A |
|
547 |
||
548 |
LDR r2, [r1, #KHwUartMcr] |
|
549 |
AND r2, #~KTcrTlr |
|
550 |
STR r2, [r1, #KHwUartMcr] ; Disable the TCR, TLR |
|
551 |
||
552 |
MOV r2, #KOperationMode |
|
553 |
STR r2, [r1, #KHwUartLcr] ; UART to operation mode |
|
554 |
||
555 |
; 17.5.1.1.3 |
|
556 |
||
557 |
; MDR1[2:0] is 0x7(Disable) from reset |
|
558 |
||
559 |
MOV r2, #KConfigurationModeB |
|
560 |
STR r2, [r1, #KHwUartLcr] ; UART to configuration mode B |
|
561 |
||
562 |
LDR r2, [r1, #KHwUartEfr] |
|
563 |
ORR r2, #KEnhancedEnMask |
|
564 |
STR r2, [r1, #KHwUartEfr] ; Enable the IER, FCR, MCR |
|
565 |
||
566 |
; IER is clear from Reset |
|
567 |
||
568 |
MOV r2, #K115k2L |
|
569 |
STR r2, [r1, #KHwUartDll] ; Set baud rate |
|
570 |
; DLH is 00 from Reset |
|
571 |
||
572 |
; IER is clear from Reset |
|
573 |
||
574 |
MOV r2, #K8BitsNoParity1Stop |
|
575 |
STR r2, [r1, #KHwUartLcr] |
|
576 |
||
577 |
MOV r2, #KUART16XMode |
|
578 |
STR r2, [r1, #KHwUartMdr1] |
|
579 |
||
580 |
||
581 |
MOV r1, #0x19000 ; Set up delay loop to allow line to settle |
|
582 |
SUBS r1, r1, #1 |
|
583 |
SUBNE pc, pc, #12 |
|
584 |
||
585 |
MOV pc, lr |
|
586 |
||
587 |
;******************************************************************************* |
|
588 |
; Get the base address of the debug UART |
|
589 |
; |
|
590 |
; Enter with : |
|
591 |
; R12 points to ROM header |
|
592 |
; There may be no stack |
|
593 |
; |
|
594 |
; Leave with : |
|
595 |
; R1 = base address of port |
|
596 |
; No other registers modified |
|
597 |
;******************************************************************************* |
|
598 |
GetDebugPortBase ROUT |
|
599 |
LDR r1, [r12, #TRomHeader_iDebugPort] |
|
600 |
CMP r1, #42 ; JTAG? |
|
601 |
MOVEQS r1, #0 |
|
602 |
MOVEQ pc, lr ; yes - return 0 and set Z |
|
603 |
||
604 |
CMP r1, #2 |
|
605 |
BNE %FA1 ; skip if not port 2 |
|
606 |
GET_ADDRESS r1, Serial2PhysBase, Serial2LinBase |
|
607 |
MOVS r1, r1 ; clear Z |
|
608 |
MOV pc, lr |
|
609 |
1 |
|
610 |
CMP r1, #1 |
|
611 |
BNE %FA1 ; skip if not port 1 |
|
612 |
GET_ADDRESS r1, Serial1PhysBase, Serial1LinBase |
|
613 |
MOVS r1, r1 ; clear Z |
|
614 |
MOV pc, lr |
|
615 |
1 |
|
616 |
GET_ADDRESS r1, Serial0PhysBase, Serial0LinBase |
|
617 |
MOVS r1, r1 ; clear Z |
|
618 |
MOV pc, lr |
|
619 |
||
620 |
ENDIF ; CFG_DebugBootRom |
|
621 |
||
622 |
||
623 |
||
624 |
||
625 |
||
626 |
;******************************************************************************* |
|
627 |
; BOOT FUNCTION TABLE |
|
628 |
;******************************************************************************* |
|
629 |
||
630 |
BootTable |
|
631 |
DCD DoWriteC ; output a debug character |
|
632 |
DCD GetRamBanks ; get list of RAM banks |
|
633 |
DCD SetupRamBank ; set up a RAM bank |
|
634 |
DCD GetRomBanks ; get list of ROM banks |
|
635 |
DCD SetupRomBank ; set up a ROM bank |
|
636 |
DCD GetHwBanks ; get list of HW banks |
|
637 |
DCD ReservePhysicalMemory ; reserve physical RAM if required |
|
638 |
DCD GetParameters ; get platform dependent parameters |
|
639 |
DCD FinalInitialise ; Final initialisation before booting the kernel |
|
640 |
DCD HandleAllocRequest ; allocate memory |
|
641 |
DCD GetPdeValue ; usually in generic code |
|
642 |
DCD GetPteValue ; usually in generic code |
|
643 |
DCD PageTableUpdate ; usually in generic code |
|
644 |
DCD EnableMmu ; Enable the MMU (usually in generic code) |
|
645 |
||
646 |
; These entries specify the standard MMU permissions for various areas |
|
647 |
; They can be omitted if MMU is absent |
|
648 |
BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; ROM |
|
649 |
BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; kernel data/stack/heap |
|
650 |
BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; super page/CPU page |
|
651 |
BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page directory/tables |
|
652 |
BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; exception vectors |
|
653 |
BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; hardware registers |
|
654 |
DCD 0 ; unused (minicache flush) |
|
655 |
DCD 0 ; unused (maincache flush) |
|
656 |
BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page table info |
|
657 |
BTP_ENTRY CLIENT_DOMAIN, PERM_RWRW, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; user RAM |
|
658 |
BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_STRONGLY_ORDERED, 1, 1, 0, 0 ; temporary identity mapping |
|
659 |
BTP_ENTRY CLIENT_DOMAIN, UNC_PERM, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; uncached |
|
660 |
||
661 |
END |