1 /*

     2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

     3 * All rights reserved.

     4 * This component and the accompanying materials are made available

     5 * under the terms of "Eclipse Public License v1.0"

     6 * which accompanies this distribution, and is available

     7 * at the URL "http://www.eclipse.org/legal/epl-v10.html".

     8 *

     9 * Initial Contributors:

    10 * Nokia Corporation - initial contribution.

    11 *

    12 * Contributors:

    13 *

    14 * Description:  

    15 * naviengine_assp\naviengine.h

    16 * Definitions for NE1_TBVariant ASSP

    17 *

    18 */

    19 

    20 

    21 

    22 #ifndef __A32NAVIENGINE_H__

    23 #define __A32NAVIENGINE_H__

    24 #include <e32const.h>

    25 #include <e32hal.h>

    26 

    27 //-------------------------------------------------------------------

    28 // Constant conventions:

    29 //-------------------------------------------------------------------

    30 

    31 // KH       Hardware definition

    32 // KHw      4-byte word definition prefix

    33 // KHb      Byte definition prefix

    34 // KHt      Bit definition prefix

    35 // KHm      Mask definition prefix

    36 // KHs      Shift definition prefix

    37 // KHo      Offset definition prefix

    38 // KHwRo    Read-only register

    39 // KHwWo    Write-only register

    40 // KHwRw    Read/write register

    41 // KHwBase  Base address within memory map

    42 // _i       Input suffix

    43 // _o       Output suffix

    44 // _b       Input/output suffix

    45 //

    46 // ALL ASSP specific hardware registers should be defined in this file, not

    47 // in local files.  The register belongs to the ASSP, not the driver.

    48 

    49 //----------------------------------------------------------------------------

    50 // Memory map: physical addresses

    51 //----------------------------------------------------------------------------

    52 

    53 // These details are taken directly from the NaviEngine SoC TRM "S18599EJ1V0UM00.pdf"

    54 // Table 4-1 Address Map

    55 const TUint KHwBaseMPcorePrivatePhys = 0xc0000000; // Private MPcore region for SCU and Interrupt controller (8k address space)

    56 const TUint KHwDDR2RamBasePhys       = 0x80000000; // 256MB of DDR2 RAM sits here (in a 1GB address space)

    57 const TUint KHwPCIPhys               = 0x20000000; // PCI controller (128MB address space)

    58 const TUint KHwInternal              = 0x18000000; // Internal SoC peripherals reside in this area (16MB address space)

    59 

    60 // Table 4-2 AXI Address Map

    61 const TUint KHwAXI64IC2Phys          = 0x80000000; // AXI64 bus base address

    62 const TUint KHwSATAPhys              = 0x18016000; // SATA Controller

    63 const TUint KHwAXI64DMACPhys         = 0x18015000; // DMA Controller for the AXI64 bus

    64 const TUint KHwVideoPhys             = 0x18014000; // External Video Controller

    65 const TUint KHwDispPhys              = 0x18010000; // LCD/VGA display controller

    66 const TUint KHwSGXPhys               = 0x18000000; // SGX display controller

    67 

    68 // Table 4-3 AHB Address Map

    69 const TUint KHwCFWindow2Phys         = 0x18070000;

    70 const TUint KHwCFWindow1Phys         = 0x18060000;

    71 const TUint KHwCFWindow0Phys         = 0x18050000;

    72 const TUint KHwATA6_CS1Phys          = 0x18029000;

    73 const TUint KHwATA6_CS0Phys          = 0x18028000;

    74 const TUint KHwUSBHPhys              = 0x18024000; // Internal PCI controller memory window

    75 const TUint KHwAHB32PCI_USBPhys      = 0x18023000; // PCI controller for the internal USB controller

    76 const TUint KHwAHB32PCI_ExtPhys      = 0x18022000; // PCI controller for the external PCI bus

    77 const TUint KHwDDR2RegPhys           = 0x18021000; // DDR2 memory control registers

    78 const TUint KHwAHB0DMAC4Phys         = 0x18020000; // AHB bus DMA Controller 4

    79 const TUint KHwAHB0DMAC3Phys         = 0x1801f000; // AHB bus DMA Controller 3

    80 const TUint KHwAHB0DMAC2Phys         = 0x1801e000; // AHB bus DMA Controller 2

    81 const TUint KHwAHB0DMAC1Phys         = 0x1801d000; // AHB bus DMA Controller 1

    82 const TUint KHwAHB0DMAC0Phys         = 0x1801c000; // AHB bus DMA Controller 0

    83 const TUint KHwAHBEXDMACPhys         = 0x1801b000; // AHB bus DMA Controller on external bus

    84 const TUint KHwEXBUSPhys             = 0x18018000; // External Bus / NAND / CF

    85 

    86 // Table 4-4 APB Address Map

    87 const TUint KHwDTVIfPhys             = 0x1804C000; // Digital TV interface

    88 const TUint KHwAPB1Phys              = 0x18030000; // AHB32APB bus base address

    89 

    90 const TUint KHwPWM7Phys              = 0x1803AC00;

    91 const TUint KHwPWM6Phys              = 0x1803A800;

    92 const TUint KHwPWM5Phys              = 0x1803A400;

    93 const TUint KHwPWM4Phys              = 0x1803A000;

    94 const TUint KHwPWM3Phys              = 0x18039C00;

    95 const TUint KHwPWM2Phys              = 0x18039800;

    96 const TUint KHwPWM1Phys              = 0x18039400;

    97 const TUint KHwPWM0Phys              = 0x18039000;

    98 const TUint KHwGPIOPhys              = 0x18038000; // GPIO module

    99 const TUint KHwSYSCTRLPhys           = 0x18037C00; // System Control Unit

   100 const TUint KHweWDTPhys              = 0x18037800; // External Watchdog Timer

   101 const TUint KHwTimer5Phys            = 0x18037400; // Timers

   102 const TUint KHwTimer4Phys            = 0x18037000;

   103 const TUint KHwTimer3Phys            = 0x18036C00;

   104 const TUint KHwTimer2Phys            = 0x18036800;

   105 const TUint KHwTimer1Phys            = 0x18036400;

   106 const TUint KHwTimer0Phys            = 0x18036000;

   107 const TUint KHwUART7Phys             = 0x18035C00; // UARTs

   108 const TUint KHwUART6Phys             = 0x18035800;

   109 const TUint KHwUART5Phys             = 0x18035400;

   110 const TUint KHwUART4Phys             = 0x18035000;

   111 const TUint KHwUART3Phys             = 0x18034C00;

   112 const TUint KHwUART2Phys             = 0x18034800;

   113 const TUint KHwUART1Phys             = 0x18034400;

   114 const TUint KHwUART0Phys             = 0x18034000;

   115 const TUint KHwI2S3Phys              = 0x18033000; // I2S

   116 const TUint KHwI2S2Phys              = 0x18032C00;

   117 const TUint KHwI2S1Phys              = 0x18032800;

   118 const TUint KHwI2S0Phys              = 0x18032400;

   119 const TUint KHwI2CPhys               = 0x18032000; // I2C

   120 const TUint KHwCSI1Phys              = 0x18031800; // CSI

   121 const TUint KHwCSI0Phys              = 0x18031400;

   122 const TUint KHwSPDIFPhys             = 0x18031000; // SPDIF

   123 const TUint KHwSDPhys                = 0x18030000; // SD

   124 

   125 // Taken from the NE1-TB Hardware Specification "NE1-TB_HW-Spec_R1p0_20071221.pdf"

   126 // Section 5

   127 const TUint KHwFPGAPhys              = 0x04010000; // FPGA registers

   128 

   129 // Taken from an email Section 4 and email exchange with NEC

   130 const TUint KHwLANPhys               = 0x04000000; // SMCS 9118 LAN Controller

   131 

   132 

   133 //----------------------------------------------------------------------------

   134 // Memory map: linear addresses

   135 // This has to be consistent with HwBanks mappings in bootrom (see, ne1_tb.s).

   136 //----------------------------------------------------------------------------

   137 #ifdef __MEMMODEL_DIRECT__

   138 

   139 const TUint KHwBaseUart0            = KHwUART0Phys;              // serial port #0

   140 const TUint KHwBaseMPCorePrivate    = KHwBaseMPcorePrivatePhys;  // 4KB of private MPcore region for SCU and Interrupt controller

   141 const TUint KHwTimersBase           = KHwTimer0Phys;             // six SoC timers

   142 const TUint KHwDisplayBase          = KHwDispPhys;               // SoC display controller

   143 const TUint KHwBaseI2C              = KHwI2CPhys;                // I2C

   144 const TUint KHwFPGABase             = KHwFPGAPhys;               // FPGA registers

   145 const TUint KHwSPDIFBase            = KHwSPDIFPhys;              // SPDIF

   146 const TUint KHwBaseSDCtrl           = KHwSDPhys;                 // SD

   147 const TUint KDMACExBusBase          = KHwAHBEXDMACPhys;          // DMAC(4C) 4KB

   148 const TUint KDMAC32Base             = KHwAHB0DMAC0Phys;          // DMAC(8C) 20KB

   149 const TUint KHwDMAC64Base           = KHwAXI64DMACPhys;          // DMAC(4C) 4KB on AXI bus - 64bit

   150 const TUint KHwBaseEthernet         = KHwLANPhys;                // Ethernet

   151 const TUint KHwGPIOBase             = KHwGPIOPhys;               // GPIO

   152 const TUint KHwPciBase              = KHwAHB32PCI_ExtPhys;       // PCI Bridges

   153 const TUint KHwUsbHWindow           = KHwUSBHPhys;               // Internal PCI window

   154 //const TUint KHw xxx Base          = KHw xxx Phys;              // xxx

   155 

   156 #else

   157 

   158 const TLinAddr KHWIOBase            = 0xC6000000u;               // Base address of virtual address range used for HW mappings

   159 

   160 const TUint KHwBaseUart0            = KHWIOBase;                 //Bank # 0, ofset      0,  size 4K         // serial port #0                                                ///< Internal, clients get value from HCR

   161 const TUint KHwBaseMPCorePrivate    = KHWIOBase + 0x01000;       //Bank # 1, offset  1000h, size 2*4K       // 4KB of private MPcore region for SCU and Interrupt controller ///< Internal, clients get value from HCR

   162 const TUint KHwTimersBase           = KHWIOBase + 0x03000;       //Bank # 2, offset  3000h, size 2*K        // six SoC timers                                                ///< Internal, clients get value from HCR

   163 const TUint KHwDisplayBase          = KHWIOBase + 0x05000;       //Bank # 3, offset  4000h, size 4*K        // SoC display controller                                        ///< Internal, clients get value from HCR

   164 const TUint KHwBaseI2C              = KHWIOBase + 0x09000;       //Bank # 4, offset  9000h, size 2*4K       // I2C                                                           ///< Internal, clients get value from HCR

   165 const TUint KHwFPGABase             = KHWIOBase + 0x0B000;       //Bank # 5, offset  B000h, size 4K         // FPGA registers                                                ///< Internal, clients get value from HCR

   166 const TUint KHwSPDIFBase            = KHWIOBase + 0x0C000;       //Bank # 6, offset  C000h, size 4K         // SPDIF                                                         ///< Internal, clients get value from HCR

   167 const TUint KHwBaseSDCtrl           = KHWIOBase + 0x0D000;       //Bank # 7, offset  D000h, size 4K         // SD                                                            ///< Internal, clients get value from HCR

   168 const TUint KDMACExBusBase          = KHWIOBase + 0x0E000;       //Bank # 8, offset  D000h, size 6*4K = 24K // DMAC(4C) 4KB                                                  ///< Internal, clients get value from HCR

   169 const TUint KDMAC32Base             = KHWIOBase + 0x0F000;       //Bank # 9, offset  D000h, size 6*4K = 24K // DMAC(8C) 20KB                                                 ///< Internal, clients get value from HCR

   170 const TUint KHwBaseEthernet         = KHWIOBase + 0x14000;       //Bank #10, offset 14000h, size 4K         // Ethernet                                                      ///< Internal, clients get value from HCR

   171 const TUint KHwGPIOBase             = KHWIOBase + 0x15000;       //Bank #11, offset 15000h, size 4K         // GPIO                                                          ///< Internal, clients get value from HCR

   172 const TUint KHwPciBase              = KHWIOBase + 0x16000;       //Bank #12, offset 16000h, size 2*4K       // PCI Bridges                                                   ///< Internal, clients get value from HCR

   173 const TUint KHwUsbHWindow           = KHWIOBase + 0x18000;       //Bank #13, offset 18000h, size 2*4K       // Internal PCI window                                           ///< Internal, clients get value from HCR

   174 const TUint KHwDMAC64Base           = KHWIOBase + 0x1A000;       //Bank #14, offset 1A000h, size 4k         // DMAC(4C) 4KB on AXI bus - 64bit                               ///< Internal, clients get value from HCR

   175 //const TUint KHw xxx Base            = KHWIOBase + 0x1B000;     //Bank #15, offset 1B000h, size xK         // xxx                                                           ///< Internal, clients get value from HCR

   176 #endif

   177 

   178 

   179 

   180 

   181 const TUint KHwBaseUart1            = KHwBaseUart0         + 0x400;  // serial port #1               ///< Internal, clients get value from HCR

   182 const TUint KHwBaseUart2            = KHwBaseUart0         + 0x800;  // serial port #2               ///< Internal, clients get value from HCR

   183 const TUint KHwBaseSCU              = KHwBaseMPCorePrivate;          // Snoop Control Unit           ///< Internal, clients get value from HCR

   184 const TUint KHwBaseIntIf            = KHwBaseMPCorePrivate + 0x100;  // CPU interrupt interface      ///< Internal, clients get value from HCR

   185 const TUint KHwBaseGlobalIntDist    = KHwBaseMPCorePrivate + 0x1000; // Global Interrupt Distributer ///< Internal, clients get value from HCR

   186 const TUint KHwWatchdog             = KHwTimersBase        + 0x1800; // eWDT (Watchdog Timer)        ///< Internal, clients get value from HCR

   187 const TUint KHwSystemCtrlBase       = KHwTimersBase        + 0x1c00; // system control unit          ///< Internal, clients get value from HCR

   188 const TUint KHwBaseI2S0             = KHwBaseI2C           + 0x400;  // I2S0                         ///< Internal, clients get value from HCR

   189 const TUint KHwBaseI2S1             = KHwBaseI2S0          + 0x400;  // I2S1                         ///< Internal, clients get value from HCR

   190 const TUint KHwBaseI2S2             = KHwBaseI2S0          + 0x800;  // I2S2                         ///< Internal, clients get value from HCR

   191 const TUint KHwBaseI2S3             = KHwBaseI2S0          + 0xC00;  // I2S3                         ///< Internal, clients get value from HCR

   192 const TUint KHwBaseCSI0             = KHwSPDIFBase         + 0x400;  // CSI0                         ///< Internal, clients get value from HCR

   193 const TUint KHwBaseCSI1             = KHwBaseCSI0          + 0x400;  // CSI1                         ///< Internal, clients get value from HCR

   194 const TUint KHwLCDDispBase          = KHwFPGABase          + 0x0400; // LCD display                  ///< Internal, clients get value from HCR

   195 const TUint KHwTSPBase              = KHwFPGABase          + 0x0600; // Digitiser                    ///< Internal, clients get value from HCR

   196 const TUint KHwPciBridgeExtern      = KHwPciBase;                    // External PCI Bridge          ///< Internal, clients get value from HCR

   197 const TUint KHwPciBridgeUsb         = KHwPciBase           + 0x1000; // UsbHost dedicated PCI Bridge ///< Internal, clients get value from HCR

   198 

   199 

   200 

   201 //----------------------------------------------------------------------------

   202 // CPU interrupt interface registers' addresses.

   203 //----------------------------------------------------------------------------

   204 const TUint KHwCIIControl     = KHwBaseIntIf + 0x00; // Control

   205 const TUint KHwCIIPrioMask    = KHwBaseIntIf + 0x04; // Priority mask

   206 const TUint KHwCIIBinPoint    = KHwBaseIntIf + 0x08; // Binary point

   207 const TUint KHwCIIIntAck      = KHwBaseIntIf + 0x0C; // Interrupt acknowledge RO

   208 const TUint KHwCIIEndOfInt    = KHwBaseIntIf + 0x10; // End of interrupt WO

   209 const TUint KHwCIIPrioRun     = KHwBaseIntIf + 0x14; // Running Interrupt RO

   210 const TUint KHwCIIHighPend    = KHwBaseIntIf + 0x18; // Highest pending interrupt RO

   211 

   212 const TUint KHoCIIIntAck      = 0x0C;                // Interrupt acknowledge RO

   213 const TUint KHoCIIEndOfInt    = 0x10;                // End of interrupt WO

   214 

   215 //----------------------------------------------------------------------------

   216 // Global Interrupt Distributor registers' addresses

   217 //----------------------------------------------------------------------------

   218 const TUint KHoGidControl         = KHwBaseGlobalIntDist + 0x000; // Control Register. Holds enable bit.

   219 const TUint KHoGidType            = KHwBaseGlobalIntDist + 0x004; // Controller type. Read only register

   220 const TUint KHoGidIntEnableBase   = KHwBaseGlobalIntDist + 0x100; // Writing into these registers will enable appropriate interrupt(s), 1 bit per interrupt

   221 const TUint KHoGidIntDisableBase  = KHwBaseGlobalIntDist + 0x180; // Writing into these registers will disable appropriate interrupt(s), 1 bit per interrupt

   222 const TUint KHoGidPendSetBase     = KHwBaseGlobalIntDist + 0x200; // Writing into these registers will return appropriate interrupt(s) from Pending to Inactive state. Active state is not modified, 1 bit per interrupt

   223 const TUint KHoGidPendClearBase   = KHwBaseGlobalIntDist + 0x280; // Writing into these registers will put appropriate interrupt(s) into  Pending state, 1 bit per interrupt

   224 const TUint KHoGidActiveBase      = KHwBaseGlobalIntDist + 0x300; // Indicates if corresponding interrupt is active. Ints 0-31 (the first reg.) are aliased for each CPU, 1 bit per interrupt

   225 const TUint KHoGidPriorityBase    = KHwBaseGlobalIntDist + 0x400; // Priority of the interrupts, 8 bits per int, only 4 used

   226 const TUint KHoGidTargetBase      = KHwBaseGlobalIntDist + 0x800; // Interrupt CPU targets, 8 bits per int, only 4 used

   227 const TUint KHoGidConfigBase      = KHwBaseGlobalIntDist + 0xC00; // Interrupt configuration register: edge or leveled; 1-N or N-N software model,  2 bits per interrupt

   228 const TUint KHoGidSoftwareTrigger = KHwBaseGlobalIntDist + 0xF00; // Software interrupt Trigger Register. A single register for all ints.

   229 

   230 //----------------------------------------------------------------------------

   231 // SystemControlUnit registers' addresses

   232 //----------------------------------------------------------------------------

   233 const TUint KHoSCUClockMaskCtrl                     = 0x80; // Mask control

   234 const TUint KHoSCUDisplayDCLKCtrl                   = 0x8c; // Display DCLK control

   235 const TUint KHw60HzDisplay                          = 11;

   236 

   237 // Divide I2S CLK Control Register

   238 const TUint KHoSCUDivideI2SCLKCtrl = 0x94;

   239 const TUint KHtSCUDivI2SCLKCtrl_I2S0MCLK_SEL        = (1<<4); // Selects the I2S0 MCLK source: 1-SPDIF, 0-external input.

   240 const TUint KHsSCUDivI2SCLKCtrl_I2S0MCLK_FREQ       = 0;      // shift for the MCK clock frequency for I2S0 unit

   241 const TUint KHsSCUDivI2SCLKCtrl_I2S1MCLK_FREQ       = 8;      // shift for the MCK clock frequency for I2S1 unit

   242 const TUint KHsSCUDivI2SCLKCtrl_I2S2MCLK_FREQ       = 16;     // shift for the MCK clock frequency for I2S2 unit

   243 const TUint KHsSCUDivI2SCLKCtrl_I2S3MCLK_FREQ       = 24;     // shift for the MCK clock frequency for I2S3 unit

   244 // values for MCK clock frequency

   245 const TUint KHSCUDivI2SCLKCtrl_I2SMCLK_FREQ36_864M  = 0;

   246 const TUint KHSCUDivI2SCLKCtrl_I2SMCLK_FREQ24_576M  = 1;

   247 const TUint KHSCUDivI2SCLKCtrl_I2SMCLK_FREQ18_432M  = 2;

   248 const TUint KHSCUDivI2SCLKCtrl_I2SMCLK_FREQ33_8688M = 4;

   249 const TUint KHSCUDivI2SCLKCtrl_I2SMCLK_FREQ22_5792M = 5;

   250 const TUint KHSCUDivI2SCLKCtrl_I2SMCLK_FREQ16_9344M = 6;

   251 

   252 //----------------------------------------------------------------------------

   253 // I2S Register Addresses

   254 //----------------------------------------------------------------------------

   255 const TUint KHoI2SCtrl              = 0x00;    // I2S Control register offset

   256 const TUint KHtI2SCtrl_MSMODE       = (1<<28); // master/slave mode (1-master, 0-slave)

   257 const TUint KHtI2SCtrl_TEN          = (1<<25); // transmission enable (1-enable, 0-disable)

   258 const TUint KHtI2SCtrl_REN          = (1<<24); // reception (1-enable, 0-disable)

   259 const TUint KHsI2SCtrl_FCKLKSEL     = 16;      // [3:0] clock select mask (Sampling fq)

   260 const TUint KHsI2SCtrl_FSMODE       = 12;      // [1:0] number of SCLK cycles in one frame (1WS cycle)

   261 const TUint KHsI2SCtrl_FORMAT       = 8;       // [2:0] transfer format (I2S = 100b)

   262 const TUint KHtI2SCtrl_INVALID      = (1<<6);  // Invalid data format(1 - outputs "1" as invalid data)

   263 const TUint KHsI2SCtrl_DLENGTH      = 0;       // [4:0] sampling data length

   264 

   265 const TUint KHoI2SFifoCtrl          = 0x04;    // I2S Fifo Control register offset

   266 const TUint KHtI2SFifoCtrl_TDMAEN   = (1<<23); // Enables DMA req on transmit side

   267 const TUint KHtI2SFifoCtrl_TFIFOCLR = (1<<22); // transmit FIFO initialisation

   268 const TUint KHsI2SFifoCtrl_TFIFOLT  = 19;      // [2:0] L-ch transmit FIFO trigger level (0-3: 2-16 word space avl)

   269 const TUint KHsI2SFifoCtrl_TFIFORT  = 16;      // [2:0] R-ch transmit FIFO trigger level (0-3: 2-16 word space avl)

   270 const TUint KHtI2SFifoCtrl_RDMAEN   = (1<<7);  // Enables DMA req on receive side

   271 const TUint KHtI2SFifoCtrl_RFIFOCLR = (1<<6);  // receive FIFO initialisation

   272 const TUint KHsI2SFifoCtrl_RFIFOLT  = 3;       // [2:0] L-ch receive FIFO-full trigger level (0-3: 2-16 word space avl)

   273 const TUint KHsI2SFifoCtrl_RFIFORT  = 0;       // [2:0] R-ch receive FIFO-full trigger level (0-3: 2-16 word space avl)

   274 

   275 const TUint KHoI2SFifoSts           = 0x08;    // I2S Fifo status register offset

   276 const TUint KHtI2SFifoSts_TFL_FULL	= (1<<17); // L-ch transmit FIFO full (32 words)

   277 const TUint KHtI2SFifoSts_TFR_FULL	= (1<<16); // R-ch transmit FIFO full (32 words)

   278 const TUint KHtI2SFifoSts_RFL_EMPTY = (1<<1);  // L-ch receive FIFO empty

   279 const TUint KHtI2SFifoSts_RFR_EMPTY = (1<<0);  // R-ch receive FIFO empty

   280 

   281 const TUint KHoI2SIntFlg            = 0x0C;    // I2S interrupt flag register offset

   282 const TUint KHtI2SIntFlg_TFLURINT	= (1<<19); // L-ch transmit FIFO underrun

   283 const TUint KHtI2SIntFlg_TFLEINT    = (1<<18); // L-ch transmit FIFO reached the empty trigger level

   284 const TUint KHtI2SIntFlg_TFRURINT   = (1<<17); // R-ch transmit FIFO underrun

   285 const TUint KHtI2SIntFlg_TFREINT    = (1<<16); // R-ch transmit FIFO reached the empty trigger level

   286 const TUint KHtI2SIntFlg_RFLORINT   = (1<<3);  // L-ch receive FIFO overrun

   287 const TUint KHtI2SIntFlg_RFLFINT    = (1<<2);  // L-ch receive FIFO reached the full trigger level

   288 const TUint KHtI2SIntFlg_RFRORINT   = (1<<1);  // R-ch receive FIFO overrun

   289 const TUint KHtI2SIntFlg_RFRFINT    = (1<<0);  // R-ch receive FIFO reached the full trigger level

   290 

   291 const TUint KHoI2SIntMask           = 0x10;    // I2S interrupt mask register offset

   292 const TUint KHtI2SIntMask_TFLURINT  = (1<<19); // L-ch transmit FIFO underrun int enable

   293 const TUint KHtI2SIntMask_TFLEINT   = (1<<18); // L-ch transmit FIFO reached the empty trigger level int enable

   294 const TUint KHtI2SIntMask_TFRURINT  = (1<<17); // R-ch transmit FIFO underrun int enable

   295 const TUint KHtI2SIntMask_TFREINT   = (1<<16); // R-ch transmit FIFO reached the empty trigger level int enable

   296 const TUint KHtI2SIntMask_RFLORINT  = (1<<3);  // L-ch receive FIFO overrun int enable

   297 const TUint KHtI2SIntMask_RFLFINT   = (1<<2);  // L-ch receive FIFO reached the full trigger level int enable

   298 const TUint KHtI2SIntMask_RFRORINT  = (1<<1);  // R-ch receive FIFO overrun int enable

   299 const TUint KHtI2SIntMask_RFRFINT   = (1<<0);  // R-ch receive FIFO reached the full trigger level int enable

   300 const TUint KHmI2SIntMask_ALL       = 0xF000F; // All interrupts mask

   301 

   302 const TUint KHoI2SRx                = 0x20;    // I2S receive data FIFO register offset

   303 const TUint KHoI2STx                = 0x30;    // I2S transmit data FIFO register offset

   304 

   305 //----------------------------------------------------------------------------

   306 //FPGA Register Addresses

   307 //----------------------------------------------------------------------------

   308 const TUint KHoLCDControl      = 0x400;

   309 const TUint KHoSystemPowerDown = 0xF10;

   310 

   311 const TUint KHwIDMODE          = KHwFPGABase+0x0810;

   312 const TUint KHmUserSwitches    = 0x3C00;

   313 const TUint KHsUserSwitches    = 10;

   314 const TUint KHmLcdSwitches     = 0x3000;

   315 const TUint KHsLcdSwitches     = 12;

   316 const TUint KHmKeyConfigSwitch = 0x800;

   317 const TUint KHsKeyConfigSwitch = 11;

   318 

   319 // There are 4 red LEDs that can be controlled by the FPGA

   320 // Each LED has a bit in the register, where 0==off and 1==on

   321 const TUint KHoFpgaLeds        = 0x0A06;

   322 const TUint KHwFpgaLeds        = KHwFPGABase+KHoFpgaLeds;

   323 

   324 const TUint KHmFpgaLeds        = 0xF;

   325 

   326 const TUint KHsFpgaLed0        = 0x0;

   327 const TUint KHsFpgaLed1        = 0x1;

   328 const TUint KHsFpgaLed2        = 0x2;

   329 const TUint KHsFpgaLed3        = 0x3;

   330 

   331 const TUint KHtFpgaLed0        = 1 << KHsFpgaLed0;

   332 const TUint KHtFpgaLed1        = 1 << KHsFpgaLed1;

   333 const TUint KHtFpgaLed2        = 1 << KHsFpgaLed2;

   334 const TUint KHtFpgaLed3        = 1 << KHsFpgaLed3;

   335 

   336 //----------------------------------------------------------------------------

   337 //CSI Register Addresses

   338 //----------------------------------------------------------------------------

   339 const TUint KHoCSIModeControl       = 0x00;  // CSI Mode Control Register

   340 const TUint KHsCSIModeTWait         = 16;    // CSI waiting time for transaction shift

   341 const TUint KHtCSIModeEnable        = 1<<7;  // CSI enable

   342 const TUint KHtCSIModeTrEnable      = 1<<6;  // CSI transmission and reception mode select

   343 const TUint KHtCSIModeDataLen       = 1<<5;  // CSI Data length select: 0-8bits, 1-16bits

   344 const TUint KHtCSIModeTransferDir   = 1<<4;  // CSI Transfer direction mode: 0-MSB first, 1-LSB first

   345 const TUint KHtCSIModeTransferState = 1<<0;  // CSI Transfer state indication flag: 0-idle first, 1-transmission

   346 

   347 const TUint KHoCSIClockSelect       = 0x04;  // CSI Clock Select Register

   348 const TUint KHtCSIClockSelectSSE    = 1<<9;  // SS pin enable

   349 const TUint KHtCSIClockSelectSSPol  = 1<<8;  // SS pin polarity select (0: SS pin low active,  1: SS pin high active)

   350 const TUint KHtCSIClockSelectCKP    = 1<<4;  // Clock polarity select

   351 const TUint KHtCSIClockSelectDAP    = 1<<3;  // Clock phase select

   352 

   353 const TUint KHsCSIClockSelect       = 0;     // Communication clock select shift CKS[2:0]

   354 const TUint KHCSIClockValPCLKdiv4   = 0;     //  1/4 PCLK (master mode)   16.67 MHz

   355 const TUint KHCSIClockValPCLKdiv16  = 1;     //  1/16 PCLK (master mode)	4.17 MHz

   356 const TUint KHCSIClockValPCLKdiv32  = 2;     //  1/32 PCLK (master mode)	2.08 MHz

   357 const TUint KHCSIClockValPCLKdiv64  = 3;     //  1/64 PCLK (master mode)	1.04 MHz

   358 const TUint KHCSIClockValPCLKdiv128 = 4;     //  1/128 PCLK (master mode)	 521 kHz

   359 const TUint KHCSIClockValPCLKdiv256 = 5;     //  1/256 PCLK (master mode)	 260 kHz

   360 const TUint KHCSIClockValPCLKdiv512 = 6;     //  1/512 PCLK (master mode)	 130 kHz

   361 const TUint KHCSIClockValSlave      = 7;     //  SCKI (slave mode)

   362 

   363 const TUint KHoCSIControl           = 0x08;  // CSI Control Register

   364 const TUint KHtCSIControlCSIRst     = 1<<28; // CSI unit reset

   365 const TUint KHtCSIControlTxTrgEn    = 1<<27; // Permission of CSI_FIFOTRG.bit10-8(T_TRG[2:0]) operation

   366 const TUint KHtCSIControlTxFifoFull = 1<<26; // State of Tx FIFO buffer

   367 const TUint KHtCSIControlTxDMAE     = 1<<24; // Tx DMA mode

   368 const TUint KHtCSIControlSSMon      = 1<<21; // SS signal monitor

   369 const TUint KHtCSIControlRxTrgEn    = 1<<19; // Permission of CSI_FIFOTRG.bit2-0(R_TRG[2:0]) operation

   370 const TUint KHtCSIControlRxFifoFull = 1<<18; // State of Rx FIFO buffer

   371 const TUint KHtCSIControlRxDMAE     = 1<<16; // Rx DMA mode

   372 

   373 const TUint KHtCSIControlSSDnIE     = 1<<15; // SS signal negative-edge interrupt (CSI_INT.bit15(SS_DN)) enable

   374 const TUint KHtCSIControlSSUpIE     = 1<<14; // SS signal positive-edge interrupt (CSI_INT.bit14(SS_UP)) enable

   375 const TUint KHtCSIControlTxUndIE    = 1<<13; // Tx FIFO buffer under-run error interrupt (CSI_INT.bit13(UNDER)) enable

   376 const TUint KHtCSIControlRxOvfIE    = 1<<12; // Rx FIFO buffer overflow error interrupt (CSI_INT.bit12(OVERF)) enable

   377 const TUint KHtCSIControlTEndIE     = 1<<8;  // Transmission end interrupt (CSI_INT.bit8(CSIEND)) enable

   378 const TUint KHtCSIControlTxTrgIE    = 1<<4;  // Tx trigger level interrupt (CSI_INT.bit4(T_TRGR)) enable

   379 const TUint KHtCSIControlRxTrgIE    = 1<<0;  // Rx trigger level interrupt (CSI_INT.bit0(R_TRGR bit) enable

   380 

   381 const TUint KHoCSIIntStatus   = 0x0C;  // CSI Interrupt Status Register

   382 const TUint KHtCSIIntStatusSSDn    = 1<<15;  // SS signal negative-edge interrupt

   383 const TUint KHtCSIIntStatusSSUp    = 1<<14;  // SS signal positive-edge interrupt

   384 const TUint KHtCSIIntStatusTxUnd   = 1<<13;  // Tx FIFO buffer under-run error interrupt

   385 const TUint KHtCSIIntStatusRxOvf   = 1<<12;  // Rx FIFO buffer overflow error interrupt

   386 const TUint KHtCSIIntStatusTEnd    = 1<<8;   // Transmission end interrupt

   387 const TUint KHtCSIIntStatusTxTrgIE = 1<<4;   // Tx trigger level interrupt

   388 const TUint KHtCSIIntStatusRxTrgIE = 1<<0;   // Rx trigger level interrupt

   389 

   390 const TUint KHoCSIIFifoL           = 0x10;   // CSI Receive FIFO level indicate Register

   391 const TUint KHoCSIOFifoL           = 0x14;   // CSI Transmit FIFO level indicate Register

   392 const TUint KHoCSIIFifo            = 0x18;   // CSI Receive FIFO Window Register

   393 const TUint KHoCSIOFifo            = 0x1C;   // CSI Transmit FIFO Window Register

   394 const TUint KHwCSIFifoLMax         = 32;     // maximum amount of data in the CSI FIFO

   395 

   396 const TUint KHoCSIFifoTrgLvl       = 0x20;   // CSI FIFO Trigger Level Register

   397 const TUint KHsCSITxFifoTrgLvl     = 8;      // transmit FIFO trigger level shift [10:8]

   398 const TUint KHsCSIRxFifoTrgLvl     = 0;      // receive FIFO trigger level shift [2:0]

   399 

   400 //----------------------------------------------------------------------------

   401 // GPIO Register Addresses

   402 //----------------------------------------------------------------------------

   403 const TUint KHwRwGpio_Port_Control_Enable   = KHwGPIOBase + 0x00;

   404 const TUint KHwWoGpio_Port_Control_Disable  = KHwGPIOBase + 0x04;

   405 const TUint KHwWoGpio_Port_Set_Clear_Hi     = KHwGPIOBase + 0x08;

   406 const TUint KHwWoGpio_Port_Set_Clear_Lo     = KHwGPIOBase + 0x0c;

   407 const TUint KHwRoGpio_Port_Value            = KHwGPIOBase + 0x10;

   408 const TUint KHwRwGpio_Int                   = KHwGPIOBase + 0x14;

   409 const TUint KHwRwGpio_Int_Enable            = KHwGPIOBase + 0x18;

   410 const TUint KHwWoGpio_Int_Disable           = KHwGPIOBase + 0x1c;

   411 const TUint KHwRwGpio_Int_Hold              = KHwGPIOBase + 0x20;

   412 const TUint KHwRwGpio_Int_Mode0             = KHwGPIOBase + 0x24;

   413 const TUint KHwRwGpio_Int_Mode1             = KHwGPIOBase + 0x28;

   414 const TUint KHwRwGpio_Int_Mode2             = KHwGPIOBase + 0x2c;

   415 const TUint KHwRwGpio_Int_Mode3             = KHwGPIOBase + 0x30;

   416 const TUint KHwRwGpi_Polarity_Invert        = KHwGPIOBase + 0x38;

   417 const TUint KHwWoGpi_Polarity_Reset         = KHwGPIOBase + 0x3c;

   418 const TUint KHwRwGpo_Polarity_Invert        = KHwGPIOBase + 0x40;

   419 const TUint KHwWoGpo_Polarity_Reset         = KHwGPIOBase + 0x44;

   420 

   421 const TUint KGpio_Ethernet_Int_Pin          = 20;

   422 

   423 //----------------------------------------------------------------------------

   424 // eWDT Register Addresses

   425 //----------------------------------------------------------------------------

   426 const TUint KHwWatchdog_WDTCNT (KHwWatchdog +  0); // Control register

   427 const TUint KHwWatchdog_WDTSET (KHwWatchdog +  4); // Period setting register

   428 const TUint KHwWatchdog_WDTTIM (KHwWatchdog +  8); // Lapsed time register

   429 const TUint KHwWatchdog_WDTINT (KHwWatchdog + 12); // Interrupt register

   430 

   431 //----------------------------------------------------------------------------

   432 // Baud Rate Divisor values

   433 //----------------------------------------------------------------------------

   434 const TUint KBaudRateDiv_50      = 0;

   435 const TUint KBaudRateDiv_75      = 0;

   436 const TUint KBaudRateDiv_110     = 0;

   437 const TUint KBaudRateDiv_134     = 0;

   438 const TUint KBaudRateDiv_150     = 55417;

   439 const TUint KBaudRateDiv_300     = 27708;

   440 const TUint KBaudRateDiv_600     = 13854;

   441 const TUint KBaudRateDiv_1200    = 6927;

   442 const TUint KBaudRateDiv_1800    = 4618;

   443 const TUint KBaudRateDiv_2000    = 4156;

   444 const TUint KBaudRateDiv_2400    = 3464;

   445 const TUint KBaudRateDiv_3600    = 2309;

   446 const TUint KBaudRateDiv_4800    = 1732;

   447 const TUint KBaudRateDiv_7200    = 1155;

   448 const TUint KBaudRateDiv_9600    = 866;

   449 const TUint KBaudRateDiv_19200   = 433;

   450 const TUint KBaudRateDiv_38400   = 216;

   451 const TUint KBaudRateDiv_57600   = 144;

   452 const TUint KBaudRateDiv_115200  = 72;

   453 const TUint KBaudRateDiv_230400  = 36;

   454 

   455 const TUint KBaudRateDiv_default = 72; // Set to KBaudRateDiv_115200 but h2inc.pl doesn't support token replacement.

   456 

   457 //----------------------------------------------------------------------------

   458 // Memory Layout addresses for BootLoader / bootstrap interaction

   459 //----------------------------------------------------------------------------

   460 

   461 const TUint KRamTargetAddr                = 0x88000000;      // Phys. addr. of the image to be started by bootloader.

   462 const TUint KCoreLoaderAddress            = 0x8D000000;      // base of ram + 208MB

   463 

   464 const TUint xKMega                        = (1024*1024);     // we can't use KMega because h2inc won't resolve tokens from other includes

   465 const TLinAddr KNORFlashTargetAddr        = 0x00000000;      // Onboard NOR flash starts at phys addr 0x0

   466 const TLinAddr KNORFlashTargetSize        = ( 64 * xKMega);  // and is 64MB is size

   467 const TLinAddr KRamTargetSize             = (128 * xKMega);  // Reserved RAM starts at phys addr 0x88000000 and is 128MB is size

   468 

   469 // The layout of the onboard NOR is

   470 // [bootloader][configblock][flashedimage][reserved]

   471 const TLinAddr KNORFlashMaxBootloaderSize = (5 * xKMega);

   472 const TLinAddr KNORFlashMaxImageSize      = KNORFlashTargetSize - KNORFlashMaxBootloaderSize;

   473 

   474 //----------------------------------------------------------------------------

   475 // Restart Reason Codes

   476 //----------------------------------------------------------------------------

   477 

   478 // Restart types (bits 31-29)

   479 const TUint KmRestartReasonsActions            = 0xE0000000; // Bits 31 to 29

   480 

   481 // These three bits are indications for the bootloader to perform some activity

   482 const TUint KtRestartReasonHardRestart         = 0x80000000; // Bit31 back to bootloader

   483 const TUint KtRestartReasonSoftRestart         = 0x40000000; // Bit30 back to same image (will need image location too)

   484 const TUint KtRestartReasonBootRestart         = 0x20000000; // Bit29 back into new image (will need image location too)

   485 

   486 // This bit is an indicator for ane image to detect it is being warm booted

   487 const TUint KtRestartReasonWarmBoot            = 0x10000000; // Bit28 this boot is "warm"

   488 

   489 // Image locations (bits 27-20)

   490 const TUint KmRestartImageLocations            = 0x0FF00000; // Bits 27 to 20

   491 const TUint KtRestartReasonRAMImage            = 0x08000000; // Bit27

   492 const TUint KtRestartReasonNORImage            = 0x04000000; // Bit26

   493 const TUint KtRestartReasonNANDImage           = 0x02000000; // Bit25

   494 const TUint KtRestartReasonONENANDImage        = 0x01000000; // Bit24

   495 const TUint KtRestartReasonSIBLEYImage         = 0x00800000; // Bit23

   496 const TUint KtRestartReasonOTAUpgrade          = 0x00400000; // Bit22

   497 const TUint KtRestartReasonCoreLdr             = 0x00200000; // Bit21  This platform specific reason introduced to start SMP enabled CoreLdr

   498 

   499 // Restart startup Mode (bits 19-16)

   500 const TUint KmRestartStartupModes              = 0x000F0000; // Bits 19 to 16

   501 const TUint KsRestartStartupModes              = 16;

   502 const TUint KRestartStartupModesSize           = 4;          // size in bits

   503 

   504 // Custom restart reasons (bits 15-8)

   505 const TUint KmRestartCustomRestartReasons      = 0x0000FF00; // Bits 15 to 8

   506 const TUint KsRestartCustomRestartReasons      = 8;

   507 const TUint KRestartCustomRestartReasonsSize   = 8;          // size in bits

   508 

   509 // Define USB loader restart (after USB link dropped)

   510 const TUint KtRestartCustomRestartUSBLoader    = 0x00008000; // Bit 15

   511 const TUint KtRestartCustomRestartMemCheck     = 0x00004000; // Bit 14

   512 const TUint KtRestartCustomRestartMemCheckPass = 0x00002000; // Bit 13

   513 

   514 // Mask of all the bits used during the memory test (but not the start)

   515 const TUint KmRestartCustomRestartMemCheckBits = 0x00003F00; // Bits 13 to 8

   516 

   517 

   518 // Gap (bits 7-0)

   519 

   520 #endif